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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [sw/] [mor1kx/] [int.c] - Diff between revs 38 and 48

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Rev 38 Rev 48
/*
/*
 *
 *
 * User interrupt handler software for OR1200
 * User interrupt handler software for OR1200
 *
 *
 */
 */
 
 
#include "mor1kx-utils.h"
#include "mor1kx-utils.h"
#include "spr-defs.h"
#include "spr-defs.h"
#include "int.h"
#include "int.h"
 
 
/* Interrupt handlers table */
/* Interrupt handlers table */
struct ihnd int_handlers[MAX_INT_HANDLERS];
struct ihnd int_handlers[MAX_INT_HANDLERS];
 
 
/* Initialize routine */
/* Initialize routine */
int int_init()
int int_init()
{
{
  int i;
  int i;
 
 
  for(i = 0; i < MAX_INT_HANDLERS; i++) {
  for(i = 0; i < MAX_INT_HANDLERS; i++) {
    int_handlers[i].handler = 0;
    int_handlers[i].handler = 0;
    int_handlers[i].arg = 0;
    int_handlers[i].arg = 0;
  }
  }
 
 
  return 0;
  return 0;
}
}
 
 
/* Add interrupt handler */
/* Add interrupt handler */
int int_add(unsigned long irq, void (* handler)(void *), void *arg)
int int_add(unsigned long irq, void (* handler)(void *), void *arg)
{
{
  if(irq >= MAX_INT_HANDLERS)
  if(irq >= MAX_INT_HANDLERS)
    return -1;
    return -1;
 
 
  int_handlers[irq].handler = handler;
  int_handlers[irq].handler = handler;
  int_handlers[irq].arg = arg;
  int_handlers[irq].arg = arg;
 
 
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << irq));
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << irq));
 
 
  return 0;
  return 0;
}
}
 
 
/* Disable interrupt */
/* Disable interrupt */
int int_disable(unsigned long irq)
int int_disable(unsigned long irq)
{
{
  if(irq >= MAX_INT_HANDLERS)
  if(irq >= MAX_INT_HANDLERS)
    return -1;
    return -1;
 
 
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << irq));
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << irq));
 
 
  return 0;
  return 0;
}
}
 
 
/* Enable interrupt */
/* Enable interrupt */
int int_enable(unsigned long irq)
int int_enable(unsigned long irq)
{
{
  if(irq >= MAX_INT_HANDLERS)
  if(irq >= MAX_INT_HANDLERS)
    return -1;
    return -1;
 
 
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << irq));
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << irq));
 
 
  return 0;
  return 0;
}
}
 
 
/* Main interrupt handler */
/* Main interrupt handler */
void int_main()
void int_main()
{
{
  unsigned long picsr = mfspr(SPR_PICSR);
  unsigned long picsr = mfspr(SPR_PICSR);
  unsigned long i = 0;
  unsigned long i = 0;
 
 
  mtspr(SPR_PICSR, 0);
  mtspr(SPR_PICSR, 0);
 
 
  while(i < 32) {
  while(i < 32) {
    if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
    if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
      (*int_handlers[i].handler)(int_handlers[i].arg);
      (*int_handlers[i].handler)(int_handlers[i].arg);
#ifdef OR1200_INT_CHECK_BIT_CLEARED
#ifdef OR1200_INT_CHECK_BIT_CLEARED
      // Ensure PICSR bit is cleared, incase it takes some time for the
      // Ensure PICSR bit is cleared, incase it takes some time for the
      // IRQ line going low to propagate back to PIC
      // IRQ line going low to propagate back to PIC
      while (mfspr(SPR_PICSR) & (0x00000001L << i))
      while (mfspr(SPR_PICSR) & (0x00000001L << i))
#endif
#endif
              mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(0x00000001L << i));
              mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(0x00000001L << i));
    }
    }
    i++;
    i++;
  }
  }
}
}
 
 
 
 
void int_clear_all_pending(void)
void int_clear_all_pending(void)
{
{
  // Clear all pending interrupts in the PICSR
  // Clear all pending interrupts in the PICSR
  mtspr(SPR_PICSR, 0);
  mtspr(SPR_PICSR, 0);
}
}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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