# TCL File Generated by Component Editor 13.1
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# TCL File Generated by Component Editor 14.0
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# Sun Mar 30 12:22:06 CEST 2014
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# Mon Aug 18 22:50:23 CEST 2014
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# DO NOT MODIFY
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# DO NOT MODIFY
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#
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#
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# ao486 "ao486" v1.0
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# ao486 "ao486" v1.0
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# 2014.03.30.12:22:06
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# 2014.08.18.22:50:23
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#
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#
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#
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#
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#
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#
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# request TCL package from ACDS 13.1
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# request TCL package from ACDS 14.0
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#
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#
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package require -exact qsys 13.1
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package require -exact qsys 14.0
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#
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#
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# module ao486
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# module ao486
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#
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#
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set_module_property DESCRIPTION ""
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set_module_property DESCRIPTION ""
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set_module_property NAME ao486
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set_module_property NAME ao486
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set_module_property VERSION 1.0
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP ao486
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set_module_property GROUP ao486
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set_module_property AUTHOR ""
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME ao486
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set_module_property DISPLAY_NAME ao486
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property EDITABLE true
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set_module_property ANALYZE_HDL AUTO
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set_module_property REPORT_TO_TALKBACK false
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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#
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# file sets
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# file sets
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#
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL ao486
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL ao486
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file ao486.v VERILOG PATH ao486.v TOP_LEVEL_FILE
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add_fileset_file ao486.v VERILOG PATH ao486.v TOP_LEVEL_FILE
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add_fileset_file avalon_io.v VERILOG PATH avalon_io.v
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add_fileset_file avalon_io.v VERILOG PATH avalon_io.v
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add_fileset_file defines.v VERILOG PATH defines.v
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add_fileset_file defines.v VERILOG PATH defines.v
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add_fileset_file exception.v VERILOG PATH exception.v
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add_fileset_file exception.v VERILOG PATH exception.v
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add_fileset_file global_regs.v VERILOG PATH global_regs.v
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add_fileset_file global_regs.v VERILOG PATH global_regs.v
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add_fileset_file condition.v VERILOG PATH pipeline/condition.v
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add_fileset_file condition.v VERILOG PATH pipeline/condition.v
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add_fileset_file decode.v VERILOG PATH pipeline/decode.v
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add_fileset_file decode.v VERILOG PATH pipeline/decode.v
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add_fileset_file decode_commands.v VERILOG PATH pipeline/decode_commands.v
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add_fileset_file decode_commands.v VERILOG PATH pipeline/decode_commands.v
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add_fileset_file decode_prefix.v VERILOG PATH pipeline/decode_prefix.v
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add_fileset_file decode_prefix.v VERILOG PATH pipeline/decode_prefix.v
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add_fileset_file decode_ready.v VERILOG PATH pipeline/decode_ready.v
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add_fileset_file decode_ready.v VERILOG PATH pipeline/decode_ready.v
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add_fileset_file decode_regs.v VERILOG PATH pipeline/decode_regs.v
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add_fileset_file decode_regs.v VERILOG PATH pipeline/decode_regs.v
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add_fileset_file execute.v VERILOG PATH pipeline/execute.v
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add_fileset_file execute.v VERILOG PATH pipeline/execute.v
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add_fileset_file execute_commands.v VERILOG PATH pipeline/execute_commands.v
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add_fileset_file execute_commands.v VERILOG PATH pipeline/execute_commands.v
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add_fileset_file execute_divide.v VERILOG PATH pipeline/execute_divide.v
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add_fileset_file execute_divide.v VERILOG PATH pipeline/execute_divide.v
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add_fileset_file execute_multiply.v VERILOG PATH pipeline/execute_multiply.v
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add_fileset_file execute_multiply.v VERILOG PATH pipeline/execute_multiply.v
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add_fileset_file execute_offset.v VERILOG PATH pipeline/execute_offset.v
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add_fileset_file execute_offset.v VERILOG PATH pipeline/execute_offset.v
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add_fileset_file execute_shift.v VERILOG PATH pipeline/execute_shift.v
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add_fileset_file execute_shift.v VERILOG PATH pipeline/execute_shift.v
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add_fileset_file fetch.v VERILOG PATH pipeline/fetch.v
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add_fileset_file fetch.v VERILOG PATH pipeline/fetch.v
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add_fileset_file microcode.v VERILOG PATH pipeline/microcode.v
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add_fileset_file microcode.v VERILOG PATH pipeline/microcode.v
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add_fileset_file microcode_commands.v VERILOG PATH pipeline/microcode_commands.v
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add_fileset_file microcode_commands.v VERILOG PATH pipeline/microcode_commands.v
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add_fileset_file pipeline.v VERILOG PATH pipeline/pipeline.v
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add_fileset_file pipeline.v VERILOG PATH pipeline/pipeline.v
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add_fileset_file read.v VERILOG PATH pipeline/read.v
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add_fileset_file read.v VERILOG PATH pipeline/read.v
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add_fileset_file read_commands.v VERILOG PATH pipeline/read_commands.v
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add_fileset_file read_commands.v VERILOG PATH pipeline/read_commands.v
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add_fileset_file read_debug.v VERILOG PATH pipeline/read_debug.v
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add_fileset_file read_debug.v VERILOG PATH pipeline/read_debug.v
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add_fileset_file read_effective_address.v VERILOG PATH pipeline/read_effective_address.v
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add_fileset_file read_effective_address.v VERILOG PATH pipeline/read_effective_address.v
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add_fileset_file read_mutex.v VERILOG PATH pipeline/read_mutex.v
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add_fileset_file read_mutex.v VERILOG PATH pipeline/read_mutex.v
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add_fileset_file read_segment.v VERILOG PATH pipeline/read_segment.v
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add_fileset_file read_segment.v VERILOG PATH pipeline/read_segment.v
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add_fileset_file write.v VERILOG PATH pipeline/write.v
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add_fileset_file write.v VERILOG PATH pipeline/write.v
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add_fileset_file write_commands.v VERILOG PATH pipeline/write_commands.v
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add_fileset_file write_commands.v VERILOG PATH pipeline/write_commands.v
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add_fileset_file write_debug.v VERILOG PATH pipeline/write_debug.v
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add_fileset_file write_debug.v VERILOG PATH pipeline/write_debug.v
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add_fileset_file write_register.v VERILOG PATH pipeline/write_register.v
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add_fileset_file write_register.v VERILOG PATH pipeline/write_register.v
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add_fileset_file write_stack.v VERILOG PATH pipeline/write_stack.v
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add_fileset_file write_stack.v VERILOG PATH pipeline/write_stack.v
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add_fileset_file write_string.v VERILOG PATH pipeline/write_string.v
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add_fileset_file write_string.v VERILOG PATH pipeline/write_string.v
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add_fileset_file avalon_mem.v VERILOG PATH memory/avalon_mem.v
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add_fileset_file avalon_mem.v VERILOG PATH memory/avalon_mem.v
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add_fileset_file cache_data_ram.v VERILOG PATH memory/cache_data_ram.v
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add_fileset_file cache_data_ram.v VERILOG PATH memory/cache_data_ram.v
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add_fileset_file dcache.v VERILOG PATH memory/dcache.v
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add_fileset_file dcache.v VERILOG PATH memory/dcache.v
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add_fileset_file dcache_control_ram.v VERILOG PATH memory/dcache_control_ram.v
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add_fileset_file dcache_control_ram.v VERILOG PATH memory/dcache_control_ram.v
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add_fileset_file dcache_matched.v VERILOG PATH memory/dcache_matched.v
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add_fileset_file dcache_matched.v VERILOG PATH memory/dcache_matched.v
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add_fileset_file dcache_read.v VERILOG PATH memory/dcache_read.v
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add_fileset_file dcache_read.v VERILOG PATH memory/dcache_read.v
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add_fileset_file dcache_to_icache_fifo.v VERILOG PATH memory/dcache_to_icache_fifo.v
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add_fileset_file dcache_to_icache_fifo.v VERILOG PATH memory/dcache_to_icache_fifo.v
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add_fileset_file dcache_write.v VERILOG PATH memory/dcache_write.v
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add_fileset_file dcache_write.v VERILOG PATH memory/dcache_write.v
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add_fileset_file icache.v VERILOG PATH memory/icache.v
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add_fileset_file icache.v VERILOG PATH memory/icache.v
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add_fileset_file icache_control_ram.v VERILOG PATH memory/icache_control_ram.v
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add_fileset_file icache_control_ram.v VERILOG PATH memory/icache_control_ram.v
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add_fileset_file icache_matched.v VERILOG PATH memory/icache_matched.v
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add_fileset_file icache_matched.v VERILOG PATH memory/icache_matched.v
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add_fileset_file icache_read.v VERILOG PATH memory/icache_read.v
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add_fileset_file icache_read.v VERILOG PATH memory/icache_read.v
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add_fileset_file link_dcacheread.v VERILOG PATH memory/link_dcacheread.v
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add_fileset_file link_dcacheread.v VERILOG PATH memory/link_dcacheread.v
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add_fileset_file link_dcachewrite.v VERILOG PATH memory/link_dcachewrite.v
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add_fileset_file link_dcachewrite.v VERILOG PATH memory/link_dcachewrite.v
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add_fileset_file link_readburst.v VERILOG PATH memory/link_readburst.v
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add_fileset_file link_readburst.v VERILOG PATH memory/link_readburst.v
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add_fileset_file link_readcode.v VERILOG PATH memory/link_readcode.v
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add_fileset_file link_readcode.v VERILOG PATH memory/link_readcode.v
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add_fileset_file link_readline.v VERILOG PATH memory/link_readline.v
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add_fileset_file link_readline.v VERILOG PATH memory/link_readline.v
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add_fileset_file link_writeburst.v VERILOG PATH memory/link_writeburst.v
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add_fileset_file link_writeburst.v VERILOG PATH memory/link_writeburst.v
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add_fileset_file link_writeline.v VERILOG PATH memory/link_writeline.v
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add_fileset_file link_writeline.v VERILOG PATH memory/link_writeline.v
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add_fileset_file memory.v VERILOG PATH memory/memory.v
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add_fileset_file memory.v VERILOG PATH memory/memory.v
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add_fileset_file memory_read.v VERILOG PATH memory/memory_read.v
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add_fileset_file memory_read.v VERILOG PATH memory/memory_read.v
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add_fileset_file memory_write.v VERILOG PATH memory/memory_write.v
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add_fileset_file memory_write.v VERILOG PATH memory/memory_write.v
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add_fileset_file prefetch.v VERILOG PATH memory/prefetch.v
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add_fileset_file prefetch.v VERILOG PATH memory/prefetch.v
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add_fileset_file prefetch_control.v VERILOG PATH memory/prefetch_control.v
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add_fileset_file prefetch_control.v VERILOG PATH memory/prefetch_control.v
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add_fileset_file prefetch_fifo.v VERILOG PATH memory/prefetch_fifo.v
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add_fileset_file prefetch_fifo.v VERILOG PATH memory/prefetch_fifo.v
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add_fileset_file tlb.v VERILOG PATH memory/tlb.v
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add_fileset_file tlb.v VERILOG PATH memory/tlb.v
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add_fileset_file tlb_memtype.v VERILOG PATH memory/tlb_memtype.v
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add_fileset_file tlb_memtype.v VERILOG PATH memory/tlb_memtype.v
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add_fileset_file tlb_regs.v VERILOG PATH memory/tlb_regs.v
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add_fileset_file tlb_regs.v VERILOG PATH memory/tlb_regs.v
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add_fileset_file simple_fifo.v VERILOG PATH ../common/simple_fifo.v
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add_fileset_file simple_fifo.v VERILOG PATH ../common/simple_fifo.v
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add_fileset_file simple_ram.v VERILOG PATH ../common/simple_ram.v
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add_fileset_file simple_ram.v VERILOG PATH ../common/simple_ram.v
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#
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#
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# parameters
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# parameters
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#
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#
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#
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#
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# display items
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# display items
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#
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#
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#
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#
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# connection point clock
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# connection point clock
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#
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#
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add_interface clock clock end
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock clk clk Input 1
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add_interface_port clock clk clk Input 1
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#
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#
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# connection point reset_sink
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# connection point reset_sink
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#
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#
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add_interface reset_sink reset end
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add_interface reset_sink reset end
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set_interface_property reset_sink associatedClock clock
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set_interface_property reset_sink associatedClock clock
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set_interface_property reset_sink synchronousEdges DEASSERT
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set_interface_property reset_sink synchronousEdges DEASSERT
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set_interface_property reset_sink ENABLED true
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set_interface_property reset_sink ENABLED true
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set_interface_property reset_sink EXPORT_OF ""
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set_interface_property reset_sink EXPORT_OF ""
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set_interface_property reset_sink PORT_NAME_MAP ""
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set_interface_property reset_sink PORT_NAME_MAP ""
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set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
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set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
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set_interface_property reset_sink SVD_ADDRESS_GROUP ""
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set_interface_property reset_sink SVD_ADDRESS_GROUP ""
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add_interface_port reset_sink rst_n reset_n Input 1
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add_interface_port reset_sink rst_n reset_n Input 1
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#
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#
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# connection point avalon_memory
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# connection point avalon_memory
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#
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#
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add_interface avalon_memory avalon start
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add_interface avalon_memory avalon start
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set_interface_property avalon_memory addressUnits SYMBOLS
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set_interface_property avalon_memory addressUnits SYMBOLS
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set_interface_property avalon_memory associatedClock clock
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set_interface_property avalon_memory associatedClock clock
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set_interface_property avalon_memory associatedReset reset_sink
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set_interface_property avalon_memory associatedReset reset_sink
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set_interface_property avalon_memory bitsPerSymbol 8
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set_interface_property avalon_memory bitsPerSymbol 8
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set_interface_property avalon_memory burstOnBurstBoundariesOnly false
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set_interface_property avalon_memory burstOnBurstBoundariesOnly false
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set_interface_property avalon_memory burstcountUnits WORDS
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set_interface_property avalon_memory burstcountUnits WORDS
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set_interface_property avalon_memory doStreamReads false
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set_interface_property avalon_memory doStreamReads false
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set_interface_property avalon_memory doStreamWrites false
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set_interface_property avalon_memory doStreamWrites false
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set_interface_property avalon_memory holdTime 0
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set_interface_property avalon_memory holdTime 0
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set_interface_property avalon_memory linewrapBursts false
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set_interface_property avalon_memory linewrapBursts false
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set_interface_property avalon_memory maximumPendingReadTransactions 0
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set_interface_property avalon_memory maximumPendingReadTransactions 0
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set_interface_property avalon_memory maximumPendingWriteTransactions 0
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set_interface_property avalon_memory readLatency 0
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set_interface_property avalon_memory readLatency 0
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set_interface_property avalon_memory readWaitTime 1
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set_interface_property avalon_memory readWaitTime 1
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set_interface_property avalon_memory setupTime 0
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set_interface_property avalon_memory setupTime 0
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set_interface_property avalon_memory timingUnits Cycles
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set_interface_property avalon_memory timingUnits Cycles
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set_interface_property avalon_memory writeWaitTime 0
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set_interface_property avalon_memory writeWaitTime 0
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set_interface_property avalon_memory ENABLED true
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set_interface_property avalon_memory ENABLED true
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set_interface_property avalon_memory EXPORT_OF ""
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set_interface_property avalon_memory EXPORT_OF ""
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set_interface_property avalon_memory PORT_NAME_MAP ""
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set_interface_property avalon_memory PORT_NAME_MAP ""
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set_interface_property avalon_memory CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_memory CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_memory SVD_ADDRESS_GROUP ""
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set_interface_property avalon_memory SVD_ADDRESS_GROUP ""
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add_interface_port avalon_memory avm_address address Output 32
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add_interface_port avalon_memory avm_address address Output 32
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add_interface_port avalon_memory avm_writedata writedata Output 32
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add_interface_port avalon_memory avm_writedata writedata Output 32
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add_interface_port avalon_memory avm_byteenable byteenable Output 4
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add_interface_port avalon_memory avm_byteenable byteenable Output 4
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add_interface_port avalon_memory avm_burstcount burstcount Output 3
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add_interface_port avalon_memory avm_burstcount burstcount Output 3
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add_interface_port avalon_memory avm_write write Output 1
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add_interface_port avalon_memory avm_write write Output 1
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add_interface_port avalon_memory avm_read read Output 1
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add_interface_port avalon_memory avm_read read Output 1
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add_interface_port avalon_memory avm_waitrequest waitrequest Input 1
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add_interface_port avalon_memory avm_waitrequest waitrequest Input 1
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add_interface_port avalon_memory avm_readdatavalid readdatavalid Input 1
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add_interface_port avalon_memory avm_readdatavalid readdatavalid Input 1
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add_interface_port avalon_memory avm_readdata readdata Input 32
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add_interface_port avalon_memory avm_readdata readdata Input 32
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#
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#
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# connection point interrupt
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# connection point interrupt
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#
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#
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add_interface interrupt conduit end
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add_interface interrupt conduit end
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set_interface_property interrupt associatedClock clock
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set_interface_property interrupt associatedClock clock
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set_interface_property interrupt associatedReset reset_sink
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set_interface_property interrupt associatedReset ""
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set_interface_property interrupt ENABLED true
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set_interface_property interrupt ENABLED true
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set_interface_property interrupt EXPORT_OF ""
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set_interface_property interrupt EXPORT_OF ""
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set_interface_property interrupt PORT_NAME_MAP ""
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set_interface_property interrupt PORT_NAME_MAP ""
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set_interface_property interrupt CMSIS_SVD_VARIABLES ""
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set_interface_property interrupt CMSIS_SVD_VARIABLES ""
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set_interface_property interrupt SVD_ADDRESS_GROUP ""
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set_interface_property interrupt SVD_ADDRESS_GROUP ""
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add_interface_port interrupt interrupt_do export Input 1
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add_interface_port interrupt interrupt_do interrupt_do Input 1
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add_interface_port interrupt interrupt_vector export Input 8
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add_interface_port interrupt interrupt_vector interrupt_vector Input 8
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add_interface_port interrupt interrupt_done export Output 1
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add_interface_port interrupt interrupt_done interrupt_done Output 1
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#
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#
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# connection point avalon_io
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# connection point avalon_io
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#
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#
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add_interface avalon_io avalon start
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add_interface avalon_io avalon start
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set_interface_property avalon_io addressUnits SYMBOLS
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set_interface_property avalon_io addressUnits SYMBOLS
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set_interface_property avalon_io associatedClock clock
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set_interface_property avalon_io associatedClock clock
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set_interface_property avalon_io associatedReset reset_sink
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set_interface_property avalon_io associatedReset reset_sink
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set_interface_property avalon_io bitsPerSymbol 8
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set_interface_property avalon_io bitsPerSymbol 8
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set_interface_property avalon_io burstOnBurstBoundariesOnly false
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set_interface_property avalon_io burstOnBurstBoundariesOnly false
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set_interface_property avalon_io burstcountUnits WORDS
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set_interface_property avalon_io burstcountUnits WORDS
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set_interface_property avalon_io doStreamReads false
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set_interface_property avalon_io doStreamReads false
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set_interface_property avalon_io doStreamWrites false
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set_interface_property avalon_io doStreamWrites false
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set_interface_property avalon_io holdTime 0
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set_interface_property avalon_io holdTime 0
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set_interface_property avalon_io linewrapBursts false
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set_interface_property avalon_io linewrapBursts false
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set_interface_property avalon_io maximumPendingReadTransactions 0
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set_interface_property avalon_io maximumPendingReadTransactions 0
|
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set_interface_property avalon_io maximumPendingWriteTransactions 0
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set_interface_property avalon_io readLatency 0
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set_interface_property avalon_io readLatency 0
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set_interface_property avalon_io readWaitTime 1
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set_interface_property avalon_io readWaitTime 1
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set_interface_property avalon_io setupTime 0
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set_interface_property avalon_io setupTime 0
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set_interface_property avalon_io timingUnits Cycles
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set_interface_property avalon_io timingUnits Cycles
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set_interface_property avalon_io writeWaitTime 0
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set_interface_property avalon_io writeWaitTime 0
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set_interface_property avalon_io ENABLED true
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set_interface_property avalon_io ENABLED true
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set_interface_property avalon_io EXPORT_OF ""
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set_interface_property avalon_io EXPORT_OF ""
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set_interface_property avalon_io PORT_NAME_MAP ""
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set_interface_property avalon_io PORT_NAME_MAP ""
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set_interface_property avalon_io CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_io CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_io SVD_ADDRESS_GROUP ""
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set_interface_property avalon_io SVD_ADDRESS_GROUP ""
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|
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add_interface_port avalon_io avalon_io_address address Output 16
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add_interface_port avalon_io avalon_io_address address Output 16
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add_interface_port avalon_io avalon_io_byteenable byteenable Output 4
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add_interface_port avalon_io avalon_io_byteenable byteenable Output 4
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add_interface_port avalon_io avalon_io_read read Output 1
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add_interface_port avalon_io avalon_io_read read Output 1
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add_interface_port avalon_io avalon_io_readdatavalid readdatavalid Input 1
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add_interface_port avalon_io avalon_io_readdatavalid readdatavalid Input 1
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add_interface_port avalon_io avalon_io_readdata readdata Input 32
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add_interface_port avalon_io avalon_io_readdata readdata Input 32
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add_interface_port avalon_io avalon_io_write write Output 1
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add_interface_port avalon_io avalon_io_write write Output 1
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add_interface_port avalon_io avalon_io_writedata writedata Output 32
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add_interface_port avalon_io avalon_io_writedata writedata Output 32
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add_interface_port avalon_io avalon_io_waitrequest waitrequest Input 1
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add_interface_port avalon_io avalon_io_waitrequest waitrequest Input 1
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#
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# connection point reset_only_ao486
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#
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add_interface reset_only_ao486 reset end
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set_interface_property reset_only_ao486 associatedClock clock
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set_interface_property reset_only_ao486 synchronousEdges DEASSERT
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set_interface_property reset_only_ao486 ENABLED true
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set_interface_property reset_only_ao486 EXPORT_OF ""
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set_interface_property reset_only_ao486 PORT_NAME_MAP ""
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set_interface_property reset_only_ao486 CMSIS_SVD_VARIABLES ""
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set_interface_property reset_only_ao486 SVD_ADDRESS_GROUP ""
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add_interface_port reset_only_ao486 rst_internal_n reset_n Input 1
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No newline at end of file
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