/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Author: Eyal Hochberg ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// eyal@provartec.com ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//////////////////////////////////////
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//////////////////////////////////////
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//
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//
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// General:
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// General:
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// The AXI master has an internal master per ID.
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// The AXI master has an internal master per ID.
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// These internal masters work simultaniously and an interconnect matrix connets them.
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// These internal masters work simultaniously and an interconnect matrix connets them.
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//
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//
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//
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//
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// I/F :
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// I/F :
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// idle - all internal masters emptied their command FIFOs
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// idle - all internal masters emptied their command FIFOs
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// scrbrd_empty - all scoreboard checks have been completed (for random testing)
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// scrbrd_empty - all scoreboard checks have been completed (for random testing)
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//
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//
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//
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//
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// Tasks:
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// Tasks:
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//
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//
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// enable(input master_num)
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// enable(input master_num)
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// Description: Enables master
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// Description: Enables master
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// Parameters: master_num - number of internal master
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// Parameters: master_num - number of internal master
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//
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//
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// enable_all()
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// enable_all()
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// Description: Enables all masters
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// Description: Enables all masters
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//
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//
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// write_single(input master_num, input addr, input wdata)
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// write_single(input master_num, input addr, input wdata)
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// Description: write a single AXI burst (1 data cycle)
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// Description: write a single AXI burst (1 data cycle)
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// Parameters: master_num - number of internal master
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// Parameters: master_num - number of internal master
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// addr - address
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// addr - address
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// wdata - write data
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// wdata - write data
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//
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//
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// read_single(input master_num, input addr, output rdata)
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// read_single(input master_num, input addr, output rdata)
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// Description: read a single AXI burst (1 data cycle)
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// Description: read a single AXI burst (1 data cycle)
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// Parameters: master_num - number of internal master
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// Parameters: master_num - number of internal master
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// addr - address
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// addr - address
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// rdata - return read data
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// rdata - return read data
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//
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//
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// check_single(input master_num, input addr, input expected)
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// check_single(input master_num, input addr, input expected)
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// Description: read a single AXI burst and gives an error if the data read does not match expected
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// Description: read a single AXI burst and gives an error if the data read does not match expected
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// Parameters: master_num - number of internal master
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// Parameters: master_num - number of internal master
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// addr - address
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// addr - address
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// expected - expected read data
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// expected - expected read data
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//
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//
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// write_and_check_single(input master_num, input addr, input data)
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// write_and_check_single(input master_num, input addr, input data)
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// Description: write a single AXI burst read it back and compare the write and read data
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// Description: write a single AXI burst read it back and compare the write and read data
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// Parameters: master_num - number of internal master
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// Parameters: master_num - number of internal master
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// addr - address
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// addr - address
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// data - data to write and expect on read
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// data - data to write and expect on read
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//
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//
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// insert_wr_cmd(input master_num, input addr, input len, input size)
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// insert_wr_cmd(input master_num, input addr, input len, input size)
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// Description: add an AXI write burst to command FIFO
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// Description: add an AXI write burst to command FIFO
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// Parameters: master_num - number of internal master
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// Parameters: master_num - number of internal master
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// addr - address
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// addr - address
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// len - AXI LEN (data strobe number)
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// len - AXI LEN (data strobe number)
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// size - AXI SIZE (data width)
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// size - AXI SIZE (data width)
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//
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//
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// insert_rd_cmd(input master_num, input addr, input len, input size)
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// insert_rd_cmd(input master_num, input addr, input len, input size)
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// Description: add an AXI read burst to command FIFO
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// Description: add an AXI read burst to command FIFO
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// Parameters: master_num - number of internal master
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// Parameters: master_num - number of internal master
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// addr - address
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// addr - address
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// len - AXI LEN (data strobe number)
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// len - AXI LEN (data strobe number)
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// size - AXI SIZE (data width)
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// size - AXI SIZE (data width)
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//
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//
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// insert_wr_data(input master_num, input wdata)
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// insert_wr_data(input master_num, input wdata)
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// Description: add a single data to data FIFO (to be used in write bursts)
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// Description: add a single data to data FIFO (to be used in write bursts)
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// Parameters: master_num - number of internal master
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// Parameters: master_num - number of internal master
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// wdata - write data
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// wdata - write data
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//
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//
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// insert_wr_incr_data(input master_num, input addr, input len, input size)
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// insert_wr_incr_data(input master_num, input addr, input len, input size)
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// Description: add an AXI write burst to command FIFO will use incremental data (no need to use insert_wr_data)
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// Description: add an AXI write burst to command FIFO will use incremental data (no need to use insert_wr_data)
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// Parameters: master_num - number of internal master
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// Parameters: master_num - number of internal master
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// addr - address
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// addr - address
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// len - AXI LEN (data strobe number)
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// len - AXI LEN (data strobe number)
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// size - AXI SIZE (data width)
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// size - AXI SIZE (data width)
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//
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//
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// insert_rand_chk(input master_num, input burst_num)
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// insert_rand_chk(input master_num, input burst_num)
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// Description: add multiple commands to command FIFO. Each command writes incremental data to a random address, reads the data back and checks the data. Useful for random testing.
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// Description: add multiple commands to command FIFO. Each command writes incremental data to a random address, reads the data back and checks the data. Useful for random testing.
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// Parameters: master_num - number of internal master
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// Parameters: master_num - number of internal master
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// burst_num - total number of bursts to check
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// burst_num - total number of bursts to check
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//
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//
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// insert_rand(input burst_num)
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// insert_rand(input burst_num)
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// Description: disperces burst_num between internal masters and calls insert_rand_chk for each master
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// Description: disperces burst_num between internal masters and calls insert_rand_chk for each master
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// Parameters: burst_num - total number of bursts to check (combined)
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// Parameters: burst_num - total number of bursts to check (combined)
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//
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//
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//
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//
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// Parameters:
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// Parameters:
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//
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//
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// For random testing: (changing these values automatically update interanl masters)
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// For random testing: (changing these values automatically update interanl masters)
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// ahb_bursts - if set, bursts will only be of length 1, 4, 8 or 16.
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// ahb_bursts - if set, bursts will only be of length 1, 4, 8 or 16.
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// len_min - minimum burst AXI LEN (length)
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// len_min - minimum burst AXI LEN (length)
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// len_max - maximum burst AXI LEN (length)
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// len_max - maximum burst AXI LEN (length)
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// size_min - minimum burst AXI SIZE (width)
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// size_min - minimum burst AXI SIZE (width)
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// size_max - maximum burst AXI SIZE (width)
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// size_max - maximum burst AXI SIZE (width)
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// addr_min - minimum address (in bytes)
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// addr_min - minimum address (in bytes)
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// addr_max - maximum address (in bytes)
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// addr_max - maximum address (in bytes)
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//
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//
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//////////////////////////////////////
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//////////////////////////////////////
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OUTFILE PREFIX.v
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OUTFILE PREFIX.v
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INCLUDE def_axi_master.txt
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INCLUDE def_axi_master.txt
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ITER IDX ID_NUM
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ITER IDX ID_NUM
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module PREFIX(PORTS);
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module PREFIX(PORTS);
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`include "prgen_rand.v"
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`include "prgen_rand.v"
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input clk;
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input clk;
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input reset;
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input reset;
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port GROUP_STUB_AXI;
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port GROUP_STUB_AXI;
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output idle;
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output idle;
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output scrbrd_empty;
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output scrbrd_empty;
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//random parameters
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//random parameters
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integer GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT;
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integer GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT;
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wire GROUP_STUB_AXI_IDX;
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wire GROUP_STUB_AXI_IDX;
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wire idle_IDX;
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wire idle_IDX;
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wire scrbrd_empty_IDX;
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wire scrbrd_empty_IDX;
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always @(*)
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always @(*)
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begin
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begin
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#FFD;
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#FFD;
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PREFIX_singleIDX.GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND;
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PREFIX_singleIDX.GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND;
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end
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end
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assign idle = CONCAT(idle_IDX &);
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assign idle = CONCAT(idle_IDX &);
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assign scrbrd_empty = CONCAT(scrbrd_empty_IDX &);
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assign scrbrd_empty = CONCAT(scrbrd_empty_IDX &);
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CREATE axi_master_single.v
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CREATE axi_master_single.v
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LOOP IDX ID_NUM
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LOOP IDX ID_NUM
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PREFIX_single #(IDX, ID_BITS'GROUP_AXI_ID[IDX], CMD_DEPTH)
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PREFIX_single #(IDX, ID_BITS'bGROUP_AXI_ID[IDX], CMD_DEPTH)
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PREFIX_singleIDX(
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PREFIX_singleIDX(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.GROUP_STUB_AXI(GROUP_STUB_AXI_IDX),
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.GROUP_STUB_AXI(GROUP_STUB_AXI_IDX),
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.idle(idle_IDX),
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.idle(idle_IDX),
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.scrbrd_empty(scrbrd_empty_IDX)
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.scrbrd_empty(scrbrd_empty_IDX)
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);
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);
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ENDLOOP IDX
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ENDLOOP IDX
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IFDEF TRUE(ID_NUM==1)
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IFDEF TRUE(ID_NUM==1)
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assign GROUP_STUB_AXI.OUT = GROUP_STUB_AXI_0.OUT;
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assign GROUP_STUB_AXI.OUT = GROUP_STUB_AXI_0.OUT;
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assign GROUP_STUB_AXI_0.IN = GROUP_STUB_AXI.IN;
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assign GROUP_STUB_AXI_0.IN = GROUP_STUB_AXI.IN;
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ELSE TRUE(ID_NUM==1)
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ELSE TRUE(ID_NUM==1)
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CREATE ic.v \\
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CREATE ic.v \\
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DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX) \\
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DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX) \\
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DEFCMD(SWAP.GLOBAL MASTER_NUM ID_NUM) \\
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DEFCMD(SWAP.GLOBAL MASTER_NUM ID_NUM) \\
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DEFCMD(SWAP.GLOBAL SLAVE_NUM 1) \\
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DEFCMD(SWAP.GLOBAL SLAVE_NUM 1) \\
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DEFCMD(SWAP.GLOBAL CONST(ID_BITS) ID_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(ID_BITS) ID_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(CMD_DEPTH) CMD_DEPTH) \\
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DEFCMD(SWAP.GLOBAL CONST(CMD_DEPTH) CMD_DEPTH) \\
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DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS) \\
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DEFCMD(DEFINE.GLOBAL UNIQUE_ID) \\
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DEFCMD(SWAP.GLOBAL CONST(USER_BITS) 0)
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DEFCMD(SWAP.GLOBAL CONST(USER_BITS) 0)
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LOOP IDX ID_NUM
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LOOP IDX ID_NUM
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STOMP NEWLINE
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STOMP NEWLINE
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DEFCMD(GROUP.GLOBAL MIDX_ID overrides { ) \\
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DEFCMD(GROUP.GLOBAL MIDX_ID overrides { ) \\
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DEFCMD(GROUP_AXI_ID[IDX]) \\
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DEFCMD(GROUP_AXI_ID[IDX]) \\
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DEFCMD(})
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DEFCMD(})
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ENDLOOP IDX
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ENDLOOP IDX
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PREFIX_ic PREFIX_ic(
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PREFIX_ic PREFIX_ic(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.MIDX_GROUP_STUB_AXI(GROUP_STUB_AXI_IDX),
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.MIDX_GROUP_STUB_AXI(GROUP_STUB_AXI_IDX),
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.S0_GROUP_STUB_AXI(GROUP_STUB_AXI),
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.S0_GROUP_STUB_AXI(GROUP_STUB_AXI),
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STOMP ,
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STOMP ,
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|
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);
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);
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ENDIF TRUE(ID_NUM==1)
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ENDIF TRUE(ID_NUM==1)
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task check_master_num;
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task check_master_num;
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input [24*8-1:0] task_name;
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input [24*8-1:0] task_name;
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input [31:0] master_num;
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input [31:0] master_num;
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begin
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begin
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if (master_num >= ID_NUM)
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if (master_num >= ID_NUM)
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begin
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begin
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$display("FATAL ERROR: task %0s called for master %0d that does not exist.\tTime: %0d ns.", task_name, master_num, $time);
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$display("FATAL ERROR: task %0s called for master %0d that does not exist.\tTime: %0d ns.", task_name, master_num, $time);
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end
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end
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end
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end
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endtask
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endtask
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task enable;
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task enable;
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input [31:0] master_num;
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input [31:0] master_num;
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begin
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begin
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check_master_num("enable", master_num);
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check_master_num("enable", master_num);
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case (master_num)
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case (master_num)
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IDX : PREFIX_singleIDX.enable = 1;
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IDX : PREFIX_singleIDX.enable = 1;
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endcase
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endcase
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end
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end
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endtask
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endtask
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|
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task enable_all;
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task enable_all;
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begin
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begin
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PREFIX_singleIDX.enable = 1;
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PREFIX_singleIDX.enable = 1;
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end
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end
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endtask
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endtask
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|
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task write_single;
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task write_single;
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input [31:0] master_num;
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input [31:0] master_num;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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input [DATA_BITS-1:0] wdata;
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input [DATA_BITS-1:0] wdata;
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begin
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begin
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check_master_num("write_single", master_num);
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check_master_num("write_single", master_num);
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case (master_num)
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case (master_num)
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IDX : PREFIX_singleIDX.write_single(addr, wdata);
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IDX : PREFIX_singleIDX.write_single(addr, wdata);
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endcase
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endcase
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end
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end
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endtask
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endtask
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task read_single;
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task read_single;
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input [31:0] master_num;
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input [31:0] master_num;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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output [DATA_BITS-1:0] rdata;
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output [DATA_BITS-1:0] rdata;
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begin
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begin
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check_master_num("read_single", master_num);
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check_master_num("read_single", master_num);
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case (master_num)
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case (master_num)
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IDX : PREFIX_singleIDX.read_single(addr, rdata);
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IDX : PREFIX_singleIDX.read_single(addr, rdata);
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endcase
|
endcase
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end
|
end
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endtask
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endtask
|
|
|
task check_single;
|
task check_single;
|
input [31:0] master_num;
|
input [31:0] master_num;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
|
input [DATA_BITS-1:0] expected;
|
input [DATA_BITS-1:0] expected;
|
begin
|
begin
|
check_master_num("check_single", master_num);
|
check_master_num("check_single", master_num);
|
case (master_num)
|
case (master_num)
|
IDX : PREFIX_singleIDX.check_single(addr, expected);
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IDX : PREFIX_singleIDX.check_single(addr, expected);
|
endcase
|
endcase
|
end
|
end
|
endtask
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endtask
|
|
|
task write_and_check_single;
|
task write_and_check_single;
|
input [31:0] master_num;
|
input [31:0] master_num;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [DATA_BITS-1:0] data;
|
input [DATA_BITS-1:0] data;
|
begin
|
begin
|
check_master_num("write_and_check_single", master_num);
|
check_master_num("write_and_check_single", master_num);
|
case (master_num)
|
case (master_num)
|
IDX : PREFIX_singleIDX.write_and_check_single(addr, data);
|
IDX : PREFIX_singleIDX.write_and_check_single(addr, data);
|
endcase
|
endcase
|
end
|
end
|
endtask
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endtask
|
|
|
task insert_wr_cmd;
|
task insert_wr_cmd;
|
input [31:0] master_num;
|
input [31:0] master_num;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [LEN_BITS-1:0] len;
|
input [LEN_BITS-1:0] len;
|
input [SIZE_BITS-1:0] size;
|
input [SIZE_BITS-1:0] size;
|
begin
|
begin
|
check_master_num("insert_wr_cmd", master_num);
|
check_master_num("insert_wr_cmd", master_num);
|
case (master_num)
|
case (master_num)
|
IDX : PREFIX_singleIDX.insert_wr_cmd(addr, len, size);
|
IDX : PREFIX_singleIDX.insert_wr_cmd(addr, len, size);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_rd_cmd;
|
task insert_rd_cmd;
|
input [31:0] master_num;
|
input [31:0] master_num;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [LEN_BITS-1:0] len;
|
input [LEN_BITS-1:0] len;
|
input [SIZE_BITS-1:0] size;
|
input [SIZE_BITS-1:0] size;
|
begin
|
begin
|
check_master_num("insert_rd_cmd", master_num);
|
check_master_num("insert_rd_cmd", master_num);
|
case (master_num)
|
case (master_num)
|
IDX : PREFIX_singleIDX.insert_rd_cmd(addr, len, size);
|
IDX : PREFIX_singleIDX.insert_rd_cmd(addr, len, size);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_wr_data;
|
task insert_wr_data;
|
input [31:0] master_num;
|
input [31:0] master_num;
|
input [DATA_BITS-1:0] wdata;
|
input [DATA_BITS-1:0] wdata;
|
begin
|
begin
|
check_master_num("insert_wr_data", master_num);
|
check_master_num("insert_wr_data", master_num);
|
case (master_num)
|
case (master_num)
|
IDX : PREFIX_singleIDX.insert_wr_data(wdata);
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IDX : PREFIX_singleIDX.insert_wr_data(wdata);
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endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_wr_incr_data;
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task insert_wr_incr_data;
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input [31:0] master_num;
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input [31:0] master_num;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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input [LEN_BITS-1:0] len;
|
input [LEN_BITS-1:0] len;
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input [SIZE_BITS-1:0] size;
|
input [SIZE_BITS-1:0] size;
|
begin
|
begin
|
check_master_num("insert_wr_incr_data", master_num);
|
check_master_num("insert_wr_incr_data", master_num);
|
case (master_num)
|
case (master_num)
|
IDX : PREFIX_singleIDX.insert_wr_incr_data(addr, len, size);
|
IDX : PREFIX_singleIDX.insert_wr_incr_data(addr, len, size);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_rand_chk;
|
task insert_rand_chk;
|
input [31:0] master_num;
|
input [31:0] master_num;
|
input [31:0] burst_num;
|
input [31:0] burst_num;
|
begin
|
begin
|
check_master_num("insert_rand_chk", master_num);
|
check_master_num("insert_rand_chk", master_num);
|
case (master_num)
|
case (master_num)
|
IDX : PREFIX_singleIDX.insert_rand_chk(burst_num);
|
IDX : PREFIX_singleIDX.insert_rand_chk(burst_num);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_rand;
|
task insert_rand;
|
input [31:0] burst_num;
|
input [31:0] burst_num;
|
|
|
reg [31:0] burst_numIDX;
|
reg [31:0] burst_numIDX;
|
integer remain;
|
integer remain;
|
begin
|
begin
|
remain = burst_num;
|
remain = burst_num;
|
LOOP IDX ID_NUM
|
LOOP IDX ID_NUM
|
if (remain > 0)
|
if (remain > 0)
|
begin
|
begin
|
burst_numIDX = rand(1, remain);
|
burst_numIDX = rand(1, remain);
|
remain = remain - burst_numIDX;
|
remain = remain - burst_numIDX;
|
insert_rand_chk(IDX, burst_numIDX);
|
insert_rand_chk(IDX, burst_numIDX);
|
end
|
end
|
ENDLOOP IDX
|
ENDLOOP IDX
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
endmodule
|
endmodule
|
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