/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Author: Eyal Hochberg ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// eyal@provartec.com ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//////////////////////////////////////
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//////////////////////////////////////
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//
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//
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// General:
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// General:
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// The APB slave can use APB or APB3 protocol (APB3 is with pslverr and pready)
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// The APB slave can use APB or APB3 protocol (APB3 is with pslverr and pready)
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// APB3 is set by DEFINE in def_apb_slave.txt
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// APB3 is set by DEFINE in def_apb_slave.txt
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// All following tasks regard APB3 only.
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// All following tasks regard APB3 only.
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//
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//
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//
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//
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// Tasks:
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// Tasks:
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//
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//
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// set_random_delay(input min_delay, input max_delay)
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// set_random_delay(input min_delay, input max_delay)
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// Description: Set random wait states on pready
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// Description: Set random wait states on pready
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// Parameters: min_delay - minimum delay
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// Parameters: min_delay - minimum delay
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// max_delay = maximum delay
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// max_delay = maximum delay
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//
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//
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// set_fixed_delay(input delay)
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// set_fixed_delay(input delay)
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// Description: Set fixed wait states on pready
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// Description: Set fixed wait states on pready
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// Parameters: delay - fixed delay on pready
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// Parameters: delay - fixed delay on pready
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//
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//
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// set_slverr(input address)
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// set_slverr(input address)
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// Description: Set address to return slave error (pslverr)
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// Description: Set address to return slave error (pslverr)
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// Parameters: address - address will return pslverr
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// Parameters: address - address will return pslverr
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//
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//
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//
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//
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//////////////////////////////////////
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//////////////////////////////////////
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OUTFILE PREFIX.v
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OUTFILE PREFIX.v
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INCLUDE def_apb_slave.txt
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INCLUDE def_apb_slave.txt
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module PREFIX(PORTS);
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module PREFIX(PORTS);
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CREATE prgen_rand.v DEFCMD(DEFINE NOT_IN_LIST)
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`include "prgen_rand.v"
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`include "prgen_rand.v"
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parameter SLAVE_NUM = 0;
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parameter SLAVE_NUM = 0;
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input clk;
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input clk;
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input reset;
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input reset;
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revport GROUP_STUB_APB;
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revport GROUP_STUB_APB;
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wire GROUP_STUB_MEM;
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wire GROUP_STUB_MEM;
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IFDEF APB3
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IFDEF APB3
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reg busy_rand_enable = 0; //enable random busy
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reg busy_rand_enable = 0; //enable random busy
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integer busy_min = 0; //min busy cycles
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integer busy_min = 0; //min busy cycles
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integer busy_max = 5; //max busy cycles
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integer busy_max = 5; //max busy cycles
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integer busy_delay = 1; //fixed delay for pready
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integer busy_delay = 1; //fixed delay for pready
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reg err_enable = 0;
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reg err_enable = 0;
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reg [ADDR_BITS-1:0] err_addr = {ADDR_BITS{1'b1}}; //error address
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reg [ADDR_BITS-1:0] err_addr = {ADDR_BITS{1'b1}}; //error address
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wire pslverr = err_enable && (paddr == err_addr);
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wire pslverr = err_enable && (paddr == err_addr);
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reg pready = 1'b1;
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reg pready = 1'b1;
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always @(negedge clk)
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always @(negedge clk)
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begin
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begin
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#FFD;
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#FFD;
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if (psel)
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if (psel)
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begin
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begin
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if (busy_rand_enable)
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if (busy_rand_enable)
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begin
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begin
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busy_delay = rand(busy_min, busy_max);
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busy_delay = rand(busy_min, busy_max);
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end
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end
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if (busy_delay > 0)
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if (busy_delay > 0)
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begin
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begin
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pready = 1'b0;
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pready = 1'b0;
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repeat (busy_delay)
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repeat (busy_delay)
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begin
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begin
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@(posedge clk); #FFD;
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@(posedge clk); #FFD;
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end
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end
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pready = 1'b1;
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pready = 1'b1;
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@(posedge clk); #FFD;
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@(posedge clk); #FFD;
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end
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end
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end
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end
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end
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end
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task set_random_delay;
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task set_random_delay;
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input [31:0] delay_min;
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input [31:0] delay_min;
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input [31:0] delay_max;
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input [31:0] delay_max;
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begin
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begin
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busy_rand_enable = 1;
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busy_rand_enable = 1;
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busy_min = delay_min;
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busy_min = delay_min;
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busy_max = delay_max;
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busy_max = delay_max;
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end
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end
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endtask
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endtask
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task set_fixed_delay;
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task set_fixed_delay;
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input [31:0] delay;
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input [31:0] delay;
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begin
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begin
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busy_rand_enable = 0;
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busy_rand_enable = 0;
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busy_delay = delay;
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busy_delay = delay;
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end
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end
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endtask
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endtask
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task set_slverr;
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task set_slverr;
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input [31:0] addr;
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input [31:0] addr;
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begin
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begin
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err_enable = 1;
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err_enable = 1;
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err_addr = addr;
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err_addr = addr;
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end
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end
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endtask
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endtask
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ELSE APB3
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ELSE APB3
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wire pready = 1'b1;
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wire pready = 1'b1;
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wire pslverr = 1'b0;
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wire pslverr = 1'b0;
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ENDIF APB3
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ENDIF APB3
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assign WR = psel & penable & pwrite;
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assign WR = psel & penable & pwrite;
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assign RD = psel & (~penable) & (~pwrite);
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assign RD = psel & (~penable) & (~pwrite);
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assign ADDR_WR = paddr;
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assign ADDR_WR = paddr;
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assign ADDR_RD = paddr;
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assign ADDR_RD = paddr;
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assign DIN = pwdata;
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assign DIN = pwdata;
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assign BSEL = 4'b1111;
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assign BSEL = 4'b1111;
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assign prdata = pready ? DOUT : {DATA_BITS{1'bx}};
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assign prdata = pready ? DOUT : {DATA_BITS{1'bx}};
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CREATE apb_slave_mem.v
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CREATE apb_slave_mem.v
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PREFIX_mem PREFIX_mem(
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PREFIX_mem PREFIX_mem(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.GROUP_STUB_MEM(GROUP_STUB_MEM),
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.GROUP_STUB_MEM(GROUP_STUB_MEM),
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STOMP ,
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STOMP ,
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);
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);
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IFDEF TRACE
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IFDEF TRACE
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CREATE apb_slave_trace.v
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CREATE apb_slave_trace.v
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PREFIX_trace #(SLAVE_NUM)
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PREFIX_trace #(SLAVE_NUM)
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PREFIX_trace(
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PREFIX_trace(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.GROUP_STUB_MEM(GROUP_STUB_MEM),
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.GROUP_STUB_MEM(GROUP_STUB_MEM),
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STOMP ,
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STOMP ,
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);
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);
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ENDIF TRACE
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ENDIF TRACE
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endmodule
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endmodule
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