//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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////
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////
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////
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////
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//// FIFO BLOCK to I2C Core
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//// FIFO BLOCK to I2C Core
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////
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////
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////
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////
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////
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////
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//// This file is part of the APB to I2C project
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//// This file is part of the APB to I2C project
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////
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////
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//// http://www.opencores.org/cores/apbi2c/
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//// http://www.opencores.org/cores/apbi2c/
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////
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////
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////
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////
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////
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////
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//// Description
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//// Description
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////
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////
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//// Implementation of APB IP core according to
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//// Implementation of APB IP core according to
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////
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////
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//// apbi2c_spec IP core specification document.
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//// apbi2c_spec IP core specification document.
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////
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////
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////
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////
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////
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////
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//// To Do: This block inst functional yet when you try only write half registers and it didnt go correctly FULL and EMPTY
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//// To Do: This block inst functional yet when you try only write half registers and it didnt go correctly FULL and EMPTY
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////
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////
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////
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////
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////
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////
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////
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////
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////
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////
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//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
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//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
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//// Ronal Dario Celaya
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//// Ronal Dario Celaya
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////
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////
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/////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////
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////
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////
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////
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////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG
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//// Copyright (C) 2009 Authors and OPENCORES.ORG
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////
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////
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////
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////
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////
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////
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//// This source file may be used and distributed without
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//// This source file may be used and distributed without
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////
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////
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//// restriction provided that this copyright statement is not
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//// restriction provided that this copyright statement is not
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////
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////
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//// removed from the file and that any derivative work contains
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//// removed from the file and that any derivative work contains
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//// the original copyright notice and the associated disclaimer.
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//// the original copyright notice and the associated disclaimer.
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////
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////
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////
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////
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//// This source file is free software; you can redistribute it
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//// This source file is free software; you can redistribute it
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////
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////
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//// and/or modify it under the terms of the GNU Lesser General
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//// and/or modify it under the terms of the GNU Lesser General
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////
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////
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//// Public License as published by the Free Software Foundation;
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//// Public License as published by the Free Software Foundation;
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//// either version 2.1 of the License, or (at your option) any
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//// either version 2.1 of the License, or (at your option) any
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////
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////
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//// later version.
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//// later version.
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////
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////
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////
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////
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////
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////
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//// This source is distributed in the hope that it will be
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//// This source is distributed in the hope that it will be
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////
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////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied
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//// useful, but WITHOUT ANY WARRANTY; without even the implied
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////
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////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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////
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////
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//// PURPOSE. See the GNU Lesser General Public License for more
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//// PURPOSE. See the GNU Lesser General Public License for more
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//// details.
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//// details.
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////
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////
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////
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////
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////
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////
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//// You should have received a copy of the GNU Lesser General
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//// You should have received a copy of the GNU Lesser General
|
////
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////
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//// Public License along with this source; if not, download it
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//// Public License along with this source; if not, download it
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////
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////
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//// from http://www.opencores.org/lgpl.shtml
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//// from http://www.opencores.org/lgpl.shtml
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////
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////
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////
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////
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///////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////
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`timescale 1ns/1ps
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module fifo
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module fifo
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#(
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#(
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parameter integer DWIDTH = 32,
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parameter integer DWIDTH = 32,
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parameter integer AWIDTH = 4
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parameter integer AWIDTH = 4
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)
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)
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(
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(
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input clock, reset, wr_en, rd_en,
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input clock, reset, wr_en, rd_en,
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input [DWIDTH-1:0] data_in,
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input [DWIDTH-1:0] data_in,
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output f_full, f_empty,
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output f_full, f_empty,
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output [DWIDTH-1:0] data_out
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output [DWIDTH-1:0] data_out
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);
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);
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reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
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// reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
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parameter integer DEPTH = 1 << AWIDTH;
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wire [DWIDTH-1:0] data_ram_out;
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wire wr_en_ram;
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wire rd_en_ram;
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reg [AWIDTH-1:0] wr_ptr;
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reg [AWIDTH-1:0] wr_ptr;
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reg [AWIDTH-1:0] rd_ptr;
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reg [AWIDTH-1:0] rd_ptr;
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reg [AWIDTH-1:0] last_position;
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reg [AWIDTH:0] counter;
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reg last_was_write;
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reg last_was_write;
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//Write pointer
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always@(posedge clock)
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always@(posedge clock)
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begin
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begin
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if (reset)
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if (reset)
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//SYNCHRONOUS RESET
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begin
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begin
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rd_ptr <= {AWIDTH{1'b0}};
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wr_ptr <= {(AWIDTH){1'b0}};
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wr_ptr <= {AWIDTH{1'b0}};
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last_position <= {AWIDTH{1'b0}};
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last_was_write <= 1'b1;
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// NONBLOCKING
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end
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end
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else
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else if (wr_en && !f_full)
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begin
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begin
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wr_ptr <= wr_ptr + 1'b1;
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end
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end
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if(wr_en)//WRITE OPERATION
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//Read pointer
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always@(posedge clock)
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begin
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begin
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mem[wr_ptr] <= data_in; //WRITE TO ARRAY
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if (reset)
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wr_ptr <= wr_ptr + 11'd1;
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begin
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last_position <= last_position + 11'd1;
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rd_ptr <= {(AWIDTH){1'b0}};
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last_was_write <= 1'b0;
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rd_ptr <= {AWIDTH{1'b0}};
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end
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end
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else if(rd_en)// READ OPERATION
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else if (rd_en && !f_empty)
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begin
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begin
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wr_ptr <= {AWIDTH{1'b0}};
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rd_ptr <= rd_ptr + 1'b1;
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end
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end
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if(rd_ptr != {AWIDTH{1'b1}} && last_position == {AWIDTH{1'b0}})
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//Counter
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always@(posedge clock)
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begin
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begin
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rd_ptr <= rd_ptr + 11'd1;
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if (reset)
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end
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else if(rd_ptr != last_position)
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begin
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begin
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rd_ptr <= rd_ptr + 11'd1;
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counter <= {(AWIDTH+1){1'b0}};
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end
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end
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else
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if(rd_ptr == last_position - 4'b1 || rd_ptr == {AWIDTH{1'b1}})
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begin
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begin
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last_was_write <= 1'b1;
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if (rd_en && !f_empty && !wr_en)
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last_position <= {AWIDTH{1'b0}};
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begin
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counter <= counter - 1'b1;
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end
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end
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else if (wr_en && !f_full && !rd_en)
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begin
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counter <= counter + 1'b1;
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end
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end
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end
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end
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end
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end
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assign f_full = (counter == DEPTH -1) ; //(!last_was_write | last_position != {AWIDTH{1'b0}} )? 1'b1:1'b0;
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assign f_empty = (counter == {AWIDTH{1'b0}}); //(last_was_write)? 1'b1:1'b0;
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assign wr_en_ram = wr_en;
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assign rd_en_ram = rd_en;
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assign data_out = data_ram_out;
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assign f_full = (!last_was_write | last_position != {AWIDTH{1'b0}} )? 1'b1:1'b0;
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dp_ram #(DWIDTH, AWIDTH)
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assign f_empty = (last_was_write)? 1'b1:1'b0;
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RAM_1 (
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assign data_out = mem[rd_ptr];//WRITE ON OUTPUT
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.clock(clock),
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.reset(reset),
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.wr_en(wr_en_ram),
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.rd_en(rd_en_ram),
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.data_in(data_in),
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.wr_addr(wr_ptr),
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.data_out(data_ram_out),
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.rd_addr(rd_ptr)
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);
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endmodule
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endmodule
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