//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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////
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////
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////
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////
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//// TOP I2C BLOCK to I2C Core
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//// TOP I2C BLOCK to I2C Core
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////
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////
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////
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////
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////
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////
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//// This file is part of the APB to I2C project
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//// This file is part of the APB to I2C project
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////
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////
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//// http://www.opencores.org/cores/apbi2c/
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//// http://www.opencores.org/cores/apbi2c/
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////
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////
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////
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////
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////
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////
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//// Description
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//// Description
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////
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////
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//// Implementation of APB IP core according to
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//// Implementation of APB IP core according to
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////
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////
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//// apbi2c_spec IP core specification document.
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//// apbi2c_spec IP core specification document.
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////
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////
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////
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////
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////
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////
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//// To Do: Things are right here but always all block can suffer changes
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//// To Do: Things are right here but always all block can suffer changes
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////
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////
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////
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////
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////
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////
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////
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////
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////
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////
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//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
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//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
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//// Ronal Dario Celaya
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//// Ronal Dario Celaya
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////
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////
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/////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////
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////
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////
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////
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////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG
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//// Copyright (C) 2009 Authors and OPENCORES.ORG
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////
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////
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////
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////
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////
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////
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//// This source file may be used and distributed without
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//// This source file may be used and distributed without
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////
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////
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//// restriction provided that this copyright statement is not
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//// restriction provided that this copyright statement is not
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////
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////
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//// removed from the file and that any derivative work contains
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//// removed from the file and that any derivative work contains
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//// the original copyright notice and the associated disclaimer.
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//// the original copyright notice and the associated disclaimer.
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////
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////
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////
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////
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//// This source file is free software; you can redistribute it
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//// This source file is free software; you can redistribute it
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////
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////
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//// and/or modify it under the terms of the GNU Lesser General
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//// and/or modify it under the terms of the GNU Lesser General
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////
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////
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//// Public License as published by the Free Software Foundation;
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//// Public License as published by the Free Software Foundation;
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//// either version 2.1 of the License, or (at your option) any
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//// either version 2.1 of the License, or (at your option) any
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////
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////
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//// later version.
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//// later version.
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////
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////
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////
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////
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////
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////
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//// This source is distributed in the hope that it will be
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//// This source is distributed in the hope that it will be
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////
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////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied
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//// useful, but WITHOUT ANY WARRANTY; without even the implied
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////
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////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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////
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////
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//// PURPOSE. See the GNU Lesser General Public License for more
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//// PURPOSE. See the GNU Lesser General Public License for more
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//// details.
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//// details.
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////
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////
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////
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////
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////
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////
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//// You should have received a copy of the GNU Lesser General
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//// You should have received a copy of the GNU Lesser General
|
////
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////
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//// Public License along with this source; if not, download it
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//// Public License along with this source; if not, download it
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////
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////
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//// from http://www.opencores.org/lgpl.shtml
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//// from http://www.opencores.org/lgpl.shtml
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////
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////
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////
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////
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///////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////
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`timescale 1ns/1ps //timescale
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`timescale 1ns/1ps //timescale
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module i2c(
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module i2c(
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//APB PORTS
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//APB PORTS
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input PCLK,
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input PCLK,
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input PRESETn,
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input PRESETn,
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input [31:0] PADDR,
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input [31:0] PADDR,
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input [31:0] PWDATA,
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input [31:0] PWDATA,
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input PWRITE,
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input PWRITE,
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input PSELx,
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input PSELx,
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input PENABLE,
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input PENABLE,
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output PREADY,
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output PREADY,
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output PSLVERR,
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output PSLVERR,
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output INT_RX,
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output INT_RX,
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output INT_TX,
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output INT_TX,
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output [31:0] PRDATA,
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output [31:0] PRDATA,
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//I2C OUTPUT
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//I2C OUTPUT
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inout SDA,
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inout SDA,
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inout SCL
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inout SCL
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);
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);
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wire RESET_N;
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wire RESET_N;
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//THIS IS USED TO RESET FIFO
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//THIS IS USED TO RESET FIFO
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assign RESET_N = (PRESETn == 0)?1'b1:1'b0;
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assign RESET_N = (PRESETn == 0)?1'b1:1'b0;
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//WIRES USED TO CONECT BLOCK WITH EACH OTHER
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//WIRES USED TO CONECT BLOCK WITH EACH OTHER
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wire TX_RD_EN;
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wire TX_RD_EN;
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wire TX_F_EMPTY;
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wire TX_F_EMPTY;
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wire TX_F_FULL;
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wire TX_F_FULL;
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wire [31:0] TX_DATA_IN;
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wire [31:0] TX_DATA_IN;
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wire [31:0] TX_DATA_OUT;
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wire [31:0] TX_DATA_OUT;
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wire TX_WRITE_ENA;
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wire TX_WRITE_ENA;
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wire RX_RD_EN;
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wire RX_RD_EN;
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wire RX_F_EMPTY;
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wire RX_F_EMPTY;
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wire RX_F_FULL;
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wire RX_F_FULL;
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wire [31:0] RX_DATA_IN;
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wire [31:0] RX_DATA_IN;
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wire [31:0] RX_DATA_OUT;
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wire [31:0] RX_DATA_OUT;
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wire RX_WRITE_ENA;
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wire RX_WRITE_ENA;
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wire [13:0] REGISTER_CONFIG;
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wire [13:0] REGISTER_CONFIG;
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wire error;
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wire error;
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wire tx_empty;
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wire tx_empty;
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wire rx_empty;
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wire rx_empty;
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wire w_pwrite;
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wire w_full;
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wire w_full_tx;
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assign w_pwrite = (PWRITE == 1'b0)?1'b1:1'b0;
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//CONECTIONS WITH FIFO TX
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//CONECTIONS WITH FIFO TX
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fifo DUT_FIFO_TX (
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fifo DUT_FIFO_TX (
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.clock(PCLK),
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.clock(PCLK),
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.reset(RESET_N),
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.reset(RESET_N),
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.wr_en(TX_WRITE_ENA),
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.wr_en(TX_WRITE_ENA),
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.rd_en(TX_RD_EN),
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.rd_en(TX_RD_EN),
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.data_in(TX_DATA_IN),
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.data_in(TX_DATA_IN),
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.f_full(TX_F_FULL),
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.f_full(w_full),
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.f_empty(TX_F_EMPTY),
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.f_empty(TX_F_EMPTY),
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.data_out(TX_DATA_OUT)
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.data_out(TX_DATA_OUT)
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);
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);
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and(w_full_tx,w_pwrite,w_full);
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assign TX_F_FULL = w_full_tx;
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//CONECTIONS WITH FIFO RX
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//CONECTIONS WITH FIFO RX
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fifo DUT_FIFO_RX (
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fifo DUT_FIFO_RX (
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.clock(PCLK),
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.clock(PCLK),
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.reset(RESET_N),
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.reset(RESET_N),
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.wr_en(RX_WRITE_ENA),
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.wr_en(RX_WRITE_ENA),
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.rd_en(RX_RD_EN),
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.rd_en(RX_RD_EN),
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.data_in(RX_DATA_IN),
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.data_in(RX_DATA_IN),
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.f_full(RX_F_FULL),
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.f_full(RX_F_FULL),
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.f_empty(RX_F_EMPTY),
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.f_empty(RX_F_EMPTY),
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.data_out(RX_DATA_OUT)
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.data_out(RX_DATA_OUT)
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);
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);
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//CONECTIONS WITH APB AND ALL BLOCKS WHERE IS TWO FIFOS AND I2C CORE
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//CONECTIONS WITH APB AND ALL BLOCKS WHERE IS TWO FIFOS AND I2C CORE
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apb DUT_APB (
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apb DUT_APB (
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.PCLK(PCLK),
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.PCLK(PCLK),
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.PRESETn(PRESETn),
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.PRESETn(PRESETn),
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.PADDR(PADDR),
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.PADDR(PADDR),
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.PRDATA(PRDATA),
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.PRDATA(PRDATA),
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.PWDATA(PWDATA),
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.PWDATA(PWDATA),
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.PWRITE(PWRITE),
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.PWRITE(PWRITE),
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.PSELx(PSELx),
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.PSELx(PSELx),
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.PENABLE(PENABLE),
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.PENABLE(PENABLE),
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.PREADY(PREADY),
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.PREADY(PREADY),
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.PSLVERR(PSLVERR),
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.PSLVERR(PSLVERR),
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.READ_DATA_ON_RX(RX_DATA_OUT),
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.READ_DATA_ON_RX(RX_DATA_OUT),
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.INTERNAL_I2C_REGISTER_CONFIG(REGISTER_CONFIG),
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.INTERNAL_I2C_REGISTER_CONFIG(REGISTER_CONFIG),
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.INT_RX(INT_RX),
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.INT_RX(INT_RX),
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.WR_ENA(TX_WRITE_ENA),
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.WR_ENA(TX_WRITE_ENA),
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.WRITE_DATA_ON_TX(TX_DATA_IN),
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.WRITE_DATA_ON_TX(TX_DATA_IN),
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.RD_ENA(RX_RD_EN),
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.RD_ENA(RX_RD_EN),
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.INT_TX(INT_TX),
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.INT_TX(INT_TX),
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.TX_EMPTY(tx_empty),
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.TX_EMPTY(tx_empty),
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.RX_EMPTY(rx_empty),
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.RX_EMPTY(rx_empty),
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.ERROR(error)
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.ERROR(error)
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);
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);
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//I2C CORE BLOCK WITH ALL ANOTHER BLOCKS
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//I2C CORE BLOCK WITH ALL ANOTHER BLOCKS
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module_i2c DUT_I2C_INTERNAL (
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module_i2c DUT_I2C_INTERNAL (
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.PCLK(PCLK),
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.PCLK(PCLK),
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.PRESETn(PRESETn),
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.PRESETn(PRESETn),
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.fifo_tx_rd_en(TX_RD_EN),
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.fifo_tx_rd_en(TX_RD_EN),
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.fifo_tx_f_full(TX_F_FULL),
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.fifo_tx_f_full(TX_F_FULL),
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.fifo_tx_f_empty(TX_F_EMPTY),
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.fifo_tx_f_empty(TX_F_EMPTY),
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.fifo_tx_data_out(TX_DATA_OUT),
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.fifo_tx_data_out(TX_DATA_OUT),
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.fifo_rx_wr_en(RX_WRITE_ENA),
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.fifo_rx_wr_en(RX_WRITE_ENA),
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.fifo_rx_f_empty(RX_F_EMPTY),
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.fifo_rx_f_empty(RX_F_EMPTY),
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.fifo_rx_data_in(RX_DATA_IN),
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.fifo_rx_data_in(RX_DATA_IN),
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.fifo_rx_f_full(RX_F_FULL),
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.fifo_rx_f_full(RX_F_FULL),
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.DATA_CONFIG_REG(REGISTER_CONFIG),
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.DATA_CONFIG_REG(REGISTER_CONFIG),
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.TX_EMPTY(tx_empty),
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.TX_EMPTY(tx_empty),
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.RX_EMPTY(rx_empty),
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.RX_EMPTY(rx_empty),
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.ERROR(error),
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.ERROR(error),
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.SDA(SDA),
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.SDA(SDA),
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.SCL(SCL)
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.SCL(SCL)
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);
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);
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endmodule
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endmodule
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