------------------------------------------------------------------
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------------------------------------------------------------------
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-- Universal dongle board source code
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-- Universal dongle board source code
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--
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--
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-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
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-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
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--
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--
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-- This source code is free hardware; you can redistribute it and/or
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-- This source code is free hardware; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- version 2.1 of the License, or (at your option) any later version.
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--
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--
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-- This source code is distributed in the hope that it will be useful,
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-- This source code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- Lesser General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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--
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--
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-- The complete text of the GNU Lesser General Public License can be found in
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-- The complete text of the GNU Lesser General Public License can be found in
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-- the file 'lesser.txt'.
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-- the file 'lesser.txt'.
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Company: ArtecDesign
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-- Company: ArtecDesign
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-- Engineer: Jüri Toomessoo
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-- Engineer: Jüri Toomessoo
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--
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--
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-- Create Date: 12:57:23 28/02/2008
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-- Create Date: 12:57:23 28/02/2008
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-- Design Name: Postcode serial pipe Hardware
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-- Design Name: Postcode serial pipe Hardware
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-- Module Name: pc_serializer - rtl
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-- Module Name: pc_serializer - rtl
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity pc_serializer is
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entity pc_serializer is
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Port ( --system signals
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Port( --system signals
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sys_clk : in STD_LOGIC;
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sys_clk : in STD_LOGIC;
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resetn : in STD_LOGIC;
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resetn : in STD_LOGIC;
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--postcode data port
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--postcode data port
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dbg_data : in STD_LOGIC_VECTOR (7 downto 0);
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dbg_data : in STD_LOGIC_VECTOR(7 downto 0);
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dbg_wr : in STD_LOGIC; --write not read
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dbg_wr : in STD_LOGIC; --write not read
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dbg_full : out STD_LOGIC; --write not read
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dbg_full : out STD_LOGIC; --write not read
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dbg_almost_full : out STD_LOGIC;
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dbg_almost_full : out STD_LOGIC;
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dbg_usedw : out STD_LOGIC_VECTOR (12 DOWNTO 0);
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dbg_usedw : out STD_LOGIC_VECTOR(12 DOWNTO 0);
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--debug USB port
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--debug USB port
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dbg_usb_mode_en: in std_logic; -- enable this debug mode
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dbg_usb_mode_en : in std_logic; -- enable this debug mode
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dbg_usb_wr : out std_logic; -- write performed on edge \ of signal
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dbg_usb_wr : out std_logic; -- write performed on edge \ of signal
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dbg_usb_txe_n : in std_logic; -- tx fifo not full (redy for new data if low)
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dbg_usb_txe_n : in std_logic; -- tx fifo not full (redy for new data if low)
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dbg_usb_bd : inout std_logic_vector(7 downto 0) --bus data
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dbg_usb_bd : out std_logic_vector(7 downto 0) --bus data
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);
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);
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end pc_serializer;
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end pc_serializer;
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architecture rtl of pc_serializer is
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architecture rtl of pc_serializer is
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component fifo
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component fifo
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PORT
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PORT(
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(
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aclr : IN STD_LOGIC ;
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aclr : IN STD_LOGIC ;
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clock : IN STD_LOGIC ;
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clock : IN STD_LOGIC;
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data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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rdreq : IN STD_LOGIC ;
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rdreq : IN STD_LOGIC;
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wrreq : IN STD_LOGIC ;
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wrreq : IN STD_LOGIC;
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almost_full : OUT STD_LOGIC ;
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almost_full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC ;
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empty : OUT STD_LOGIC;
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full : OUT STD_LOGIC ;
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full : OUT STD_LOGIC;
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q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
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usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
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);
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);
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end component;
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end component;
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--type state is (RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs); -- simple ASCII converter to USB fifo
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--type state is (RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs); -- simple ASCII converter to USB fifo
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signal CS : std_logic_vector(8 downto 0);--state;
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signal CS : std_logic_vector(8 downto 0); --state;
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signal RETS : std_logic_vector(8 downto 0); --state;
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signal RETS : std_logic_vector(8 downto 0); --state;
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signal next_char : std_logic_vector(7 downto 0); --bus data
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signal next_char : std_logic_vector(7 downto 0); --bus data
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signal ascii_char : std_logic_vector(7 downto 0); --bus data
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signal ascii_char : std_logic_vector(7 downto 0); --bus data
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signal in_nibble : std_logic_vector(3 downto 0); --bus data
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signal in_nibble : std_logic_vector(3 downto 0); --bus data
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signal usb_send_char : std_logic_vector(7 downto 0); --bus data
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signal usb_send_char : std_logic_vector(7 downto 0); --bus data
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signal count : std_logic_vector(3 downto 0); --internal counter
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signal count : std_logic_vector(3 downto 0); --internal counter
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signal dly_count : std_logic_vector(15 downto 0); --internal counter
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signal dly_count : std_logic_vector(15 downto 0); --internal counter
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signal dbg_wr_pulse : std_logic; --active reset
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signal dbg_wr_pulse : std_logic; --active reset
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signal dbg_wrd : std_logic; --active reset
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signal dbg_wrd : std_logic; --active reset
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signal dbg_wr_len : std_logic; --active reset
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--signal dbg_wr_len : std_logic; --active reset
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signal usb_send : std_logic; --active reset
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signal usb_send : std_logic; --active reset
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signal rdreq_sig : std_logic; --active reset
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signal rdreq_sig : std_logic; --active reset
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signal empty_sig : std_logic; --active reset
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signal empty_sig : std_logic; --active reset
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signal full_sig : std_logic; --active reset
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signal full_sig : std_logic; --active reset
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signal almost_full : std_logic; --active reset
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signal almost_full : std_logic; --active reset
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signal q_sig : std_logic_vector(7 downto 0); --bus data
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signal q_sig : std_logic_vector(7 downto 0); --bus data
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signal reset : std_logic; --active reset
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signal reset : std_logic; --active reset
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signal half_clk : std_logic; --active reset
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signal half_clk : std_logic; --active reset
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--RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs
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--RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs
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constant RESETs: std_logic_vector(8 downto 0) := "000000001"; -- char /n
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constant RESETs : std_logic_vector(8 downto 0) := "000000001"; -- char /n
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constant HEXMARKs: std_logic_vector(8 downto 0) := "000000010"; -- char /n
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constant HEXMARKs : std_logic_vector(8 downto 0) := "000000010"; -- char /n
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constant MSNIBBLEs: std_logic_vector(8 downto 0) := "000000100"; -- char /n
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constant MSNIBBLEs : std_logic_vector(8 downto 0) := "000000100"; -- char /n
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constant LSNIBBLEs: std_logic_vector(8 downto 0) := "000001000"; -- char /n
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constant LSNIBBLEs : std_logic_vector(8 downto 0) := "000001000"; -- char /n
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constant LINEFDs: std_logic_vector(8 downto 0) := "000010000"; -- char /n
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constant LINEFDs : std_logic_vector(8 downto 0) := "000010000"; -- char /n
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constant CRs: std_logic_vector(8 downto 0) := "000100000"; -- char /n
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constant CRs : std_logic_vector(8 downto 0) := "000100000"; -- char /n
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constant START_WRITEs: std_logic_vector(8 downto 0):= "001000000"; -- char /n
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constant START_WRITEs : std_logic_vector(8 downto 0) := "001000000"; -- char /n
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constant WAITs: std_logic_vector(8 downto 0) := "010000000"; -- char /n
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constant WAITs : std_logic_vector(8 downto 0) := "010000000"; -- char /n
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constant END_WRITEs: std_logic_vector(8 downto 0) := "100000000"; -- char /n
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constant END_WRITEs : std_logic_vector(8 downto 0) := "100000000"; -- char /n
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constant CHAR_LF : std_logic_vector(7 downto 0):= x"0A"; -- char /n
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constant CHAR_LF : std_logic_vector(7 downto 0) := x"0A"; -- char /n
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constant CHAR_CR : std_logic_vector(7 downto 0):= x"0D"; -- char /n
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constant CHAR_CR : std_logic_vector(7 downto 0) := x"0D"; -- char /n
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constant CHAR_SP : std_logic_vector(7 downto 0):= x"20"; -- space
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constant CHAR_SP : std_logic_vector(7 downto 0) := x"20"; -- space
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constant CHAR_ux : std_logic_vector(7 downto 0):= x"58"; -- fifo full hex marker --upper case x
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constant CHAR_ux : std_logic_vector(7 downto 0) := x"58"; -- fifo full hex marker --upper case x
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constant CHAR_x : std_logic_vector(7 downto 0):= x"78"; -- regular hex marker
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constant CHAR_x : std_logic_vector(7 downto 0) := x"78"; -- regular hex marker
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constant CHAR_0 : std_logic_vector(7 downto 0):= x"30";
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constant CHAR_0 : std_logic_vector(7 downto 0) := x"30";
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constant CHAR_1 : std_logic_vector(7 downto 0):= x"31";
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constant CHAR_1 : std_logic_vector(7 downto 0) := x"31";
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constant CHAR_2 : std_logic_vector(7 downto 0):= x"32";
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constant CHAR_2 : std_logic_vector(7 downto 0) := x"32";
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constant CHAR_3 : std_logic_vector(7 downto 0):= x"33";
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constant CHAR_3 : std_logic_vector(7 downto 0) := x"33";
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constant CHAR_4 : std_logic_vector(7 downto 0):= x"34";
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constant CHAR_4 : std_logic_vector(7 downto 0) := x"34";
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constant CHAR_5 : std_logic_vector(7 downto 0):= x"35";
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constant CHAR_5 : std_logic_vector(7 downto 0) := x"35";
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constant CHAR_6 : std_logic_vector(7 downto 0):= x"36";
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constant CHAR_6 : std_logic_vector(7 downto 0) := x"36";
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constant CHAR_7 : std_logic_vector(7 downto 0):= x"37";
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constant CHAR_7 : std_logic_vector(7 downto 0) := x"37";
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constant CHAR_8 : std_logic_vector(7 downto 0):= x"38";
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constant CHAR_8 : std_logic_vector(7 downto 0) := x"38";
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constant CHAR_9 : std_logic_vector(7 downto 0):= x"39";
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constant CHAR_9 : std_logic_vector(7 downto 0) := x"39";
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constant CHAR_a : std_logic_vector(7 downto 0):= x"41";
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constant CHAR_a : std_logic_vector(7 downto 0) := x"41";
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constant CHAR_b : std_logic_vector(7 downto 0):= x"42";
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constant CHAR_b : std_logic_vector(7 downto 0) := x"42";
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constant CHAR_c : std_logic_vector(7 downto 0):= x"43";
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constant CHAR_c : std_logic_vector(7 downto 0) := x"43";
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constant CHAR_d : std_logic_vector(7 downto 0):= x"44";
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constant CHAR_d : std_logic_vector(7 downto 0) := x"44";
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constant CHAR_e : std_logic_vector(7 downto 0):= x"45";
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constant CHAR_e : std_logic_vector(7 downto 0) := x"45";
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constant CHAR_f : std_logic_vector(7 downto 0):= x"46";
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constant CHAR_f : std_logic_vector(7 downto 0) := x"46";
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begin
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begin
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ascii_char <=CHAR_0 when in_nibble = x"0" else
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ascii_char <=CHAR_0 when in_nibble = x"0" else
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CHAR_1 when in_nibble = x"1" else
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CHAR_1 when in_nibble = x"1" else
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CHAR_2 when in_nibble = x"2" else
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CHAR_2 when in_nibble = x"2" else
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CHAR_3 when in_nibble = x"3" else
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CHAR_3 when in_nibble = x"3" else
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CHAR_4 when in_nibble = x"4" else
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CHAR_4 when in_nibble = x"4" else
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CHAR_5 when in_nibble = x"5" else
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CHAR_5 when in_nibble = x"5" else
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CHAR_6 when in_nibble = x"6" else
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CHAR_6 when in_nibble = x"6" else
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CHAR_7 when in_nibble = x"7" else
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CHAR_7 when in_nibble = x"7" else
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CHAR_8 when in_nibble = x"8" else
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CHAR_8 when in_nibble = x"8" else
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CHAR_9 when in_nibble = x"9" else
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CHAR_9 when in_nibble = x"9" else
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CHAR_a when in_nibble = x"a" else
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CHAR_a when in_nibble = x"a" else
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CHAR_b when in_nibble = x"b" else
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CHAR_b when in_nibble = x"b" else
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CHAR_c when in_nibble = x"c" else
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CHAR_c when in_nibble = x"c" else
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CHAR_d when in_nibble = x"d" else
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CHAR_d when in_nibble = x"d" else
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CHAR_e when in_nibble = x"e" else
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CHAR_e when in_nibble = x"e" else
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CHAR_f when in_nibble = x"f";
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CHAR_f when in_nibble = x"f";
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dbg_usb_bd <= usb_send_char;
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dbg_usb_wr <= usb_send;
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dbg_usb_bd <= usb_send_char when dbg_usb_mode_en = '1' else
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(others=>'Z');
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dbg_usb_wr <= usb_send when dbg_usb_mode_en = '1' else
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'Z';
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SER_SM: process (sys_clk,resetn)
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SER_SM : process(sys_clk, resetn)
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begin -- process
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begin -- process
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if sys_clk'event and sys_clk = '1' then -- rising clock edge
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if sys_clk'event and sys_clk = '1' then -- rising clock edge
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if resetn='0' then --active low reset
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if resetn = '0' then --active low reset
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CS<= RESETs;
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CS <= RESETs;
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in_nibble <= (others=>'0');
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in_nibble <=(others => '0');
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usb_send_char <= (others=>'0');
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usb_send_char <=(others => '0');
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dly_count<= (others=>'0');
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dly_count <=(others => '0');
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usb_send <='0';
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usb_send <= '0';
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RETS <= RESETs;
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RETS <= RESETs;
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rdreq_sig <='0';
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rdreq_sig <= '0';
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count<= (others=>'1');
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count <=(others => '1');
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else
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else
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case CS is
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case CS is
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when RESETs => ----------------------------------------------------------
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when RESETs => ----------------------------------------------------------
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if empty_sig ='0' and dbg_usb_txe_n='0' and dbg_usb_mode_en='1' then --is, can and may send
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if empty_sig = '0' and dbg_usb_txe_n = '0' and dbg_usb_mode_en = '1' then --is, can and may send
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rdreq_sig <='1';
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rdreq_sig <= '1';
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count <= count + 1;
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count <= count + 1;
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RETS <= HEXMARKs;
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RETS <= HEXMARKs;
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dly_count <= x"000F";
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dly_count <= x"000F";
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CS <= END_WRITEs; --cheat as 1 extra cycle is needed for fifo to output data
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CS <= END_WRITEs; --cheat as 1 extra cycle is needed for fifo to output data
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else
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else
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usb_send <='0';
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usb_send <= '0';
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rdreq_sig <='0';
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rdreq_sig <= '0';
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CS <= RESETs; --cheat as 1 extra cycle is needed for fifo to output data
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CS <= RESETs; --cheat as 1 extra cycle is needed for fifo to output data
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end if;
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end if;
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when HEXMARKs => ----------------------------------------------------------
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when HEXMARKs => ----------------------------------------------------------
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rdreq_sig <='0'; --data will be ready on output 'till next read request
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rdreq_sig <= '0'; --data will be ready on output 'till next read request
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--if almost_full='0' then
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--if almost_full='0' then
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usb_send_char <= CHAR_x; --show fifo full status to user by hex x case
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usb_send_char <= CHAR_x; --show fifo full status to user by hex x case
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--else
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--else
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-- usb_send_char <= CHAR_ux; --show fifo full status to user by hex x case
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-- usb_send_char <= CHAR_ux; --show fifo full status to user by hex x case
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--end if;
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--end if;
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in_nibble <= q_sig(7 downto 4); --take fifo output and put to decoder
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in_nibble <= q_sig(7 downto 4); --take fifo output and put to decoder
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RETS <= MSNIBBLEs;
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RETS <= MSNIBBLEs;
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CS <= START_WRITEs;
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CS <= START_WRITEs;
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when MSNIBBLEs => ----------------------------------------------------------
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when MSNIBBLEs => ----------------------------------------------------------
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usb_send_char <= ascii_char; --put MS nibble to output
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usb_send_char <= ascii_char; --put MS nibble to output
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in_nibble <= q_sig(3 downto 0); --take fifo output and put to decoder
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in_nibble <= q_sig(3 downto 0); --take fifo output and put to decoder
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RETS <= LSNIBBLEs;
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RETS <= LSNIBBLEs;
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CS <= START_WRITEs;
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CS <= START_WRITEs;
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when LSNIBBLEs => ----------------------------------------------------------
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when LSNIBBLEs => ----------------------------------------------------------
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usb_send_char <= ascii_char; --put MS nibble to output
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usb_send_char <= ascii_char; --put MS nibble to output
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if count = x"f" then
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if count = x"f" then
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RETS <= CRs;
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RETS <= CRs;
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else
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else
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RETS <= LINEFDs;
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RETS <= LINEFDs;
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end if;
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end if;
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CS <= START_WRITEs;
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CS <= START_WRITEs;
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when CRs => ----------------------------------------------------------
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when CRs => ----------------------------------------------------------
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--if count = x"f" then
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--if count = x"f" then
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usb_send_char <= CHAR_CR; --put line feed
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usb_send_char <= CHAR_CR; --put line feed
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--else
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--else
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-- usb_send_char <= CHAR_SP; --put space
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-- usb_send_char <= CHAR_SP; --put space
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--end if;
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--end if;
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RETS <= LINEFDs;
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RETS <= LINEFDs;
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CS <= START_WRITEs;
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CS <= START_WRITEs;
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when LINEFDs => ----------------------------------------------------------
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when LINEFDs => ----------------------------------------------------------
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if count = x"f" then
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if count = x"f" then
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usb_send_char <= CHAR_LF; --put line feed
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usb_send_char <= CHAR_LF; --put line feed
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else
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else
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usb_send_char <= CHAR_SP; --put space
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usb_send_char <= CHAR_SP; --put space
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end if;
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end if;
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RETS <= RESETs;
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RETS <= RESETs;
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CS <= START_WRITEs;
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CS <= START_WRITEs;
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|
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when START_WRITEs => ----------------------------------------------------------
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when START_WRITEs => ----------------------------------------------------------
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if dly_count /= x"0004" then
|
if dly_count /= x"0004" then
|
if dbg_usb_txe_n='0' then
|
if dbg_usb_txe_n = '0' then
|
usb_send <='1';
|
usb_send <= '1';
|
dly_count <= dly_count + 1;
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dly_count <= dly_count + 1;
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else
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else
|
usb_send <='0'; --remove send signal when txe is falsely asserted
|
usb_send <= '0'; --remove send signal when txe is falsely asserted
|
end if;
|
end if;
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else
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else
|
usb_send <='0';
|
usb_send <= '0';
|
CS <= WAITs;
|
CS <= WAITs;
|
end if;
|
end if;
|
when WAITs => ----------------------------------------------------------
|
when WAITs => ----------------------------------------------------------
|
usb_send <='0';
|
usb_send <= '0';
|
CS <= END_WRITEs;
|
CS <= END_WRITEs;
|
when END_WRITEs => ----------------------------------------------------------
|
when END_WRITEs => ----------------------------------------------------------
|
rdreq_sig <='0'; --used as intermeadiate cheat state when exiting resets
|
rdreq_sig <= '0'; --used as intermeadiate cheat state when exiting resets
|
if dly_count /= x"000F" then
|
if dly_count /= x"000F" then
|
if dbg_usb_txe_n='0' then
|
if dbg_usb_txe_n = '0' then
|
dly_count <= dly_count + 1;
|
dly_count <= dly_count + 1;
|
end if;
|
end if;
|
else
|
else
|
dly_count <= (others=>'0');
|
dly_count <=(others => '0');
|
CS <= RETS;
|
CS <= RETS;
|
end if;
|
end if;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process SER_SM;
|
end process SER_SM;
|
|
|
|
|
SYNCER: process (sys_clk,resetn) --make slower clock and 2 cycle write pulse
|
SYNCER: process (sys_clk,resetn) --make slower clock and 2 cycle write pulse
|
begin -- process
|
begin -- process
|
if sys_clk'event and sys_clk = '1' then -- rising clock edge
|
if sys_clk'event and sys_clk = '1' then -- rising clock edge
|
if resetn='0' then --active low reset
|
if resetn = '0' then --active low reset
|
dbg_wr_pulse <='0';
|
dbg_wr_pulse <='0';
|
dbg_wr_len <='0';
|
--dbg_wr_len <= '0';
|
dbg_wrd <='0';
|
dbg_wrd <='0';
|
else
|
else
|
dbg_wrd <= dbg_wr;
|
dbg_wrd <= dbg_wr;
|
if dbg_wrd='0' and dbg_wr='1' then -- rising front on fifo write
|
if dbg_wrd = '0' and dbg_wr = '1' then -- rising front on fifo write
|
dbg_wr_pulse <='1';
|
dbg_wr_pulse <= '1';
|
else
|
else
|
dbg_wr_pulse <='0';
|
dbg_wr_pulse <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process SYNCER;
|
end process SYNCER;
|
|
|
|
|
reset <= not resetn;
|
reset <= not resetn;
|
dbg_full <= full_sig;
|
dbg_full <= full_sig;
|
dbg_almost_full<= almost_full;
|
dbg_almost_full <= almost_full;
|
fifo_inst : fifo PORT MAP (
|
fifo_inst : fifo PORT MAP(
|
--system signals
|
--system signals
|
aclr => reset,
|
aclr => reset,
|
clock => sys_clk, --make serial back end work 2 times slower as FDTI chip max timing length is 80 ns
|
clock => sys_clk, --make serial back end work 2 times slower as FDTI chip max timing length is 80 ns
|
-- push interface
|
-- push interface
|
data => dbg_data,
|
data => dbg_data,
|
wrreq => dbg_wr_pulse,
|
wrreq => dbg_wr_pulse,
|
almost_full => almost_full,
|
almost_full => almost_full,
|
usedw => dbg_usedw,
|
usedw => dbg_usedw,
|
--pop interface
|
--pop interface
|
rdreq => rdreq_sig,
|
rdreq => rdreq_sig,
|
empty => empty_sig,
|
empty => empty_sig,
|
full => full_sig,
|
full => full_sig,
|
q => q_sig
|
q => q_sig
|
);
|
);
|
|
|
|
|
|
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|
