-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright (C) 2011
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- This program is free software: you can redistribute it and/or modify
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- it under the terms of the GNU General Public License as published by
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-- you may not use this file except in compliance with the License.
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-- the Free Software Foundation, either version 3 of the License, or
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-- You may obtain a copy of the License at
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- Unless required by applicable law or agreed to in writing, software
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib;
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LIBRARY IEEE, common_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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ENTITY tb_common_counter IS
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ENTITY tb_common_counter IS
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END tb_common_counter;
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END tb_common_counter;
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ARCHITECTURE tb OF tb_common_counter IS
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ARCHITECTURE tb OF tb_common_counter IS
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CONSTANT clk_period : TIME := 10 ns;
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CONSTANT clk_period : TIME := 10 ns;
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CONSTANT c_cnt_init : NATURAL := 3;
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CONSTANT c_cnt_init : NATURAL := 3;
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CONSTANT c_cnt_w : NATURAL := 5;
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CONSTANT c_cnt_w : NATURAL := 5;
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SIGNAL rst : STD_LOGIC;
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SIGNAL rst : STD_LOGIC;
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL cnt_clr : STD_LOGIC := '0'; -- synchronous cnt_clr is only interpreted when clken is active
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SIGNAL cnt_clr : STD_LOGIC := '0'; -- synchronous cnt_clr is only interpreted when clken is active
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SIGNAL cnt_ld : STD_LOGIC := '0'; -- cnt_ld loads the output count with the input load value, independent of cnt_en
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SIGNAL cnt_ld : STD_LOGIC := '0'; -- cnt_ld loads the output count with the input load value, independent of cnt_en
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SIGNAL cnt_en : STD_LOGIC := '1';
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SIGNAL cnt_en : STD_LOGIC := '1';
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SIGNAL load : STD_LOGIC_VECTOR(c_cnt_w-1 DOWNTO 0) := TO_UVEC(c_cnt_init, c_cnt_w);
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SIGNAL load : STD_LOGIC_VECTOR(c_cnt_w-1 DOWNTO 0) := TO_UVEC(c_cnt_init, c_cnt_w);
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SIGNAL count : STD_LOGIC_VECTOR(c_cnt_w-1 DOWNTO 0);
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SIGNAL count : STD_LOGIC_VECTOR(c_cnt_w-1 DOWNTO 0);
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SIGNAL cnt_max : STD_LOGIC_VECTOR(c_cnt_w-1 DOWNTO 0);
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SIGNAL cnt_max : STD_LOGIC_VECTOR(c_cnt_w-1 DOWNTO 0);
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BEGIN
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BEGIN
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clk <= NOT clk AFTER clk_period/2;
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clk <= NOT clk AFTER clk_period/2;
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rst <= '1', '0' AFTER clk_period*3;
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rst <= '1', '0' AFTER clk_period*3;
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-- run 1 us
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-- run 1 us
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p_in_stimuli : PROCESS
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p_in_stimuli : PROCESS
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BEGIN
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BEGIN
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cnt_clr <= '0';
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cnt_clr <= '0';
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cnt_ld <= '0';
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cnt_ld <= '0';
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cnt_en <= '0';
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cnt_en <= '0';
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cnt_max <= (OTHERS => '0');
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cnt_max <= (OTHERS => '0');
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WAIT UNTIL rst = '0';
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WAIT UNTIL rst = '0';
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WAIT UNTIL rising_edge(clk);
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WAIT UNTIL rising_edge(clk);
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-- Start counting
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-- Start counting
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cnt_en <= '1';
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cnt_en <= '1';
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FOR I IN 0 TO 9 LOOP
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FOR I IN 0 TO 9 LOOP
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WAIT UNTIL rising_edge(clk);
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WAIT UNTIL rising_edge(clk);
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END LOOP;
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END LOOP;
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-- Reload counter
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-- Reload counter
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cnt_ld <= '1';
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cnt_ld <= '1';
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WAIT UNTIL rising_edge(clk);
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WAIT UNTIL rising_edge(clk);
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cnt_ld <= '0';
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cnt_ld <= '0';
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FOR I IN 0 TO 9 LOOP
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FOR I IN 0 TO 9 LOOP
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WAIT UNTIL rising_edge(clk);
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WAIT UNTIL rising_edge(clk);
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END LOOP;
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END LOOP;
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-- briefly stop counting
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-- briefly stop counting
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cnt_en <= '0';
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cnt_en <= '0';
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WAIT UNTIL rising_edge(clk);
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WAIT UNTIL rising_edge(clk);
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-- countine counting
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-- countine counting
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cnt_en <= '1';
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cnt_en <= '1';
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FOR I IN 0 TO 9 LOOP
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FOR I IN 0 TO 9 LOOP
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WAIT UNTIL rising_edge(clk);
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WAIT UNTIL rising_edge(clk);
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END LOOP;
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END LOOP;
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-- set the cnt_max
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-- set the cnt_max
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cnt_max <= TO_UVEC(2**(c_cnt_w-1), c_cnt_w);
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cnt_max <= TO_UVEC(2**(c_cnt_w-1), c_cnt_w);
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WAIT;
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WAIT;
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END PROCESS;
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END PROCESS;
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-- device under test
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-- device under test
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u_dut : ENTITY work.common_counter
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u_dut : ENTITY work.common_counter
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GENERIC MAP (
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GENERIC MAP (
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g_init => c_cnt_init,
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g_init => c_cnt_init,
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g_width => c_cnt_w,
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g_width => c_cnt_w,
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g_step_size => 1
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g_step_size => 1
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)
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)
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PORT MAP (
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PORT MAP (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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cnt_clr => cnt_clr,
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cnt_clr => cnt_clr,
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cnt_ld => cnt_ld,
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cnt_ld => cnt_ld,
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cnt_en => cnt_en,
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cnt_en => cnt_en,
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cnt_max => cnt_max,
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cnt_max => cnt_max,
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load => load,
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load => load,
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count => count
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count => count
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);
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);
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END tb;
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END tb;
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