-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright 2020
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- You may obtain a copy of the License at
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--
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Purpose : Capture a block of streaming data for analysis via MM access
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-- Purpose : Capture a block of streaming data for analysis via MM access
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-- Description :
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-- Description :
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-- The first g_nof_data valid streaming data input words are stored in the
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-- The first g_nof_data valid streaming data input words are stored in the
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-- data buffer. Then they can be read via the MM interface. Dependent on
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-- data buffer. Then they can be read via the MM interface. Dependent on
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-- g_use_in_sync the nxt block of valid streaming data input words gets
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-- g_use_in_sync the nxt block of valid streaming data input words gets
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-- stored when a new in_sync occurs or when the last word was read from via
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-- stored when a new in_sync occurs or when the last word was read from via
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-- the MM interface.
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-- the MM interface.
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-- Remarks:
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-- Remarks:
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-- . The actual RAM usage depends on g_data_w. Unused bits are forced to '0'
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-- . The actual RAM usage depends on g_data_w. Unused bits are forced to '0'
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-- when read.
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-- when read.
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-- . The c_mm_factor must be a power of 2 factor. Typically c_mm_factor=1 is
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-- . The c_mm_factor must be a power of 2 factor. Typically c_mm_factor=1 is
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-- sufficient for most purposes. If the application only requires
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-- sufficient for most purposes. If the application only requires
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-- eg. c_mm_factor=3 then it needs to extend the data to c_mm_factor=4.
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-- eg. c_mm_factor=3 then it needs to extend the data to c_mm_factor=4.
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-- . If c_mm_factor=2 then in_data[g_data_w/2-1:0] will appear at MM address
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-- . If c_mm_factor=2 then in_data[g_data_w/2-1:0] will appear at MM address
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-- even and in_data[g_data_w-1:g_data_w/2] at address odd.
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-- even and in_data[g_data_w-1:g_data_w/2] at address odd.
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-- The advantage of splitting at g_data_w/2 instead of at c_word_w=32 is
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-- The advantage of splitting at g_data_w/2 instead of at c_word_w=32 is
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-- that streaming 36b data can then map on 18b RAM still fit in a single
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-- that streaming 36b data can then map on 18b RAM still fit in a single
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-- RAM block. Whereas mapping the LS 32b part at even address and the MS 4b
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-- RAM block. Whereas mapping the LS 32b part at even address and the MS 4b
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-- part at odd address would require using c_word_w=32b RAM that could
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-- part at odd address would require using c_word_w=32b RAM that could
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-- require two RAM blocks. For g_data_w=2*c_word_w=64b there is no
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-- require two RAM blocks. For g_data_w=2*c_word_w=64b there is no
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-- difference between these 2 schemes. Hence by rising the g_data_w to a
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-- difference between these 2 schemes. Hence by rising the g_data_w to a
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-- power of 2 multiple of 32b the user can enforce using splitting the data
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-- power of 2 multiple of 32b the user can enforce using splitting the data
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-- a c_word_w parts.
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-- a c_word_w parts.
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LIBRARY IEEE, common_pkg_lib, mm_lib, technology_lib, common_ram_lib, common_counter_lib, common_components_lib;
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LIBRARY IEEE, common_pkg_lib, astron_mm_lib, astron_ram_lib, astron_counter_lib, common_components_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_ram_lib.common_ram_pkg.ALL;
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USE astron_ram_lib.common_ram_pkg.ALL;
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USE work.diag_pkg.ALL;
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USE work.diag_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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--USE technology_lib.technology_select_pkg.ALL;
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ENTITY diag_data_buffer IS
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ENTITY diag_data_buffer IS
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GENERIC (
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GENERIC (
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g_technology : NATURAL := c_tech_select_default;
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g_technology : NATURAL := 0;
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g_data_w : NATURAL := 32;
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g_data_w : NATURAL := 32;
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g_nof_data : NATURAL := 1024;
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g_nof_data : NATURAL := 1024;
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g_use_in_sync : BOOLEAN := FALSE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
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g_use_in_sync : BOOLEAN := FALSE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
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);
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);
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PORT (
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PORT (
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-- Memory-mapped clock domain
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-- Memory-mapped clock domain
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mm_rst : IN STD_LOGIC;
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mm_rst : IN STD_LOGIC;
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mm_clk : IN STD_LOGIC;
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mm_clk : IN STD_LOGIC;
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ram_mm_mosi : IN t_mem_mosi; -- read and overwrite access to the data buffer
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ram_mm_mosi : IN t_mem_mosi; -- read and overwrite access to the data buffer
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ram_mm_miso : OUT t_mem_miso;
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ram_mm_miso : OUT t_mem_miso;
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reg_mm_mosi : IN t_mem_mosi := c_mem_mosi_rst;
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reg_mm_mosi : IN t_mem_mosi := c_mem_mosi_rst;
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reg_mm_miso : OUT t_mem_miso;
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reg_mm_miso : OUT t_mem_miso;
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-- Streaming clock domain
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-- Streaming clock domain
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st_rst : IN STD_LOGIC;
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st_rst : IN STD_LOGIC;
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st_clk : IN STD_LOGIC;
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st_clk : IN STD_LOGIC;
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in_data : IN STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
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in_data : IN STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
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in_sync : IN STD_LOGIC := '0';
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in_sync : IN STD_LOGIC := '0';
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in_val : IN STD_LOGIC
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in_val : IN STD_LOGIC
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);
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);
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END diag_data_buffer;
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END diag_data_buffer;
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ARCHITECTURE rtl OF diag_data_buffer IS
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ARCHITECTURE rtl OF diag_data_buffer IS
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CONSTANT c_mm_factor : NATURAL := ceil_div(g_data_w, c_word_w); -- must be a power of 2 multiple
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CONSTANT c_mm_factor : NATURAL := ceil_div(g_data_w, c_word_w); -- must be a power of 2 multiple
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CONSTANT c_nof_data_mm : NATURAL := g_nof_data*c_mm_factor;
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CONSTANT c_nof_data_mm : NATURAL := g_nof_data*c_mm_factor;
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CONSTANT g_data_mm_w : NATURAL := g_data_w/c_mm_factor;
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CONSTANT g_data_mm_w : NATURAL := g_data_w/c_mm_factor;
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CONSTANT c_buf_mm : t_c_mem := (latency => 1,
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CONSTANT c_buf_mm : t_c_mem := (latency => 1,
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adr_w => ceil_log2(c_nof_data_mm),
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adr_w => ceil_log2(c_nof_data_mm),
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dat_w => g_data_mm_w,
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dat_w => g_data_mm_w,
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nof_dat => c_nof_data_mm,
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nof_dat => c_nof_data_mm,
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init_sl => '0');
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init_sl => '0');
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CONSTANT c_buf_st : t_c_mem := (latency => 1,
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CONSTANT c_buf_st : t_c_mem := (latency => 1,
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adr_w => ceil_log2(g_nof_data),
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adr_w => ceil_log2(g_nof_data),
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dat_w => g_data_w,
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dat_w => g_data_w,
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nof_dat => g_nof_data,
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nof_dat => g_nof_data,
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init_sl => '0');
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init_sl => '0');
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CONSTANT c_reg : t_c_mem := (latency => 1,
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CONSTANT c_reg : t_c_mem := (latency => 1,
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adr_w => c_diag_db_reg_adr_w,
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adr_w => c_diag_db_reg_adr_w,
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dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
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dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
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nof_dat => c_diag_db_reg_nof_dat, -- 1: word_cnt; 0:sync_cnt
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nof_dat => c_diag_db_reg_nof_dat, -- 1: word_cnt; 0:sync_cnt
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init_sl => '0');
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init_sl => '0');
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SIGNAL i_ram_mm_miso : t_mem_miso := c_mem_miso_rst; -- used to avoid vsim-8684 error "No drivers exist" for the unused fields
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SIGNAL i_ram_mm_miso : t_mem_miso := c_mem_miso_rst; -- used to avoid vsim-8684 error "No drivers exist" for the unused fields
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SIGNAL rd_last : STD_LOGIC;
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SIGNAL rd_last : STD_LOGIC;
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SIGNAL wr_sync : STD_LOGIC;
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SIGNAL wr_sync : STD_LOGIC;
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SIGNAL wr_done : STD_LOGIC;
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SIGNAL wr_done : STD_LOGIC;
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SIGNAL nxt_wr_done : STD_LOGIC;
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SIGNAL nxt_wr_done : STD_LOGIC;
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SIGNAL wr_data : STD_LOGIC_VECTOR(c_buf_st.dat_w-1 DOWNTO 0);
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SIGNAL wr_data : STD_LOGIC_VECTOR(c_buf_st.dat_w-1 DOWNTO 0);
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SIGNAL nxt_wr_data : STD_LOGIC_VECTOR(c_buf_st.dat_w-1 DOWNTO 0);
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SIGNAL nxt_wr_data : STD_LOGIC_VECTOR(c_buf_st.dat_w-1 DOWNTO 0);
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SIGNAL wr_addr : STD_LOGIC_VECTOR(c_buf_st.adr_w-1 DOWNTO 0);
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SIGNAL wr_addr : STD_LOGIC_VECTOR(c_buf_st.adr_w-1 DOWNTO 0);
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SIGNAL nxt_wr_addr : STD_LOGIC_VECTOR(c_buf_st.adr_w-1 DOWNTO 0);
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SIGNAL nxt_wr_addr : STD_LOGIC_VECTOR(c_buf_st.adr_w-1 DOWNTO 0);
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SIGNAL wr_en : STD_LOGIC;
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SIGNAL wr_en : STD_LOGIC;
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SIGNAL nxt_wr_en : STD_LOGIC;
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SIGNAL nxt_wr_en : STD_LOGIC;
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SIGNAL reg_rd_arr : STD_LOGIC_VECTOR(c_reg.nof_dat-1 DOWNTO 0);
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SIGNAL reg_rd_arr : STD_LOGIC_VECTOR(c_reg.nof_dat-1 DOWNTO 0);
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SIGNAL reg_slv : STD_LOGIC_VECTOR(c_reg.nof_dat*c_word_w-1 DOWNTO 0);
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SIGNAL reg_slv : STD_LOGIC_VECTOR(c_reg.nof_dat*c_word_w-1 DOWNTO 0);
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SIGNAL sync_cnt_clr : STD_LOGIC := '0';
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SIGNAL sync_cnt_clr : STD_LOGIC := '0';
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SIGNAL sync_cnt : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- Nof times buffer has been written
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SIGNAL sync_cnt : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- Nof times buffer has been written
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SIGNAL word_cnt : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := (OTHERS=>'0');
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SIGNAL word_cnt : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := (OTHERS=>'0');
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BEGIN
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BEGIN
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ASSERT c_mm_factor=2**true_log2(c_mm_factor) REPORT "Only support mixed width data that uses a power of 2 multiple." SEVERITY FAILURE;
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ASSERT c_mm_factor=2**true_log2(c_mm_factor) REPORT "Only support mixed width data that uses a power of 2 multiple." SEVERITY FAILURE;
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ram_mm_miso <= i_ram_mm_miso;
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ram_mm_miso <= i_ram_mm_miso;
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rd_last <= '1' WHEN UNSIGNED(ram_mm_mosi.address(c_buf_mm.adr_w-1 DOWNTO 0))=c_nof_data_mm-1 AND ram_mm_mosi.rd='1' ELSE '0';
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rd_last <= '1' WHEN UNSIGNED(ram_mm_mosi.address(c_buf_mm.adr_w-1 DOWNTO 0))=c_nof_data_mm-1 AND ram_mm_mosi.rd='1' ELSE '0';
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-- Determine the write trigger
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-- Determine the write trigger
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use_rd_last : IF g_use_in_sync=FALSE GENERATE
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use_rd_last : IF g_use_in_sync=FALSE GENERATE
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u_wr_sync : ENTITY common_components_lib.common_spulse
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u_wr_sync : ENTITY common_components_lib.common_spulse
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GENERIC MAP (
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GENERIC MAP (
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g_delay_len => c_meta_delay_len
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g_delay_len => c_meta_delay_len
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)
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)
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PORT MAP (
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PORT MAP (
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in_rst => mm_rst,
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in_rst => mm_rst,
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in_clk => mm_clk,
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in_clk => mm_clk,
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in_pulse => rd_last,
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in_pulse => rd_last,
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out_rst => st_rst,
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out_rst => st_rst,
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out_clk => st_clk,
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out_clk => st_clk,
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out_pulse => wr_sync
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out_pulse => wr_sync
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);
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);
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END GENERATE;
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END GENERATE;
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use_in_sync : IF g_use_in_sync=TRUE GENERATE
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use_in_sync : IF g_use_in_sync=TRUE GENERATE
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sync_cnt_clr <= rd_last; -- clear sync_cnt register on read of last data
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sync_cnt_clr <= rd_last; -- clear sync_cnt register on read of last data
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wr_sync <= in_sync;
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wr_sync <= in_sync;
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END GENERATE;
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END GENERATE;
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p_st_clk : PROCESS (st_clk, st_rst)
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p_st_clk : PROCESS (st_clk, st_rst)
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BEGIN
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BEGIN
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IF st_rst='1' THEN
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IF st_rst='1' THEN
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wr_data <= (OTHERS => '0');
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wr_data <= (OTHERS => '0');
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wr_addr <= (OTHERS => '0');
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wr_addr <= (OTHERS => '0');
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wr_en <= '0';
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wr_en <= '0';
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wr_done <= '0';
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wr_done <= '0';
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ELSIF rising_edge(st_clk) THEN
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ELSIF rising_edge(st_clk) THEN
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wr_data <= nxt_wr_data;
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wr_data <= nxt_wr_data;
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wr_addr <= nxt_wr_addr;
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wr_addr <= nxt_wr_addr;
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wr_en <= nxt_wr_en;
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wr_en <= nxt_wr_en;
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wr_done <= nxt_wr_done;
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wr_done <= nxt_wr_done;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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-- Write access control
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-- Write access control
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nxt_wr_data <= in_data;
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nxt_wr_data <= in_data;
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nxt_wr_en <= in_val AND NOT nxt_wr_done;
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nxt_wr_en <= in_val AND NOT nxt_wr_done;
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p_wr_addr : PROCESS (wr_done, wr_addr, wr_sync, wr_en)
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p_wr_addr : PROCESS (wr_done, wr_addr, wr_sync, wr_en)
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BEGIN
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BEGIN
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nxt_wr_done <= wr_done;
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nxt_wr_done <= wr_done;
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nxt_wr_addr <= wr_addr;
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nxt_wr_addr <= wr_addr;
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IF wr_sync='1' THEN
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IF wr_sync='1' THEN
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nxt_wr_done <= '0';
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nxt_wr_done <= '0';
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nxt_wr_addr <= (OTHERS => '0');
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nxt_wr_addr <= (OTHERS => '0');
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ELSIF wr_en='1' THEN
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ELSIF wr_en='1' THEN
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IF UNSIGNED(wr_addr)=g_nof_data-1 THEN
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IF UNSIGNED(wr_addr)=g_nof_data-1 THEN
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nxt_wr_done <= '1'; -- keep wr_addr, do not allow wr_addr increment >= g_nof_data to avoid RAM address out-of-bound warning in Modelsim in case c_buf.nof_dat < 2**c_buf.adr_w
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nxt_wr_done <= '1'; -- keep wr_addr, do not allow wr_addr increment >= g_nof_data to avoid RAM address out-of-bound warning in Modelsim in case c_buf.nof_dat < 2**c_buf.adr_w
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ELSE
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ELSE
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nxt_wr_addr <= INCR_UVEC(wr_addr, 1);
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nxt_wr_addr <= INCR_UVEC(wr_addr, 1);
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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u_buf : ENTITY common_ram_lib.common_ram_crw_crw_ratio
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u_buf : ENTITY astron_ram_lib.common_ram_crw_crw_ratio
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GENERIC MAP (
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GENERIC MAP (
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g_technology => g_technology,
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g_technology => g_technology,
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g_ram_a => c_buf_mm,
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g_ram_a => c_buf_mm,
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g_ram_b => c_buf_st,
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g_ram_b => c_buf_st,
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g_init_file => "UNUSED"
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g_init_file => "UNUSED"
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)
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)
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PORT MAP (
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PORT MAP (
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-- MM read/write port clock domain
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-- MM read/write port clock domain
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rst_a => mm_rst,
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rst_a => mm_rst,
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clk_a => mm_clk,
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clk_a => mm_clk,
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wr_en_a => ram_mm_mosi.wr,
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wr_en_a => ram_mm_mosi.wr,
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wr_dat_a => ram_mm_mosi.wrdata(c_buf_mm.dat_w-1 DOWNTO 0),
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wr_dat_a => ram_mm_mosi.wrdata(c_buf_mm.dat_w-1 DOWNTO 0),
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adr_a => ram_mm_mosi.address(c_buf_mm.adr_w-1 DOWNTO 0),
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adr_a => ram_mm_mosi.address(c_buf_mm.adr_w-1 DOWNTO 0),
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rd_en_a => ram_mm_mosi.rd,
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rd_en_a => ram_mm_mosi.rd,
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rd_dat_a => i_ram_mm_miso.rddata(c_buf_mm.dat_w-1 DOWNTO 0),
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rd_dat_a => i_ram_mm_miso.rddata(c_buf_mm.dat_w-1 DOWNTO 0),
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rd_val_a => i_ram_mm_miso.rdval,
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rd_val_a => i_ram_mm_miso.rdval,
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|
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-- ST write only port clock domain
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-- ST write only port clock domain
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rst_b => st_rst,
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rst_b => st_rst,
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clk_b => st_clk,
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clk_b => st_clk,
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wr_en_b => wr_en,
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wr_en_b => wr_en,
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wr_dat_b => wr_data,
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wr_dat_b => wr_data,
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adr_b => wr_addr,
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adr_b => wr_addr,
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rd_en_b => '0',
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rd_en_b => '0',
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rd_dat_b => OPEN,
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rd_dat_b => OPEN,
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rd_val_b => OPEN
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rd_val_b => OPEN
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);
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);
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u_reg : ENTITY mm_lib.common_reg_r_w_dc
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u_reg : ENTITY astron_mm_lib.common_reg_r_w_dc
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GENERIC MAP (
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GENERIC MAP (
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g_reg => c_reg
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g_reg => c_reg
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)
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)
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PORT MAP (
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PORT MAP (
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-- Clocks and reset
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-- Clocks and reset
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mm_rst => mm_rst,
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mm_rst => mm_rst,
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mm_clk => mm_clk,
|
mm_clk => mm_clk,
|
st_rst => st_rst,
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st_rst => st_rst,
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st_clk => st_clk,
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st_clk => st_clk,
|
|
|
-- Memory Mapped Slave in mm_clk domain
|
-- Memory Mapped Slave in mm_clk domain
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sla_in => reg_mm_mosi,
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sla_in => reg_mm_mosi,
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sla_out => reg_mm_miso,
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sla_out => reg_mm_miso,
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|
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-- MM registers in st_clk domain
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-- MM registers in st_clk domain
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reg_wr_arr => OPEN,
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reg_wr_arr => OPEN,
|
reg_rd_arr => reg_rd_arr,
|
reg_rd_arr => reg_rd_arr,
|
in_reg => reg_slv,
|
in_reg => reg_slv,
|
out_reg => OPEN
|
out_reg => OPEN
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);
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);
|
|
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reg_slv <= word_cnt & sync_cnt;
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reg_slv <= word_cnt & sync_cnt;
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|
|
u_word_cnt : ENTITY common_counter_lib.common_counter
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u_word_cnt : ENTITY astron_counter_lib.common_counter
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PORT MAP (
|
PORT MAP (
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rst => st_rst,
|
rst => st_rst,
|
clk => st_clk,
|
clk => st_clk,
|
cnt_en => wr_en,
|
cnt_en => wr_en,
|
cnt_clr => wr_sync,
|
cnt_clr => wr_sync,
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count => word_cnt
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count => word_cnt
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);
|
);
|
|
|
u_sync_cnt : ENTITY common_counter_lib.common_counter
|
u_sync_cnt : ENTITY astron_counter_lib.common_counter
|
PORT MAP (
|
PORT MAP (
|
rst => st_rst,
|
rst => st_rst,
|
clk => st_clk,
|
clk => st_clk,
|
cnt_en => wr_sync,
|
cnt_en => wr_sync,
|
cnt_clr => sync_cnt_clr,
|
cnt_clr => sync_cnt_clr,
|
count => sync_cnt
|
count => sync_cnt
|
);
|
);
|
|
|
END rtl;
|
END rtl;
|
|
|
|
|