-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright (C) 2011
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- This program is free software: you can redistribute it and/or modify
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- it under the terms of the GNU General Public License as published by
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-- you may not use this file except in compliance with the License.
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-- the Free Software Foundation, either version 3 of the License, or
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-- You may obtain a copy of the License at
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- Unless required by applicable law or agreed to in writing, software
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib;
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LIBRARY IEEE, common_pkg_lib;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.MATH_REAL.ALL;
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USE IEEE.MATH_REAL.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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PACKAGE diag_pkg IS
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PACKAGE diag_pkg IS
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- PHY interface tests (e.g. for ethernet, transceivers, lvds, memory)
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-- PHY interface tests (e.g. for ethernet, transceivers, lvds, memory)
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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CONSTANT c_diag_test_mode_no_tst : NATURAL := 0; -- no test, the PHY interface runs in normal user mode
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CONSTANT c_diag_test_mode_no_tst : NATURAL := 0; -- no test, the PHY interface runs in normal user mode
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CONSTANT c_diag_test_mode_loop_local : NATURAL := 1; -- loop back via PHY chip
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CONSTANT c_diag_test_mode_loop_local : NATURAL := 1; -- loop back via PHY chip
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CONSTANT c_diag_test_mode_loop_remote : NATURAL := 2; -- loop back via loopback cable or plug in the connector
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CONSTANT c_diag_test_mode_loop_remote : NATURAL := 2; -- loop back via loopback cable or plug in the connector
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CONSTANT c_diag_test_mode_tx : NATURAL := 4; -- transmit only
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CONSTANT c_diag_test_mode_tx : NATURAL := 4; -- transmit only
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CONSTANT c_diag_test_mode_rx : NATURAL := 5; -- receive only
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CONSTANT c_diag_test_mode_rx : NATURAL := 5; -- receive only
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CONSTANT c_diag_test_mode_tx_rx : NATURAL := 6; -- transmit and receive
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CONSTANT c_diag_test_mode_tx_rx : NATURAL := 6; -- transmit and receive
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CONSTANT c_diag_test_data_lfsr : NATURAL := 0; -- use pseudo random data
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CONSTANT c_diag_test_data_lfsr : NATURAL := 0; -- use pseudo random data
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CONSTANT c_diag_test_data_incr : NATURAL := 1; -- use incrementing counter data
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CONSTANT c_diag_test_data_incr : NATURAL := 1; -- use incrementing counter data
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CONSTANT c_diag_test_duration_quick : NATURAL := 0; -- end Rx test after 1 data frame or word, end Tx test after correspondingly sufficient data frames or words transmitted, or all memory lines
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CONSTANT c_diag_test_duration_quick : NATURAL := 0; -- end Rx test after 1 data frame or word, end Tx test after correspondingly sufficient data frames or words transmitted, or all memory lines
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CONSTANT c_diag_test_duration_normal : NATURAL := 1; -- idem for e.g. 100 data frames or words, or full memory
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CONSTANT c_diag_test_duration_normal : NATURAL := 1; -- idem for e.g. 100 data frames or words, or full memory
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CONSTANT c_diag_test_duration_extra : NATURAL := 2; -- idem for e.g. 100000 data frames or words
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CONSTANT c_diag_test_duration_extra : NATURAL := 2; -- idem for e.g. 100000 data frames or words
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CONSTANT c_diag_test_result_ok : NATURAL := 0; -- test went OK
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CONSTANT c_diag_test_result_ok : NATURAL := 0; -- test went OK
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CONSTANT c_diag_test_result_none : NATURAL := 1; -- test did not run, default
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CONSTANT c_diag_test_result_none : NATURAL := 1; -- test did not run, default
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CONSTANT c_diag_test_result_timeout : NATURAL := 2; -- test started but no valid data was received
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CONSTANT c_diag_test_result_timeout : NATURAL := 2; -- test started but no valid data was received
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CONSTANT c_diag_test_result_error : NATURAL := 3; -- test received valid data, but the value was wrong for one or more
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CONSTANT c_diag_test_result_error : NATURAL := 3; -- test received valid data, but the value was wrong for one or more
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CONSTANT c_diag_test_result_illegal : NATURAL := 4; -- exception, condition that can not occur in the logic
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CONSTANT c_diag_test_result_illegal : NATURAL := 4; -- exception, condition that can not occur in the logic
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Waveform Generator
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-- Waveform Generator
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- control register
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-- control register
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CONSTANT c_diag_wg_mode_w : NATURAL := 8;
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CONSTANT c_diag_wg_mode_w : NATURAL := 8;
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CONSTANT c_diag_wg_nofsamples_w : NATURAL := 16; -- >~ minimum data path block size
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CONSTANT c_diag_wg_nofsamples_w : NATURAL := 16; -- >~ minimum data path block size
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CONSTANT c_diag_wg_phase_w : NATURAL := 16; -- = c_diag_wg_nofsamples_w
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CONSTANT c_diag_wg_phase_w : NATURAL := 16; -- = c_diag_wg_nofsamples_w
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CONSTANT c_diag_wg_freq_w : NATURAL := 31; -- >> c_diag_wg_nofsamples_w, determines the minimum frequency = Fs / 2**c_diag_wg_freq_w
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CONSTANT c_diag_wg_freq_w : NATURAL := 31; -- >> c_diag_wg_nofsamples_w, determines the minimum frequency = Fs / 2**c_diag_wg_freq_w
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CONSTANT c_diag_wg_ampl_w : NATURAL := 17; -- Typically fit DSP multiply 18x18 element so use <= 17, to fit unsigned in 18 bit signed,
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CONSTANT c_diag_wg_ampl_w : NATURAL := 17; -- Typically fit DSP multiply 18x18 element so use <= 17, to fit unsigned in 18 bit signed,
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-- = waveform data width-1 (sign bit) to be able to make a 1 LSBit amplitude sinus
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-- = waveform data width-1 (sign bit) to be able to make a 1 LSBit amplitude sinus
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CONSTANT c_diag_wg_mode_off : NATURAL := 0;
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CONSTANT c_diag_wg_mode_off : NATURAL := 0;
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CONSTANT c_diag_wg_mode_calc : NATURAL := 1;
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CONSTANT c_diag_wg_mode_calc : NATURAL := 1;
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CONSTANT c_diag_wg_mode_repeat : NATURAL := 2;
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CONSTANT c_diag_wg_mode_repeat : NATURAL := 2;
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CONSTANT c_diag_wg_mode_single : NATURAL := 3;
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CONSTANT c_diag_wg_mode_single : NATURAL := 3;
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TYPE t_diag_wg IS RECORD
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TYPE t_diag_wg IS RECORD
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mode : STD_LOGIC_VECTOR(c_diag_wg_mode_w -1 DOWNTO 0);
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mode : STD_LOGIC_VECTOR(c_diag_wg_mode_w -1 DOWNTO 0);
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nof_samples : STD_LOGIC_VECTOR(c_diag_wg_nofsamples_w -1 DOWNTO 0); -- unsigned value
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nof_samples : STD_LOGIC_VECTOR(c_diag_wg_nofsamples_w -1 DOWNTO 0); -- unsigned value
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phase : STD_LOGIC_VECTOR(c_diag_wg_phase_w -1 DOWNTO 0); -- unsigned value
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phase : STD_LOGIC_VECTOR(c_diag_wg_phase_w -1 DOWNTO 0); -- unsigned value
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freq : STD_LOGIC_VECTOR(c_diag_wg_freq_w -1 DOWNTO 0); -- unsigned value
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freq : STD_LOGIC_VECTOR(c_diag_wg_freq_w -1 DOWNTO 0); -- unsigned value
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ampl : STD_LOGIC_VECTOR(c_diag_wg_ampl_w -1 DOWNTO 0); -- unsigned value, range [0:2**c_diag_wg_ampl_w> normalized to range [0 c_diag_wg_gain>
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ampl : STD_LOGIC_VECTOR(c_diag_wg_ampl_w -1 DOWNTO 0); -- unsigned value, range [0:2**c_diag_wg_ampl_w> normalized to range [0 c_diag_wg_gain>
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END RECORD;
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END RECORD;
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CONSTANT c_diag_wg_ampl_norm : REAL := 1.0; -- Use this default amplitude norm = 1.0 when WG data width = WG waveform buffer data width,
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CONSTANT c_diag_wg_ampl_norm : REAL := 1.0; -- Use this default amplitude norm = 1.0 when WG data width = WG waveform buffer data width,
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-- else use extra amplitude unit scaling by (WG data max)/(WG data max + 1)
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-- else use extra amplitude unit scaling by (WG data max)/(WG data max + 1)
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CONSTANT c_diag_wg_gain_w : NATURAL := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
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CONSTANT c_diag_wg_gain_w : NATURAL := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
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-- . use gain 2**0 = 1 to have fulle scale without clipping
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-- . use gain 2**0 = 1 to have fulle scale without clipping
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-- . use gain 2**g_calc_gain_w > 1 to cause clipping
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-- . use gain 2**g_calc_gain_w > 1 to cause clipping
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CONSTANT c_diag_wg_ampl_unit : REAL := 2**REAL(c_diag_wg_ampl_w-c_diag_wg_gain_w)*c_diag_wg_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
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CONSTANT c_diag_wg_ampl_unit : REAL := 2**REAL(c_diag_wg_ampl_w-c_diag_wg_gain_w)*c_diag_wg_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
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CONSTANT c_diag_wg_freq_unit : REAL := 2**REAL(c_diag_wg_freq_w); -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
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CONSTANT c_diag_wg_freq_unit : REAL := 2**REAL(c_diag_wg_freq_w); -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
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CONSTANT c_diag_wg_phase_unit : REAL := 2**REAL(c_diag_wg_phase_w)/ 360.0; -- ^= 1 degree
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CONSTANT c_diag_wg_phase_unit : REAL := 2**REAL(c_diag_wg_phase_w)/ 360.0; -- ^= 1 degree
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CONSTANT c_diag_wg_rst : t_diag_wg := (TO_UVEC(c_diag_wg_mode_off, c_diag_wg_mode_w),
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CONSTANT c_diag_wg_rst : t_diag_wg := (TO_UVEC(c_diag_wg_mode_off, c_diag_wg_mode_w),
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TO_UVEC( 1024, c_diag_wg_nofsamples_w),
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TO_UVEC( 1024, c_diag_wg_nofsamples_w),
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TO_UVEC( 0, c_diag_wg_phase_w),
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TO_UVEC( 0, c_diag_wg_phase_w),
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TO_UVEC( 0, c_diag_wg_freq_w),
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TO_UVEC( 0, c_diag_wg_freq_w),
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TO_UVEC( 0, c_diag_wg_ampl_w));
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TO_UVEC( 0, c_diag_wg_ampl_w));
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TYPE t_diag_wg_arr IS ARRAY (INTEGER RANGE <>) OF t_diag_wg;
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TYPE t_diag_wg_arr IS ARRAY (INTEGER RANGE <>) OF t_diag_wg;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Block Generator
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-- Block Generator
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- control register
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-- control register
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CONSTANT c_diag_bg_reg_nof_dat : NATURAL := 8;
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CONSTANT c_diag_bg_reg_nof_dat : NATURAL := 8;
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CONSTANT c_diag_bg_reg_adr_w : NATURAL := ceil_log2(c_diag_bg_reg_nof_dat);
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CONSTANT c_diag_bg_reg_adr_w : NATURAL := ceil_log2(c_diag_bg_reg_nof_dat);
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CONSTANT c_diag_bg_mode_w : NATURAL := 8;
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CONSTANT c_diag_bg_mode_w : NATURAL := 8;
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CONSTANT c_diag_bg_samples_per_packet_w : NATURAL := 24;
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CONSTANT c_diag_bg_samples_per_packet_w : NATURAL := 24;
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CONSTANT c_diag_bg_blocks_per_sync_w : NATURAL := 24;
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CONSTANT c_diag_bg_blocks_per_sync_w : NATURAL := 24;
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CONSTANT c_diag_bg_gapsize_w : NATURAL := 24;
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CONSTANT c_diag_bg_gapsize_w : NATURAL := 24;
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CONSTANT c_diag_bg_mem_adrs_w : NATURAL := 24;
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CONSTANT c_diag_bg_mem_adrs_w : NATURAL := 24;
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CONSTANT c_diag_bg_mem_low_adrs_w : NATURAL := c_diag_bg_mem_adrs_w;
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CONSTANT c_diag_bg_mem_low_adrs_w : NATURAL := c_diag_bg_mem_adrs_w;
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CONSTANT c_diag_bg_mem_high_adrs_w : NATURAL := c_diag_bg_mem_adrs_w;
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CONSTANT c_diag_bg_mem_high_adrs_w : NATURAL := c_diag_bg_mem_adrs_w;
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CONSTANT c_diag_bg_bsn_init_w : NATURAL := 64;
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CONSTANT c_diag_bg_bsn_init_w : NATURAL := 64;
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TYPE t_diag_block_gen IS RECORD
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TYPE t_diag_block_gen IS RECORD
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enable : STD_LOGIC; -- block enable
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enable : STD_LOGIC; -- block enable
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enable_sync : STD_LOGIC; -- block enable on sync pulse
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enable_sync : STD_LOGIC; -- block enable on sync pulse
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samples_per_packet : STD_LOGIC_VECTOR(c_diag_bg_samples_per_packet_w -1 DOWNTO 0);
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samples_per_packet : STD_LOGIC_VECTOR(c_diag_bg_samples_per_packet_w -1 DOWNTO 0);
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blocks_per_sync : STD_LOGIC_VECTOR(c_diag_bg_blocks_per_sync_w -1 DOWNTO 0);
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blocks_per_sync : STD_LOGIC_VECTOR(c_diag_bg_blocks_per_sync_w -1 DOWNTO 0);
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gapsize : STD_LOGIC_VECTOR(c_diag_bg_gapsize_w -1 DOWNTO 0);
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gapsize : STD_LOGIC_VECTOR(c_diag_bg_gapsize_w -1 DOWNTO 0);
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mem_low_adrs : STD_LOGIC_VECTOR(c_diag_bg_mem_low_adrs_w -1 DOWNTO 0);
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mem_low_adrs : STD_LOGIC_VECTOR(c_diag_bg_mem_low_adrs_w -1 DOWNTO 0);
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mem_high_adrs : STD_LOGIC_VECTOR(c_diag_bg_mem_high_adrs_w -1 DOWNTO 0);
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mem_high_adrs : STD_LOGIC_VECTOR(c_diag_bg_mem_high_adrs_w -1 DOWNTO 0);
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bsn_init : STD_LOGIC_VECTOR(c_diag_bg_bsn_init_w -1 DOWNTO 0);
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bsn_init : STD_LOGIC_VECTOR(c_diag_bg_bsn_init_w -1 DOWNTO 0);
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END RECORD;
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END RECORD;
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CONSTANT c_diag_block_gen_rst : t_diag_block_gen := ( '0',
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CONSTANT c_diag_block_gen_rst : t_diag_block_gen := ( '0',
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'0',
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'0',
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TO_UVEC( 256, c_diag_bg_samples_per_packet_w),
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TO_UVEC( 256, c_diag_bg_samples_per_packet_w),
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TO_UVEC( 10, c_diag_bg_blocks_per_sync_w),
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TO_UVEC( 10, c_diag_bg_blocks_per_sync_w),
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TO_UVEC( 128, c_diag_bg_gapsize_w),
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TO_UVEC( 128, c_diag_bg_gapsize_w),
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TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
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TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
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TO_UVEC( 1, c_diag_bg_mem_high_adrs_w),
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TO_UVEC( 1, c_diag_bg_mem_high_adrs_w),
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TO_UVEC( 0, c_diag_bg_bsn_init_w));
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TO_UVEC( 0, c_diag_bg_bsn_init_w));
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CONSTANT c_diag_block_gen_enabled : t_diag_block_gen := ( '1',
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CONSTANT c_diag_block_gen_enabled : t_diag_block_gen := ( '1',
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'0',
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'0',
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TO_UVEC( 50, c_diag_bg_samples_per_packet_w),
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TO_UVEC( 50, c_diag_bg_samples_per_packet_w),
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TO_UVEC( 10, c_diag_bg_blocks_per_sync_w),
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TO_UVEC( 10, c_diag_bg_blocks_per_sync_w),
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TO_UVEC( 7, c_diag_bg_gapsize_w),
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TO_UVEC( 7, c_diag_bg_gapsize_w),
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TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
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TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
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TO_UVEC( 15, c_diag_bg_mem_high_adrs_w), -- fits any BG buffer that has address width >= 4
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TO_UVEC( 15, c_diag_bg_mem_high_adrs_w), -- fits any BG buffer that has address width >= 4
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TO_UVEC( 0, c_diag_bg_bsn_init_w));
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TO_UVEC( 0, c_diag_bg_bsn_init_w));
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TYPE t_diag_block_gen_arr IS ARRAY (INTEGER RANGE <>) OF t_diag_block_gen;
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TYPE t_diag_block_gen_arr IS ARRAY (INTEGER RANGE <>) OF t_diag_block_gen;
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-- Overloaded sel_a_b (from common_pkg) for t_diag_block_gen
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-- Overloaded sel_a_b (from common_pkg) for t_diag_block_gen
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FUNCTION sel_a_b(sel : BOOLEAN; a, b : t_diag_block_gen) RETURN t_diag_block_gen;
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FUNCTION sel_a_b(sel : BOOLEAN; a, b : t_diag_block_gen) RETURN t_diag_block_gen;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Data buffer
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-- Data buffer
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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CONSTANT c_diag_db_reg_nof_dat : NATURAL := 2;
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CONSTANT c_diag_db_reg_nof_dat : NATURAL := 2;
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CONSTANT c_diag_db_reg_adr_w : NATURAL := ceil_log2(c_diag_db_reg_nof_dat);
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CONSTANT c_diag_db_reg_adr_w : NATURAL := ceil_log2(c_diag_db_reg_nof_dat);
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CONSTANT c_diag_db_max_data_w : NATURAL := 32;
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CONSTANT c_diag_db_max_data_w : NATURAL := 32;
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TYPE t_diag_data_type_enum IS (
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TYPE t_diag_data_type_enum IS (
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e_data,
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e_data,
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e_complex, -- im & re
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e_complex, -- im & re
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e_real,
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e_real,
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e_imag
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e_imag
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);
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);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Data buffer dev
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-- Data buffer dev
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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CONSTANT c_diag_db_dev_reg_nof_dat : NATURAL := 8; -- Create headroom of 4 registers.
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CONSTANT c_diag_db_dev_reg_nof_dat : NATURAL := 8; -- Create headroom of 4 registers.
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CONSTANT c_diag_db_dev_reg_adr_w : NATURAL := ceil_log2(c_diag_db_dev_reg_nof_dat);
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CONSTANT c_diag_db_dev_reg_adr_w : NATURAL := ceil_log2(c_diag_db_dev_reg_nof_dat);
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|
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- CNTR / PSRG sequence test data
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-- CNTR / PSRG sequence test data
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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|
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CONSTANT c_diag_seq_tx_reg_nof_dat : NATURAL := 4;
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CONSTANT c_diag_seq_tx_reg_nof_dat : NATURAL := 4;
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CONSTANT c_diag_seq_tx_reg_adr_w : NATURAL := ceil_log2(c_diag_seq_tx_reg_nof_dat);
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CONSTANT c_diag_seq_tx_reg_adr_w : NATURAL := ceil_log2(c_diag_seq_tx_reg_nof_dat);
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CONSTANT c_diag_seq_rx_reg_nof_steps_wi : NATURAL := 4;
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CONSTANT c_diag_seq_rx_reg_nof_steps_wi : NATURAL := 4;
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CONSTANT c_diag_seq_rx_reg_nof_steps : NATURAL := 4;
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CONSTANT c_diag_seq_rx_reg_nof_steps : NATURAL := 4;
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CONSTANT c_diag_seq_rx_reg_nof_dat : NATURAL := c_diag_seq_rx_reg_nof_steps_wi + c_diag_seq_rx_reg_nof_steps;
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CONSTANT c_diag_seq_rx_reg_nof_dat : NATURAL := c_diag_seq_rx_reg_nof_steps_wi + c_diag_seq_rx_reg_nof_steps;
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CONSTANT c_diag_seq_rx_reg_adr_w : NATURAL := ceil_log2(c_diag_seq_rx_reg_nof_dat);
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CONSTANT c_diag_seq_rx_reg_adr_w : NATURAL := ceil_log2(c_diag_seq_rx_reg_nof_dat);
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|
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-- Record with all diag seq MM register fields
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-- Record with all diag seq MM register fields
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TYPE t_diag_seq_mm_reg IS RECORD
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TYPE t_diag_seq_mm_reg IS RECORD
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-- readback control
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-- readback control
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tx_init : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
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tx_init : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
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tx_mod : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
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tx_mod : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
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tx_ctrl : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
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tx_ctrl : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
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rx_ctrl : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
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rx_ctrl : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
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rx_steps : t_integer_arr(c_diag_seq_rx_reg_nof_steps-1 DOWNTO 0);
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rx_steps : t_integer_arr(c_diag_seq_rx_reg_nof_steps-1 DOWNTO 0);
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-- read only status
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-- read only status
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tx_cnt : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
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tx_cnt : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
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rx_cnt : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
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rx_cnt : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
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rx_stat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
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rx_stat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
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rx_sample : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
|
rx_sample : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
|
END RECORD;
|
END RECORD;
|
|
|
CONSTANT c_diag_seq_tx_reg_dis : NATURAL := 0;
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CONSTANT c_diag_seq_tx_reg_dis : NATURAL := 0;
|
CONSTANT c_diag_seq_tx_reg_en_psrg : NATURAL := 1;
|
CONSTANT c_diag_seq_tx_reg_en_psrg : NATURAL := 1;
|
CONSTANT c_diag_seq_tx_reg_en_cntr : NATURAL := 3;
|
CONSTANT c_diag_seq_tx_reg_en_cntr : NATURAL := 3;
|
|
|
TYPE t_diag_seq_mm_reg_arr IS ARRAY (INTEGER RANGE <>) OF t_diag_seq_mm_reg;
|
TYPE t_diag_seq_mm_reg_arr IS ARRAY (INTEGER RANGE <>) OF t_diag_seq_mm_reg;
|
|
|
END diag_pkg;
|
END diag_pkg;
|
|
|
PACKAGE BODY diag_pkg IS
|
PACKAGE BODY diag_pkg IS
|
|
|
FUNCTION sel_a_b(sel : BOOLEAN; a, b : t_diag_block_gen) RETURN t_diag_block_gen IS
|
FUNCTION sel_a_b(sel : BOOLEAN; a, b : t_diag_block_gen) RETURN t_diag_block_gen IS
|
BEGIN
|
BEGIN
|
IF sel = TRUE THEN
|
IF sel = TRUE THEN
|
RETURN a;
|
RETURN a;
|
ELSE
|
ELSE
|
RETURN b;
|
RETURN b;
|
END IF;
|
END IF;
|
END;
|
END;
|
|
|
END diag_pkg;
|
END diag_pkg;
|
|
|