--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--
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--
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-- Copyright 2020
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- You may obtain a copy of the License at
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--
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Purpose: Verify received continuous test sequence data.
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-- Purpose: Verify received continuous test sequence data.
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-- Description:
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-- Description:
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-- The diag_rx_seq can operate in one of two modes that depend on g_use_steps:
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-- The diag_rx_seq can operate in one of two modes that depend on g_use_steps:
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--
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--
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-- . g_use_steps = FALSE
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-- . g_use_steps = FALSE
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-- The test data can be PRSG or COUNTER dependent on diag_sel.
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-- The test data can be PRSG or COUNTER dependent on diag_sel.
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-- The Rx is enabled by diag_en. Typically the Tx should already be running,
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-- The Rx is enabled by diag_en. Typically the Tx should already be running,
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-- but it is also allowed to first enable the Rx.
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-- but it is also allowed to first enable the Rx.
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-- The Rx is always ready to accept data, therefore it has no in_ready output.
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-- The Rx is always ready to accept data, therefore it has no in_ready output.
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-- Inititally when diag_en is low then diag_res = -1, when diag_en is high
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-- Inititally when diag_en is low then diag_res = -1, when diag_en is high
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-- then diag_res becomes valid, indicated by diag_res_val, after two test
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-- then diag_res becomes valid, indicated by diag_res_val, after two test
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-- data words have been received. The diag_res verifies per input dat bit,
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-- data words have been received. The diag_res verifies per input dat bit,
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-- when an in_dat bit goes wrong then the corresponding bit in diag_res goes
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-- when an in_dat bit goes wrong then the corresponding bit in diag_res goes
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-- high and remains high until the Rx is restarted again. This is useful if
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-- high and remains high until the Rx is restarted again. This is useful if
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-- the test data bits go via separate physical lines (e.g. an LVDS bus).
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-- the test data bits go via separate physical lines (e.g. an LVDS bus).
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-- When the Rx is disabled then diag_res = -1. Typically the g_diag_res_w >
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-- When the Rx is disabled then diag_res = -1. Typically the g_diag_res_w >
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-- g_dat_w:
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-- g_dat_w:
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-- . diag_res(g_diag_res_w-1:g_dat_w) => NOT diag_res_val
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-- . diag_res(g_diag_res_w-1:g_dat_w) => NOT diag_res_val
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-- . diag_res( g_dat_w-1:0 ) => aggregated diff of in_dat during
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-- . diag_res( g_dat_w-1:0 ) => aggregated diff of in_dat during
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-- diag_en
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-- diag_en
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-- It is possible to use g_diag_res_w=g_dat_w, but then it is not possible to
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-- It is possible to use g_diag_res_w=g_dat_w, but then it is not possible to
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-- distinguish between whether the test has ran at all or whether all bits
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-- distinguish between whether the test has ran at all or whether all bits
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-- got errors.
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-- got errors.
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-- The diag_sample keeps the last valid in_dat value. When diag_en='0' it is
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-- The diag_sample keeps the last valid in_dat value. When diag_en='0' it is
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-- reset to 0. Reading diag_sample via MM gives an impression of the valid
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-- reset to 0. Reading diag_sample via MM gives an impression of the valid
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-- in_dat activity. The diag_sample_diff shows the difference of the last and
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-- in_dat activity. The diag_sample_diff shows the difference of the last and
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-- the previous in_dat value. The diag_sample_diff can be useful to determine
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-- the previous in_dat value. The diag_sample_diff can be useful to determine
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-- or debug the values that are needed for diag_steps_arr.
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-- or debug the values that are needed for diag_steps_arr.
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--
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--
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-- . g_use_steps = TRUE
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-- . g_use_steps = TRUE
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-- The test data is fixed to COUNTER and diag_sel is ignored. The rx_seq can
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-- The test data is fixed to COUNTER and diag_sel is ignored. The rx_seq can
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-- verify counter data that increments in steps that are specified via
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-- verify counter data that increments in steps that are specified via
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-- diag_steps_arr[3:0]. Up to g_nof_steps <= c_diag_seq_rx_reg_nof_steps = 4
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-- diag_steps_arr[3:0]. Up to g_nof_steps <= c_diag_seq_rx_reg_nof_steps = 4
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-- step sizes are supported. If all steps are set to 1 then there is no
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-- step sizes are supported. If all steps are set to 1 then there is no
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-- difference compared using the COUNTER in g_use_steps = FALSE. Constant
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-- difference compared using the COUNTER in g_use_steps = FALSE. Constant
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-- value data can be verified by setting alls step to 0. Usinf different
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-- value data can be verified by setting alls step to 0. Usinf different
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-- steps is useful when the data is generated in linear incrementing order,
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-- steps is useful when the data is generated in linear incrementing order,
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-- but received in a different order. Eg. like after a transpose operation
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-- but received in a different order. Eg. like after a transpose operation
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-- where blocks of data are written in row and and read in colums:
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-- where blocks of data are written in row and and read in colums:
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--
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--
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-- tx: 0 1 2 3 4 5 6 7 8 9 10 11
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-- tx: 0 1 2 3 4 5 6 7 8 9 10 11
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-- transpose: 0 1 4 5 8 9 2 3 6 7 10 11
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-- transpose: 0 1 4 5 8 9 2 3 6 7 10 11
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-- rx steps: +1 +1 +1 +1 +1 +1
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-- rx steps: +1 +1 +1 +1 +1 +1
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-- -11 +3 +3 -7 +3 +3
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-- -11 +3 +3 -7 +3 +3
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--
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--
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-- The step size value range is set by the 32 bit range of the VHDL integer.
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-- The step size value range is set by the 32 bit range of the VHDL integer.
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-- Therefore typically g_dat_w should be <= 32 b. For a transpose that
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-- Therefore typically g_dat_w should be <= 32 b. For a transpose that
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-- contains more than 2**32 data words this means that the COUNTER data
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-- contains more than 2**32 data words this means that the COUNTER data
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-- wraps within the transpose. This is acceptable, because it use g_dat_w
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-- wraps within the transpose. This is acceptable, because it use g_dat_w
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-- <= 32 then still provides sufficient coverage to detect all errors.
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-- <= 32 then still provides sufficient coverage to detect all errors.
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--
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--
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-- Data errors that match a step size cannot be detected. However if such
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-- Data errors that match a step size cannot be detected. However if such
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-- an error occurs then typically the next increment will cause a mismatch.
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-- an error occurs then typically the next increment will cause a mismatch.
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--
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--
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-- Remarks:
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-- Remarks:
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-- . The feature of being able to detect errors per bit as with g_use_steps=
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-- . The feature of being able to detect errors per bit as with g_use_steps=
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-- FALSE is not supported when g_use_steps=TRUE. Therefore the
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-- FALSE is not supported when g_use_steps=TRUE. Therefore the
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-- diag_res[g_dat_w-1:0] = -1 (all '1') when a difference occurs that is no
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-- diag_res[g_dat_w-1:0] = -1 (all '1') when a difference occurs that is no
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-- in diag_steps_arr.
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-- in diag_steps_arr.
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-- . The common_lfsr_nxt_seq() that is used when g_use_steps=FALSE uses the
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-- . The common_lfsr_nxt_seq() that is used when g_use_steps=FALSE uses the
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-- in_dat_reg as initialization value for the reference sequence. All
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-- in_dat_reg as initialization value for the reference sequence. All
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-- subsequent values are derived when in_val_reg='1'. This is possible
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-- subsequent values are derived when in_val_reg='1'. This is possible
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-- because given a first value all subsequent values for PSRG or COUNTER
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-- because given a first value all subsequent values for PSRG or COUNTER
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-- with +1 increment are known. For g_use_steps=TRUE the sequence is not
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-- with +1 increment are known. For g_use_steps=TRUE the sequence is not
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-- known in advance because different increment steps can occur at
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-- known in advance because different increment steps can occur at
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-- arbitrary instants. Therefore then the in_dat_reg input is also used
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-- arbitrary instants. Therefore then the in_dat_reg input is also used
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-- during the sequence, to determine all g_nof_steps next values are correct
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-- during the sequence, to determine all g_nof_steps next values are correct
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-- in case they occur.
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-- in case they occur.
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LIBRARY IEEE, common_pkg_lib, common_components_lib, common_counter_lib;
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LIBRARY IEEE, common_pkg_lib, common_components_lib, astron_counter_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_lfsr_sequences_pkg.ALL;
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USE common_pkg_lib.common_lfsr_sequences_pkg.ALL;
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USE work.diag_pkg.ALL;
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USE work.diag_pkg.ALL;
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ENTITY diag_rx_seq IS
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ENTITY diag_rx_seq IS
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GENERIC (
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GENERIC (
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g_input_reg : BOOLEAN := FALSE; -- Use unregistered input to save logic, use registered input to ease achieving timing constrains.
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g_input_reg : BOOLEAN := FALSE; -- Use unregistered input to save logic, use registered input to ease achieving timing constrains.
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g_use_steps : BOOLEAN := FALSE;
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g_use_steps : BOOLEAN := FALSE;
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g_nof_steps : NATURAL := c_diag_seq_rx_reg_nof_steps;
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g_nof_steps : NATURAL := c_diag_seq_rx_reg_nof_steps;
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g_sel : STD_LOGIC := '1'; -- '0' = PRSG, '1' = COUNTER
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g_sel : STD_LOGIC := '1'; -- '0' = PRSG, '1' = COUNTER
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g_cnt_incr : INTEGER := 1;
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g_cnt_incr : INTEGER := 1;
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g_cnt_w : NATURAL := c_word_w;
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g_cnt_w : NATURAL := c_word_w;
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g_dat_w : NATURAL := 12;
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g_dat_w : NATURAL := 12;
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g_diag_res_w : NATURAL := 16
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g_diag_res_w : NATURAL := 16
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);
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);
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PORT (
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PORT (
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rst : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clken : IN STD_LOGIC := '1';
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clken : IN STD_LOGIC := '1';
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-- Static control input (connect via MM or leave open to use default)
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-- Static control input (connect via MM or leave open to use default)
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diag_en : IN STD_LOGIC; -- '0' = init and disable, '1' = enable
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diag_en : IN STD_LOGIC; -- '0' = init and disable, '1' = enable
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diag_sel : IN STD_LOGIC := g_sel;
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diag_sel : IN STD_LOGIC := g_sel;
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diag_steps_arr : t_integer_arr(g_nof_steps-1 DOWNTO 0) := (OTHERS=>1);
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diag_steps_arr : t_integer_arr(g_nof_steps-1 DOWNTO 0) := (OTHERS=>1);
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diag_res : OUT STD_LOGIC_VECTOR(g_diag_res_w-1 DOWNTO 0); -- diag_res valid indication bits & aggregate diff of in_dat during diag_en
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diag_res : OUT STD_LOGIC_VECTOR(g_diag_res_w-1 DOWNTO 0); -- diag_res valid indication bits & aggregate diff of in_dat during diag_en
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diag_res_val : OUT STD_LOGIC;
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diag_res_val : OUT STD_LOGIC;
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diag_sample : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0); -- monitor last valid in_dat
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diag_sample : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0); -- monitor last valid in_dat
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diag_sample_diff : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0); -- monitor difference between last valid in_dat and previous valid in_dat
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diag_sample_diff : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0); -- monitor difference between last valid in_dat and previous valid in_dat
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diag_sample_val : OUT STD_LOGIC;
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diag_sample_val : OUT STD_LOGIC;
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-- ST input
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-- ST input
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in_cnt : OUT STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0); -- count valid input test sequence data
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in_cnt : OUT STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0); -- count valid input test sequence data
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in_dat : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0); -- input test sequence data
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in_dat : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0); -- input test sequence data
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in_val : IN STD_LOGIC -- gaps are allowed, however diag_res requires at least 2 valid in_dat to report a valid result
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in_val : IN STD_LOGIC -- gaps are allowed, however diag_res requires at least 2 valid in_dat to report a valid result
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);
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);
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END diag_rx_seq;
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END diag_rx_seq;
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ARCHITECTURE rtl OF diag_rx_seq IS
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ARCHITECTURE rtl OF diag_rx_seq IS
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CONSTANT c_lfsr_nr : NATURAL := g_dat_w - c_common_lfsr_first;
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CONSTANT c_lfsr_nr : NATURAL := g_dat_w - c_common_lfsr_first;
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CONSTANT c_diag_res_latency : NATURAL := 3;
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CONSTANT c_diag_res_latency : NATURAL := 3;
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-- Used special value to signal invalid diag_res, unique assuming g_diag_res_w > g_dat_w
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-- Used special value to signal invalid diag_res, unique assuming g_diag_res_w > g_dat_w
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CONSTANT c_diag_res_invalid : STD_LOGIC_VECTOR(diag_res'RANGE) := (OTHERS=>'1');
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CONSTANT c_diag_res_invalid : STD_LOGIC_VECTOR(diag_res'RANGE) := (OTHERS=>'1');
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SIGNAL in_val_reg : STD_LOGIC;
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SIGNAL in_val_reg : STD_LOGIC;
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SIGNAL in_dat_reg : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL in_dat_reg : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL in_dat_dly1 : STD_LOGIC_VECTOR(in_dat'RANGE); -- latency common_lfsr_nxt_seq
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SIGNAL in_dat_dly1 : STD_LOGIC_VECTOR(in_dat'RANGE); -- latency common_lfsr_nxt_seq
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SIGNAL in_dat_dly2 : STD_LOGIC_VECTOR(in_dat'RANGE); -- latency ref_dat
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SIGNAL in_dat_dly2 : STD_LOGIC_VECTOR(in_dat'RANGE); -- latency ref_dat
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SIGNAL in_val_dly1 : STD_LOGIC; -- latency common_lfsr_nxt_seq
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SIGNAL in_val_dly1 : STD_LOGIC; -- latency common_lfsr_nxt_seq
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SIGNAL in_val_dly2 : STD_LOGIC; -- latency ref_dat
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SIGNAL in_val_dly2 : STD_LOGIC; -- latency ref_dat
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SIGNAL prsg : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL prsg : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL nxt_prsg : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL nxt_prsg : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL cntr : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL cntr : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL nxt_cntr : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL nxt_cntr : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL diag_dis : STD_LOGIC;
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SIGNAL diag_dis : STD_LOGIC;
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SIGNAL ref_en : STD_LOGIC;
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SIGNAL ref_en : STD_LOGIC;
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SIGNAL diff_dis : STD_LOGIC;
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SIGNAL diff_dis : STD_LOGIC;
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SIGNAL diag_res_en : STD_LOGIC;
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SIGNAL diag_res_en : STD_LOGIC;
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SIGNAL nxt_diag_res_en : STD_LOGIC;
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SIGNAL nxt_diag_res_en : STD_LOGIC;
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SIGNAL nxt_diag_res_val: STD_LOGIC;
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SIGNAL nxt_diag_res_val: STD_LOGIC;
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SIGNAL in_val_1 : STD_LOGIC;
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SIGNAL in_val_1 : STD_LOGIC;
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SIGNAL in_val_act : STD_LOGIC;
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SIGNAL in_val_act : STD_LOGIC;
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SIGNAL in_val_2 : STD_LOGIC;
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SIGNAL in_val_2 : STD_LOGIC;
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SIGNAL in_val_2_dly : STD_LOGIC_VECTOR(0 TO c_diag_res_latency-1) := (OTHERS=>'0');
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SIGNAL in_val_2_dly : STD_LOGIC_VECTOR(0 TO c_diag_res_latency-1) := (OTHERS=>'0');
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SIGNAL in_val_2_act : STD_LOGIC;
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SIGNAL in_val_2_act : STD_LOGIC;
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SIGNAL ref_dat : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL ref_dat : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL nxt_ref_dat : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL nxt_ref_dat : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL diff_dat : STD_LOGIC_VECTOR(in_dat'RANGE) := (OTHERS=>'0');
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SIGNAL diff_dat : STD_LOGIC_VECTOR(in_dat'RANGE) := (OTHERS=>'0');
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SIGNAL nxt_diff_dat : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL nxt_diff_dat : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL diff_res : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL diff_res : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL nxt_diag_res : STD_LOGIC_VECTOR(diag_res'RANGE);
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SIGNAL nxt_diag_res : STD_LOGIC_VECTOR(diag_res'RANGE);
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SIGNAL diag_res_int : STD_LOGIC_VECTOR(diag_res'RANGE) := c_diag_res_invalid;
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SIGNAL diag_res_int : STD_LOGIC_VECTOR(diag_res'RANGE) := c_diag_res_invalid;
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SIGNAL i_diag_sample : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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SIGNAL i_diag_sample : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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SIGNAL nxt_diag_sample : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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SIGNAL nxt_diag_sample : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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SIGNAL i_diag_sample_diff : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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SIGNAL i_diag_sample_diff : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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SIGNAL nxt_diag_sample_diff : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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SIGNAL nxt_diag_sample_diff : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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SIGNAL nxt_diag_sample_val : STD_LOGIC;
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SIGNAL nxt_diag_sample_val : STD_LOGIC;
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TYPE t_dat_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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TYPE t_dat_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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SIGNAL ref_dat_arr : t_dat_arr(g_nof_steps-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
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SIGNAL ref_dat_arr : t_dat_arr(g_nof_steps-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
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SIGNAL nxt_ref_dat_arr : t_dat_arr(g_nof_steps-1 DOWNTO 0);
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SIGNAL nxt_ref_dat_arr : t_dat_arr(g_nof_steps-1 DOWNTO 0);
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SIGNAL diff_arr : STD_LOGIC_VECTOR(g_nof_steps-1 DOWNTO 0) := (OTHERS=>'0');
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SIGNAL diff_arr : STD_LOGIC_VECTOR(g_nof_steps-1 DOWNTO 0) := (OTHERS=>'0');
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SIGNAL nxt_diff_arr : STD_LOGIC_VECTOR(g_nof_steps-1 DOWNTO 0);
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SIGNAL nxt_diff_arr : STD_LOGIC_VECTOR(g_nof_steps-1 DOWNTO 0);
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SIGNAL diff_detect : STD_LOGIC := '0';
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SIGNAL diff_detect : STD_LOGIC := '0';
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SIGNAL nxt_diff_detect : STD_LOGIC;
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SIGNAL nxt_diff_detect : STD_LOGIC;
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SIGNAL diff_hold : STD_LOGIC;
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SIGNAL diff_hold : STD_LOGIC;
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BEGIN
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BEGIN
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diag_dis <= NOT diag_en;
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diag_dis <= NOT diag_en;
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diag_sample <= i_diag_sample;
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diag_sample <= i_diag_sample;
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diag_sample_diff <= i_diag_sample_diff;
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diag_sample_diff <= i_diag_sample_diff;
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gen_input_reg : IF g_input_reg=TRUE GENERATE
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gen_input_reg : IF g_input_reg=TRUE GENERATE
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p_reg : PROCESS (clk)
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p_reg : PROCESS (clk)
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BEGIN
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BEGIN
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IF rising_edge(clk) THEN
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IF rising_edge(clk) THEN
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IF clken='1' THEN
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IF clken='1' THEN
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in_val_reg <= in_val;
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in_val_reg <= in_val;
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in_dat_reg <= in_dat;
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in_dat_reg <= in_dat;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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END GENERATE;
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END GENERATE;
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no_input_reg : IF g_input_reg=FALSE GENERATE
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no_input_reg : IF g_input_reg=FALSE GENERATE
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in_val_reg <= in_val;
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in_val_reg <= in_val;
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in_dat_reg <= in_dat;
|
in_dat_reg <= in_dat;
|
END GENERATE;
|
END GENERATE;
|
|
|
-- Use initialisation to set initial diag_res to invalid
|
-- Use initialisation to set initial diag_res to invalid
|
diag_res <= diag_res_int; -- use initialisation of internal signal diag_res_int rather than initialisation of entity output diag_res
|
diag_res <= diag_res_int; -- use initialisation of internal signal diag_res_int rather than initialisation of entity output diag_res
|
|
|
-- -- Use rst to set initial diag_res to invalid
|
-- -- Use rst to set initial diag_res to invalid
|
-- p_rst_clk : PROCESS (rst, clk)
|
-- p_rst_clk : PROCESS (rst, clk)
|
-- BEGIN
|
-- BEGIN
|
-- IF rst='1' THEN
|
-- IF rst='1' THEN
|
-- diag_res <= c_diag_res_invalid;
|
-- diag_res <= c_diag_res_invalid;
|
-- ELSIF rising_edge(clk) THEN
|
-- ELSIF rising_edge(clk) THEN
|
-- IF clken='1' THEN
|
-- IF clken='1' THEN
|
-- -- Internal.
|
-- -- Internal.
|
-- diag_res <= nxt_diag_res;
|
-- diag_res <= nxt_diag_res;
|
-- -- Outputs.
|
-- -- Outputs.
|
-- END IF;
|
-- END IF;
|
-- END IF;
|
-- END IF;
|
-- END PROCESS;
|
-- END PROCESS;
|
|
|
p_clk : PROCESS (clk)
|
p_clk : PROCESS (clk)
|
BEGIN
|
BEGIN
|
IF rising_edge(clk) THEN
|
IF rising_edge(clk) THEN
|
IF clken='1' THEN
|
IF clken='1' THEN
|
-- Inputs.
|
-- Inputs.
|
in_dat_dly1 <= in_dat_reg;
|
in_dat_dly1 <= in_dat_reg;
|
in_dat_dly2 <= in_dat_dly1;
|
in_dat_dly2 <= in_dat_dly1;
|
in_val_dly1 <= in_val_reg;
|
in_val_dly1 <= in_val_reg;
|
in_val_dly2 <= in_val_dly1;
|
in_val_dly2 <= in_val_dly1;
|
-- Internal.
|
-- Internal.
|
in_val_2_dly <= in_val_2 & in_val_2_dly(0 TO c_diag_res_latency-2);
|
in_val_2_dly <= in_val_2 & in_val_2_dly(0 TO c_diag_res_latency-2);
|
diag_res_int <= nxt_diag_res;
|
diag_res_int <= nxt_diag_res;
|
diag_res_en <= nxt_diag_res_en;
|
diag_res_en <= nxt_diag_res_en;
|
diag_res_val <= nxt_diag_res_val;
|
diag_res_val <= nxt_diag_res_val;
|
-- . g_use_steps=FALSE
|
-- . g_use_steps=FALSE
|
prsg <= nxt_prsg;
|
prsg <= nxt_prsg;
|
cntr <= nxt_cntr;
|
cntr <= nxt_cntr;
|
ref_dat <= nxt_ref_dat;
|
ref_dat <= nxt_ref_dat;
|
diff_dat <= nxt_diff_dat;
|
diff_dat <= nxt_diff_dat;
|
-- . g_use_steps=TRUE
|
-- . g_use_steps=TRUE
|
ref_dat_arr <= nxt_ref_dat_arr;
|
ref_dat_arr <= nxt_ref_dat_arr;
|
diff_arr <= nxt_diff_arr;
|
diff_arr <= nxt_diff_arr;
|
diff_detect <= nxt_diff_detect;
|
diff_detect <= nxt_diff_detect;
|
-- Outputs.
|
-- Outputs.
|
i_diag_sample <= nxt_diag_sample;
|
i_diag_sample <= nxt_diag_sample;
|
i_diag_sample_diff <= nxt_diag_sample_diff;
|
i_diag_sample_diff <= nxt_diag_sample_diff;
|
diag_sample_val <= nxt_diag_sample_val;
|
diag_sample_val <= nxt_diag_sample_val;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- Keep last valid in_dat value for MM monitoring
|
-- Keep last valid in_dat value for MM monitoring
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
nxt_diag_sample <= (OTHERS=>'0') WHEN diag_en='0' ELSE in_dat_reg WHEN in_val_reg='1' ELSE i_diag_sample;
|
nxt_diag_sample <= (OTHERS=>'0') WHEN diag_en='0' ELSE in_dat_reg WHEN in_val_reg='1' ELSE i_diag_sample;
|
nxt_diag_sample_diff <= (OTHERS=>'0') WHEN diag_en='0' ELSE SUB_UVEC(in_dat_reg, i_diag_sample) WHEN in_val_reg='1' ELSE i_diag_sample_diff;
|
nxt_diag_sample_diff <= (OTHERS=>'0') WHEN diag_en='0' ELSE SUB_UVEC(in_dat_reg, i_diag_sample) WHEN in_val_reg='1' ELSE i_diag_sample_diff;
|
nxt_diag_sample_val <= '0' WHEN diag_en='0' ELSE in_val_reg;
|
nxt_diag_sample_val <= '0' WHEN diag_en='0' ELSE in_val_reg;
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- Detect that there has been valid input data for at least two clock cycles
|
-- Detect that there has been valid input data for at least two clock cycles
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
|
|
u_in_val_1 : ENTITY common_components_lib.common_switch
|
u_in_val_1 : ENTITY common_components_lib.common_switch
|
PORT MAP(
|
PORT MAP(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
switch_high => in_val_reg,
|
switch_high => in_val_reg,
|
switch_low => diag_dis,
|
switch_low => diag_dis,
|
out_level => in_val_1 -- first in_val has been detected, but this one was used as seed for common_lfsr_nxt_seq
|
out_level => in_val_1 -- first in_val has been detected, but this one was used as seed for common_lfsr_nxt_seq
|
);
|
);
|
|
|
in_val_act <= in_val_1 AND in_val_reg; -- Signal the second valid in_dat after diag_en='1'
|
in_val_act <= in_val_1 AND in_val_reg; -- Signal the second valid in_dat after diag_en='1'
|
|
|
u_in_val_2 : ENTITY common_components_lib.common_switch
|
u_in_val_2 : ENTITY common_components_lib.common_switch
|
PORT MAP(
|
PORT MAP(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
switch_high => in_val_act,
|
switch_high => in_val_act,
|
switch_low => diag_dis,
|
switch_low => diag_dis,
|
out_level => in_val_2 -- second in_val has been detected, representing a true next sequence value
|
out_level => in_val_2 -- second in_val has been detected, representing a true next sequence value
|
);
|
);
|
|
|
-- Use in_val_2_act instead of in_val_2 to have stable start in case diag_dis takes just a pulse and in_val is continue high
|
-- Use in_val_2_act instead of in_val_2 to have stable start in case diag_dis takes just a pulse and in_val is continue high
|
in_val_2_act <= vector_and(in_val_2 & in_val_2_dly);
|
in_val_2_act <= vector_and(in_val_2 & in_val_2_dly);
|
|
|
-- Use the first valid in_dat after diag_en='1' to initialize the reference data sequence
|
-- Use the first valid in_dat after diag_en='1' to initialize the reference data sequence
|
ref_en <= in_val_1;
|
ref_en <= in_val_1;
|
|
|
-- Use the detection of second valid in_dat after diag_en='1' to start detection of differences
|
-- Use the detection of second valid in_dat after diag_en='1' to start detection of differences
|
diff_dis <= NOT in_val_2_act;
|
diff_dis <= NOT in_val_2_act;
|
|
|
no_steps : IF g_use_steps=FALSE GENERATE
|
no_steps : IF g_use_steps=FALSE GENERATE
|
-- Determine next reference dat based on current input dat
|
-- Determine next reference dat based on current input dat
|
common_lfsr_nxt_seq(c_lfsr_nr, -- IN
|
common_lfsr_nxt_seq(c_lfsr_nr, -- IN
|
g_cnt_incr, -- IN
|
g_cnt_incr, -- IN
|
ref_en, -- IN
|
ref_en, -- IN
|
in_val_reg, -- IN, use in_val_reg to allow gaps in the input data valid stream
|
in_val_reg, -- IN, use in_val_reg to allow gaps in the input data valid stream
|
in_dat_reg, -- IN, used only to init nxt_prsg and nxt_cntr when ref_en='0'
|
in_dat_reg, -- IN, used only to init nxt_prsg and nxt_cntr when ref_en='0'
|
prsg, -- IN
|
prsg, -- IN
|
cntr, -- IN
|
cntr, -- IN
|
nxt_prsg, -- OUT
|
nxt_prsg, -- OUT
|
nxt_cntr); -- OUT
|
nxt_cntr); -- OUT
|
|
|
nxt_ref_dat <= prsg WHEN diag_sel='0' ELSE cntr;
|
nxt_ref_dat <= prsg WHEN diag_sel='0' ELSE cntr;
|
|
|
-- Detect difference per bit. The ref_dat has latency 2 compared to the in_dat, because of the register stage in psrg/cntr and the register stage in ref_dat.
|
-- Detect difference per bit. The ref_dat has latency 2 compared to the in_dat, because of the register stage in psrg/cntr and the register stage in ref_dat.
|
p_diff_dat : PROCESS (diff_dat, ref_dat, in_val_dly2, in_dat_dly2)
|
p_diff_dat : PROCESS (diff_dat, ref_dat, in_val_dly2, in_dat_dly2)
|
BEGIN
|
BEGIN
|
nxt_diff_dat <= diff_dat;
|
nxt_diff_dat <= diff_dat;
|
IF in_val_dly2='1' THEN
|
IF in_val_dly2='1' THEN
|
FOR I IN in_dat'RANGE LOOP
|
FOR I IN in_dat'RANGE LOOP
|
nxt_diff_dat(I) <= ref_dat(I) XOR in_dat_dly2(I);
|
nxt_diff_dat(I) <= ref_dat(I) XOR in_dat_dly2(I);
|
END LOOP;
|
END LOOP;
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
gen_verify_dat : FOR I IN in_dat'RANGE GENERATE
|
gen_verify_dat : FOR I IN in_dat'RANGE GENERATE
|
-- Detect and report undefined diff input 'X', which in simulation leaves diff_res at OK, because switch_high only acts on '1'
|
-- Detect and report undefined diff input 'X', which in simulation leaves diff_res at OK, because switch_high only acts on '1'
|
p_sim_only : PROCESS(clk)
|
p_sim_only : PROCESS(clk)
|
BEGIN
|
BEGIN
|
IF rising_edge(clk) THEN
|
IF rising_edge(clk) THEN
|
IF diff_dat(I)/='0' AND diff_dat(I)/='1' THEN
|
IF diff_dat(I)/='0' AND diff_dat(I)/='1' THEN
|
REPORT "diag_rx_seq : undefined input" SEVERITY FAILURE;
|
REPORT "diag_rx_seq : undefined input" SEVERITY FAILURE;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
-- Hold any difference on the in_dat bus lines
|
-- Hold any difference on the in_dat bus lines
|
u_dat : ENTITY common_components_lib.common_switch
|
u_dat : ENTITY common_components_lib.common_switch
|
PORT MAP(
|
PORT MAP(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
switch_high => diff_dat(I),
|
switch_high => diff_dat(I),
|
switch_low => diff_dis,
|
switch_low => diff_dis,
|
out_level => diff_res(I)
|
out_level => diff_res(I)
|
);
|
);
|
END GENERATE;
|
END GENERATE;
|
END GENERATE;
|
END GENERATE;
|
|
|
use_steps : IF g_use_steps=TRUE GENERATE
|
use_steps : IF g_use_steps=TRUE GENERATE
|
-- Determine next reference data for all steps increments of current input dat
|
-- Determine next reference data for all steps increments of current input dat
|
p_ref_dat_arr : PROCESS(in_dat_reg, in_val_reg, ref_dat_arr)
|
p_ref_dat_arr : PROCESS(in_dat_reg, in_val_reg, ref_dat_arr)
|
BEGIN
|
BEGIN
|
nxt_ref_dat_arr <= ref_dat_arr;
|
nxt_ref_dat_arr <= ref_dat_arr;
|
IF in_val_reg='1' THEN
|
IF in_val_reg='1' THEN
|
FOR I IN g_nof_steps-1 DOWNTO 0 LOOP
|
FOR I IN g_nof_steps-1 DOWNTO 0 LOOP
|
nxt_ref_dat_arr(I) <= INCR_UVEC(in_dat_reg, diag_steps_arr(I));
|
nxt_ref_dat_arr(I) <= INCR_UVEC(in_dat_reg, diag_steps_arr(I));
|
END LOOP;
|
END LOOP;
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
-- Detect difference for each allowed reference data.
|
-- Detect difference for each allowed reference data.
|
p_diff_arr : PROCESS(diff_arr, in_val_reg, in_dat_reg, ref_dat_arr)
|
p_diff_arr : PROCESS(diff_arr, in_val_reg, in_dat_reg, ref_dat_arr)
|
BEGIN
|
BEGIN
|
nxt_diff_arr <= diff_arr;
|
nxt_diff_arr <= diff_arr;
|
IF in_val_reg='1' THEN
|
IF in_val_reg='1' THEN
|
nxt_diff_arr <= (OTHERS=>'1');
|
nxt_diff_arr <= (OTHERS=>'1');
|
FOR I IN g_nof_steps-1 DOWNTO 0 LOOP
|
FOR I IN g_nof_steps-1 DOWNTO 0 LOOP
|
IF UNSIGNED(ref_dat_arr(I))=UNSIGNED(in_dat_reg) THEN
|
IF UNSIGNED(ref_dat_arr(I))=UNSIGNED(in_dat_reg) THEN
|
nxt_diff_arr(I) <= '0';
|
nxt_diff_arr(I) <= '0';
|
END IF;
|
END IF;
|
END LOOP;
|
END LOOP;
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
-- detect diff when none of the step counter value matches
|
-- detect diff when none of the step counter value matches
|
p_diff_detect : PROCESS(diff_detect, diff_arr, in_val_dly1)
|
p_diff_detect : PROCESS(diff_detect, diff_arr, in_val_dly1)
|
BEGIN
|
BEGIN
|
nxt_diff_detect <= diff_detect;
|
nxt_diff_detect <= diff_detect;
|
IF in_val_dly1='1' THEN
|
IF in_val_dly1='1' THEN
|
nxt_diff_detect <= '0';
|
nxt_diff_detect <= '0';
|
IF vector_and(diff_arr)='1' THEN
|
IF vector_and(diff_arr)='1' THEN
|
nxt_diff_detect <= '1';
|
nxt_diff_detect <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
-- hold detected diff detect
|
-- hold detected diff detect
|
u_dat : ENTITY common_components_lib.common_switch
|
u_dat : ENTITY common_components_lib.common_switch
|
PORT MAP(
|
PORT MAP(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
switch_high => diff_detect,
|
switch_high => diff_detect,
|
switch_low => diff_dis,
|
switch_low => diff_dis,
|
out_level => diff_hold
|
out_level => diff_hold
|
);
|
);
|
|
|
diff_res <= (OTHERS=> diff_hold); -- convert diff_hold to diff_res slv format as used for g_use_steps=FALSE
|
diff_res <= (OTHERS=> diff_hold); -- convert diff_hold to diff_res slv format as used for g_use_steps=FALSE
|
END GENERATE;
|
END GENERATE;
|
|
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- Report valid diag_res
|
-- Report valid diag_res
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
|
|
nxt_diag_res_en <= diag_en AND in_val_2_act;
|
nxt_diag_res_en <= diag_en AND in_val_2_act;
|
nxt_diag_res_val <= diag_res_en;
|
nxt_diag_res_val <= diag_res_en;
|
|
|
p_diag_res : PROCESS (diff_res, diag_res_en)
|
p_diag_res : PROCESS (diff_res, diag_res_en)
|
BEGIN
|
BEGIN
|
nxt_diag_res <= c_diag_res_invalid;
|
nxt_diag_res <= c_diag_res_invalid;
|
IF diag_res_en='1' THEN
|
IF diag_res_en='1' THEN
|
-- The test runs AND there have been valid input samples to verify
|
-- The test runs AND there have been valid input samples to verify
|
nxt_diag_res <= (OTHERS=>'0'); -- MSBits of valid diag_res are 0
|
nxt_diag_res <= (OTHERS=>'0'); -- MSBits of valid diag_res are 0
|
nxt_diag_res(diff_res'RANGE) <= diff_res; -- diff_res of dat[]
|
nxt_diag_res(diff_res'RANGE) <= diff_res; -- diff_res of dat[]
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- Count number of valid input data
|
-- Count number of valid input data
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
u_common_counter : ENTITY common_counter_lib.common_counter
|
u_common_counter : ENTITY astron_counter_lib.common_counter
|
GENERIC MAP (
|
GENERIC MAP (
|
g_latency => 1, -- default 1 for registered count output, use 0 for immediate combinatorial count output
|
g_latency => 1, -- default 1 for registered count output, use 0 for immediate combinatorial count output
|
g_width => g_cnt_w
|
g_width => g_cnt_w
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
rst => rst,
|
rst => rst,
|
clk => clk,
|
clk => clk,
|
clken => clken,
|
clken => clken,
|
cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
|
cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
|
cnt_en => in_val,
|
cnt_en => in_val,
|
count => in_cnt
|
count => in_cnt
|
);
|
);
|
END rtl;
|
END rtl;
|
|
|