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--
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--
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-- Copyright 2020
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- You may obtain a copy of the License at
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--
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib, common_counter_lib;
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LIBRARY IEEE, common_pkg_lib, astron_counter_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_lfsr_sequences_pkg.ALL;
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USE common_pkg_lib.common_lfsr_sequences_pkg.ALL;
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-- Purpose: Transmit continuous PRSG or COUNTER test sequence data.
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-- Purpose: Transmit continuous PRSG or COUNTER test sequence data.
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-- Description:
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-- Description:
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-- The Tx test data can sequence data or constant value data dependent on
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-- The Tx test data can sequence data or constant value data dependent on
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-- diag_dc.
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-- diag_dc.
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-- The Tx test sequence data can be PRSG or COUNTER dependent on diag_sel.
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-- The Tx test sequence data can be PRSG or COUNTER dependent on diag_sel.
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-- The Tx is enabled by diag_en. When the Tx is disabled then the sequence
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-- The Tx is enabled by diag_en. When the Tx is disabled then the sequence
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-- data gets initialised with diag_init.
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-- data gets initialised with diag_init.
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-- The out_ready acts as a data request. When the generator is enabled then
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-- The out_ready acts as a data request. When the generator is enabled then
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-- output is valid for every active out_ready, to support streaming flow
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-- output is valid for every active out_ready, to support streaming flow
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-- control. With g_latency=1 the out_val is active one cycle after diag_req,
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-- control. With g_latency=1 the out_val is active one cycle after diag_req,
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-- by using g_latency=0 outval is active in the same cycle as diag_req.
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-- by using g_latency=0 outval is active in the same cycle as diag_req.
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-- Use diag_mod=0 for default binary wrap at 2**g_dat_w. For diag_rx_seq
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-- Use diag_mod=0 for default binary wrap at 2**g_dat_w. For diag_rx_seq
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-- choose diag_step = 2**g_seq_dat_w - diag_mod + g_cnt_incr to verify ok.
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-- choose diag_step = 2**g_seq_dat_w - diag_mod + g_cnt_incr to verify ok.
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ENTITY diag_tx_seq IS
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ENTITY diag_tx_seq IS
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GENERIC (
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GENERIC (
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g_latency : NATURAL := 1; -- default 1 for registered out_cnt/dat/val output, use 0 for immediate combinatorial out_cnt/dat/val output
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g_latency : NATURAL := 1; -- default 1 for registered out_cnt/dat/val output, use 0 for immediate combinatorial out_cnt/dat/val output
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g_sel : STD_LOGIC := '1'; -- '0' = PRSG, '1' = COUNTER
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g_sel : STD_LOGIC := '1'; -- '0' = PRSG, '1' = COUNTER
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g_init : NATURAL := 0; -- init value for out_dat when diag_en = '0'
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g_init : NATURAL := 0; -- init value for out_dat when diag_en = '0'
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g_cnt_incr : INTEGER := 1;
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g_cnt_incr : INTEGER := 1;
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g_cnt_w : NATURAL := c_word_w;
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g_cnt_w : NATURAL := c_word_w;
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g_dat_w : NATURAL -- >= 1, test data width
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g_dat_w : NATURAL -- >= 1, test data width
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);
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);
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PORT (
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PORT (
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rst : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clken : IN STD_LOGIC := '1';
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clken : IN STD_LOGIC := '1';
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-- Static control input (connect via MM or leave open to use default)
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-- Static control input (connect via MM or leave open to use default)
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diag_en : IN STD_LOGIC; -- '0' = init and disable output sequence, '1' = enable output sequence
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diag_en : IN STD_LOGIC; -- '0' = init and disable output sequence, '1' = enable output sequence
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diag_sel : IN STD_LOGIC := g_sel; -- '0' = PRSG sequence data, '1' = COUNTER sequence data
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diag_sel : IN STD_LOGIC := g_sel; -- '0' = PRSG sequence data, '1' = COUNTER sequence data
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diag_dc : IN STD_LOGIC := '0'; -- '0' = output diag_sel sequence data, '1' = output constant diag_init data
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diag_dc : IN STD_LOGIC := '0'; -- '0' = output diag_sel sequence data, '1' = output constant diag_init data
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diag_init : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := TO_UVEC(g_init, g_dat_w); -- init value for out_dat when diag_en = '0'
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diag_init : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := TO_UVEC(g_init, g_dat_w); -- init value for out_dat when diag_en = '0'
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diag_mod : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := TO_UVEC(0, g_dat_w); -- default 0 to wrap modulo 2*g_dat_w
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diag_mod : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := TO_UVEC(0, g_dat_w); -- default 0 to wrap modulo 2*g_dat_w
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-- ST output
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-- ST output
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diag_req : IN STD_LOGIC := '1'; -- '1' = request output, '0' = halt output
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diag_req : IN STD_LOGIC := '1'; -- '1' = request output, '0' = halt output
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out_cnt : OUT STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0); -- count valid output test sequence data
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out_cnt : OUT STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0); -- count valid output test sequence data
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out_dat : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0); -- output test sequence data
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out_dat : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0); -- output test sequence data
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out_val : OUT STD_LOGIC -- '1' when out_dat is valid
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out_val : OUT STD_LOGIC -- '1' when out_dat is valid
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);
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);
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END diag_tx_seq;
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END diag_tx_seq;
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ARCHITECTURE rtl OF diag_tx_seq IS
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ARCHITECTURE rtl OF diag_tx_seq IS
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CONSTANT c_lfsr_nr : NATURAL := g_dat_w - c_common_lfsr_first;
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CONSTANT c_lfsr_nr : NATURAL := g_dat_w - c_common_lfsr_first;
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SIGNAL diag_dis : STD_LOGIC;
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SIGNAL diag_dis : STD_LOGIC;
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SIGNAL prsg : STD_LOGIC_VECTOR(out_dat'RANGE);
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SIGNAL prsg : STD_LOGIC_VECTOR(out_dat'RANGE);
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SIGNAL nxt_prsg : STD_LOGIC_VECTOR(out_dat'RANGE);
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SIGNAL nxt_prsg : STD_LOGIC_VECTOR(out_dat'RANGE);
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SIGNAL cntr : STD_LOGIC_VECTOR(out_dat'RANGE) := (OTHERS=>'0'); -- init to avoid Warning: "NUMERIC_STD."<": metavalue detected" with UNSIGNED()
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SIGNAL cntr : STD_LOGIC_VECTOR(out_dat'RANGE) := (OTHERS=>'0'); -- init to avoid Warning: "NUMERIC_STD."<": metavalue detected" with UNSIGNED()
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SIGNAL next_cntr : STD_LOGIC_VECTOR(out_dat'RANGE) := (OTHERS=>'0'); -- init to avoid Warning: "NUMERIC_STD."<": metavalue detected" with UNSIGNED()
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SIGNAL next_cntr : STD_LOGIC_VECTOR(out_dat'RANGE) := (OTHERS=>'0'); -- init to avoid Warning: "NUMERIC_STD."<": metavalue detected" with UNSIGNED()
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SIGNAL nxt_cntr : STD_LOGIC_VECTOR(out_dat'RANGE);
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SIGNAL nxt_cntr : STD_LOGIC_VECTOR(out_dat'RANGE);
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SIGNAL nxt_out_dat : STD_LOGIC_VECTOR(out_dat'RANGE);
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SIGNAL nxt_out_dat : STD_LOGIC_VECTOR(out_dat'RANGE);
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SIGNAL nxt_out_val : STD_LOGIC;
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SIGNAL nxt_out_val : STD_LOGIC;
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BEGIN
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BEGIN
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diag_dis <= NOT diag_en;
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diag_dis <= NOT diag_en;
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p_clk : PROCESS (rst, clk)
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p_clk : PROCESS (rst, clk)
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BEGIN
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BEGIN
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IF rst='1' THEN
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IF rst='1' THEN
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prsg <= (OTHERS=>'0');
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prsg <= (OTHERS=>'0');
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cntr <= (OTHERS=>'0');
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cntr <= (OTHERS=>'0');
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ELSIF rising_edge(clk) THEN
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ELSIF rising_edge(clk) THEN
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IF clken='1' THEN
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IF clken='1' THEN
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prsg <= nxt_prsg;
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prsg <= nxt_prsg;
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cntr <= nxt_cntr;
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cntr <= nxt_cntr;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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gen_latency : IF g_latency/=0 GENERATE
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gen_latency : IF g_latency/=0 GENERATE
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p_clk : PROCESS (rst, clk)
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p_clk : PROCESS (rst, clk)
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BEGIN
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BEGIN
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IF rst='1' THEN
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IF rst='1' THEN
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out_dat <= (OTHERS=>'0');
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out_dat <= (OTHERS=>'0');
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out_val <= '0';
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out_val <= '0';
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ELSIF rising_edge(clk) THEN
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ELSIF rising_edge(clk) THEN
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IF clken='1' THEN
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IF clken='1' THEN
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out_dat <= nxt_out_dat;
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out_dat <= nxt_out_dat;
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out_val <= nxt_out_val;
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out_val <= nxt_out_val;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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END GENERATE;
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END GENERATE;
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no_latency : IF g_latency=0 GENERATE
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no_latency : IF g_latency=0 GENERATE
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out_dat <= nxt_out_dat;
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out_dat <= nxt_out_dat;
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out_val <= nxt_out_val;
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out_val <= nxt_out_val;
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END GENERATE;
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END GENERATE;
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common_lfsr_nxt_seq(c_lfsr_nr, -- IN
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common_lfsr_nxt_seq(c_lfsr_nr, -- IN
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g_cnt_incr, -- IN
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g_cnt_incr, -- IN
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diag_en, -- IN
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diag_en, -- IN
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diag_req, -- IN
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diag_req, -- IN
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diag_init, -- IN
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diag_init, -- IN
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prsg, -- IN
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prsg, -- IN
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cntr, -- IN
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cntr, -- IN
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nxt_prsg, -- OUT
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nxt_prsg, -- OUT
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next_cntr); -- OUT
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next_cntr); -- OUT
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nxt_cntr <= next_cntr WHEN UNSIGNED(next_cntr) < UNSIGNED(diag_mod) ELSE SUB_UVEC(next_cntr, diag_mod);
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nxt_cntr <= next_cntr WHEN UNSIGNED(next_cntr) < UNSIGNED(diag_mod) ELSE SUB_UVEC(next_cntr, diag_mod);
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nxt_out_dat <= diag_init WHEN diag_dc='1' ELSE prsg WHEN diag_sel='0' ELSE cntr;
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nxt_out_dat <= diag_init WHEN diag_dc='1' ELSE prsg WHEN diag_sel='0' ELSE cntr;
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nxt_out_val <= diag_en AND diag_req; -- 'en' for entire test on/off, 'req' for dynamic invalid gaps in the stream
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nxt_out_val <= diag_en AND diag_req; -- 'en' for entire test on/off, 'req' for dynamic invalid gaps in the stream
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-- Count number of valid output data
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-- Count number of valid output data
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u_common_counter : ENTITY common_counter_lib.common_counter
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u_common_counter : ENTITY astron_counter_lib.common_counter
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GENERIC MAP (
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GENERIC MAP (
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g_latency => g_latency, -- default 1 for registered count output, use 0 for immediate combinatorial count output
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g_latency => g_latency, -- default 1 for registered count output, use 0 for immediate combinatorial count output
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g_width => g_cnt_w
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g_width => g_cnt_w
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)
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)
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PORT MAP (
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PORT MAP (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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clken => clken,
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clken => clken,
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cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
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cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
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cnt_en => nxt_out_val,
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cnt_en => nxt_out_val,
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count => out_cnt
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count => out_cnt
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);
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);
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END rtl;
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END rtl;
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