-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright 2020
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- You may obtain a copy of the License at
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--
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Purpose: Dual clock FIFO
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-- Purpose: Dual clock FIFO
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LIBRARY IEEE, common_pkg_lib, common_components_lib, technology_lib, tech_fifo_lib;
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LIBRARY IEEE, common_pkg_lib, common_components_lib;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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--USE technology_lib.technology_select_pkg.ALL;
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ENTITY common_fifo_dc IS
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ENTITY common_fifo_dc IS
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GENERIC (
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GENERIC (
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g_technology : NATURAL := c_tech_select_default;
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g_technology : NATURAL := 0; --c_tech_select_default;
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g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
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g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
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g_fail_rd_emp : BOOLEAN := FALSE; -- when TRUE report FAILURE when read from an empty FIFO
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g_fail_rd_emp : BOOLEAN := FALSE; -- when TRUE report FAILURE when read from an empty FIFO
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g_dat_w : NATURAL := 36;
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g_dat_w : NATURAL := 36;
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g_nof_words : NATURAL := 256 -- 36 * 256 = 1 M9K
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g_nof_words : NATURAL := 256 -- 36 * 256 = 1 M9K
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);
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);
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PORT (
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PORT (
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rst : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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wr_clk : IN STD_LOGIC;
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wr_clk : IN STD_LOGIC;
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wr_dat : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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wr_dat : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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wr_req : IN STD_LOGIC;
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wr_req : IN STD_LOGIC;
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wr_ful : OUT STD_LOGIC;
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wr_ful : OUT STD_LOGIC;
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wrusedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_nof_words)-1 DOWNTO 0);
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wrusedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_nof_words)-1 DOWNTO 0);
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rd_clk : IN STD_LOGIC;
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rd_clk : IN STD_LOGIC;
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rd_dat : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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rd_dat : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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rd_req : IN STD_LOGIC;
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rd_req : IN STD_LOGIC;
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rd_emp : OUT STD_LOGIC;
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rd_emp : OUT STD_LOGIC;
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rdusedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_nof_words)-1 DOWNTO 0);
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rdusedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_nof_words)-1 DOWNTO 0);
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rd_val : OUT STD_LOGIC := '0'
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rd_val : OUT STD_LOGIC := '0'
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);
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);
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END common_fifo_dc;
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END common_fifo_dc;
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ARCHITECTURE str of common_fifo_dc IS
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ARCHITECTURE str of common_fifo_dc IS
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CONSTANT c_nof_words : NATURAL := 2**ceil_log2(g_nof_words); -- ensure size is power of 2 for dual clock FIFO
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CONSTANT c_nof_words : NATURAL := 2**ceil_log2(g_nof_words); -- ensure size is power of 2 for dual clock FIFO
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SIGNAL wr_rst : STD_LOGIC;
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SIGNAL wr_rst : STD_LOGIC;
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SIGNAL wr_init : STD_LOGIC;
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SIGNAL wr_init : STD_LOGIC;
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SIGNAL wr_en : STD_LOGIC;
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SIGNAL wr_en : STD_LOGIC;
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SIGNAL rd_en : STD_LOGIC;
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SIGNAL rd_en : STD_LOGIC;
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SIGNAL ful : STD_LOGIC;
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SIGNAL ful : STD_LOGIC;
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SIGNAL emp : STD_LOGIC;
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SIGNAL emp : STD_LOGIC;
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SIGNAL nxt_rd_val : STD_LOGIC;
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SIGNAL nxt_rd_val : STD_LOGIC;
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BEGIN
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BEGIN
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-- Control logic copied from LOFAR common_fifo_dc(virtex4).vhd
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-- Control logic copied from LOFAR common_fifo_dc(virtex4).vhd
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-- Need to make sure the reset lasts at least 3 cycles (see fifo_generator_ug175.pdf)
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-- Need to make sure the reset lasts at least 3 cycles (see fifo_generator_ug175.pdf)
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-- Wait at least 4 cycles after reset release before allowing FIFO wr_en (see fifo_generator_ug175.pdf)
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-- Wait at least 4 cycles after reset release before allowing FIFO wr_en (see fifo_generator_ug175.pdf)
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-- Use common_areset to:
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-- Use common_areset to:
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-- . asynchronously detect rst even when the wr_clk is stopped
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-- . asynchronously detect rst even when the wr_clk is stopped
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-- . synchronize release of rst to wr_clk domain
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-- . synchronize release of rst to wr_clk domain
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-- Using common_areset is equivalent to using common_async with same signal applied to rst and din.
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-- Using common_areset is equivalent to using common_async with same signal applied to rst and din.
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u_wr_rst : ENTITY common_components_lib.common_areset
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u_wr_rst : ENTITY common_components_lib.common_areset
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GENERIC MAP (
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GENERIC MAP (
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g_rst_level => '1',
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g_rst_level => '1',
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g_delay_len => 3
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g_delay_len => 3
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)
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)
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PORT MAP (
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PORT MAP (
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in_rst => rst,
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in_rst => rst,
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clk => wr_clk,
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clk => wr_clk,
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out_rst => wr_rst
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out_rst => wr_rst
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);
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);
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-- Delay wr_init to ensure that FIFO ful has gone low after reset release
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-- Delay wr_init to ensure that FIFO ful has gone low after reset release
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u_wr_init : ENTITY common_components_lib.common_areset
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u_wr_init : ENTITY common_components_lib.common_areset
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GENERIC MAP (
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GENERIC MAP (
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g_rst_level => '1',
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g_rst_level => '1',
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g_delay_len => 4
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g_delay_len => 4
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)
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)
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PORT MAP (
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PORT MAP (
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in_rst => wr_rst,
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in_rst => wr_rst,
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clk => wr_clk,
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clk => wr_clk,
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out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
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out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
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);
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);
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-- The FIFO under read and over write protection are kept enabled in the MegaWizard
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-- The FIFO under read and over write protection are kept enabled in the MegaWizard
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wr_en <= wr_req AND NOT wr_init; -- check on NOT ful is not necessary when overflow_checking="ON" (Altera) or according to fifo_generator_ug175.pdf (Xilinx)
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wr_en <= wr_req AND NOT wr_init; -- check on NOT ful is not necessary when overflow_checking="ON" (Altera) or according to fifo_generator_ug175.pdf (Xilinx)
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rd_en <= rd_req; -- check on NOT emp is not necessary when underflow_checking="ON" (Altera)
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rd_en <= rd_req; -- check on NOT emp is not necessary when underflow_checking="ON" (Altera)
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nxt_rd_val <= rd_req AND NOT emp; -- check on NOT emp is necessary for rd_val
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nxt_rd_val <= rd_req AND NOT emp; -- check on NOT emp is necessary for rd_val
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wr_ful <= ful WHEN wr_init='0' ELSE '0';
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wr_ful <= ful WHEN wr_init='0' ELSE '0';
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rd_emp <= emp;
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rd_emp <= emp;
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p_rd_clk : PROCESS(rd_clk)
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p_rd_clk : PROCESS(rd_clk)
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BEGIN
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BEGIN
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IF rising_edge(rd_clk) THEN
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IF rising_edge(rd_clk) THEN
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rd_val <= nxt_rd_val;
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rd_val <= nxt_rd_val;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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u_fifo : ENTITY tech_fifo_lib.tech_fifo_dc
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u_fifo : ENTITY work.tech_fifo_dc
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GENERIC MAP (
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GENERIC MAP (
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g_technology => g_technology,
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g_technology => g_technology,
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g_dat_w => g_dat_w,
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g_dat_w => g_dat_w,
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g_nof_words => c_nof_words
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g_nof_words => c_nof_words
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)
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)
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PORT MAP (
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PORT MAP (
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aclr => wr_rst, -- MegaWizard fifo_dc seems to use aclr synchronous with wr_clk
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aclr => wr_rst, -- MegaWizard fifo_dc seems to use aclr synchronous with wr_clk
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data => wr_dat,
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data => wr_dat,
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rdclk => rd_clk,
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rdclk => rd_clk,
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rdreq => rd_en,
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rdreq => rd_en,
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wrclk => wr_clk,
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wrclk => wr_clk,
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wrreq => wr_en,
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wrreq => wr_en,
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q => rd_dat,
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q => rd_dat,
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rdempty => emp,
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rdempty => emp,
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rdusedw => rdusedw,
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rdusedw => rdusedw,
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wrfull => ful,
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wrfull => ful,
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wrusedw => wrusedw
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wrusedw => wrusedw
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);
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);
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proc_common_fifo_asserts("common_fifo_dc", g_note_is_ful, g_fail_rd_emp, wr_rst, wr_clk, ful, wr_en, rd_clk, emp, rd_en);
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proc_common_fifo_asserts("common_fifo_dc", g_note_is_ful, g_fail_rd_emp, wr_rst, wr_clk, ful, wr_en, rd_clk, emp, rd_en);
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END str;
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END str;
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