-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright (C) 2013
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- This program is free software: you can redistribute it and/or modify
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- it under the terms of the GNU General Public License as published by
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-- you may not use this file except in compliance with the License.
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-- the Free Software Foundation, either version 3 of the License, or
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-- You may obtain a copy of the License at
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- Unless required by applicable law or agreed to in writing, software
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- >>> Ported from UniBoard dp_latency_adapter for fixed RL 0 --> 1
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-- >>> Ported from UniBoard dp_latency_adapter for fixed RL 0 --> 1
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LIBRARY IEEE;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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-- Purpose: Adapt from ready latency 1 to 0 to make a look ahead FIFO
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-- Purpose: Adapt from ready latency 1 to 0 to make a look ahead FIFO
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-- Description: -
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-- Description: -
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-- Remark:
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-- Remark:
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-- . A show ahead FIFO with RL=0 does not need a rd_emp output signal, because
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-- . A show ahead FIFO with RL=0 does not need a rd_emp output signal, because
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-- with RL=0 the rd_val='0' when it is empty (so emp <= NOT rd_val).
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-- with RL=0 the rd_val='0' when it is empty (so emp <= NOT rd_val).
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ENTITY common_rl_decrease IS
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ENTITY common_rl_decrease IS
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GENERIC (
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GENERIC (
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g_adapt : BOOLEAN := TRUE; -- default when TRUE then decrease sink RL 1 to source RL 0, else then implement wires
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g_adapt : BOOLEAN := TRUE; -- default when TRUE then decrease sink RL 1 to source RL 0, else then implement wires
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g_dat_w : NATURAL := 18
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g_dat_w : NATURAL := 18
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);
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);
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PORT (
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PORT (
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rst : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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-- ST sink: RL = 1
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-- ST sink: RL = 1
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snk_out_ready : OUT STD_LOGIC;
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snk_out_ready : OUT STD_LOGIC;
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snk_in_dat : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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snk_in_dat : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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snk_in_val : IN STD_LOGIC := 'X';
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snk_in_val : IN STD_LOGIC := 'X';
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-- ST source: RL = 0
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-- ST source: RL = 0
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src_in_ready : IN STD_LOGIC;
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src_in_ready : IN STD_LOGIC;
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src_out_dat : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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src_out_dat : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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src_out_val : OUT STD_LOGIC
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src_out_val : OUT STD_LOGIC
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);
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);
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END common_rl_decrease;
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END common_rl_decrease;
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ARCHITECTURE rtl OF common_rl_decrease IS
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ARCHITECTURE rtl OF common_rl_decrease IS
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-- Internally use streaming record for the SOSI, for the SISO.ready directly use src_in_ready
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-- Internally use streaming record for the SOSI, for the SISO.ready directly use src_in_ready
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TYPE t_sosi IS RECORD -- Source Out or Sink In
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TYPE t_sosi IS RECORD -- Source Out or Sink In
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data : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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data : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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valid : STD_LOGIC;
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valid : STD_LOGIC;
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END RECORD;
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END RECORD;
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TYPE t_sosi_arr IS ARRAY (INTEGER RANGE <>) OF t_sosi;
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TYPE t_sosi_arr IS ARRAY (INTEGER RANGE <>) OF t_sosi;
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CONSTANT c_sosi_rst : t_sosi := ((OTHERS=>'0'), '0');
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CONSTANT c_sosi_rst : t_sosi := ((OTHERS=>'0'), '0');
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-- SOSI IO
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-- SOSI IO
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SIGNAL snk_in : t_sosi;
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SIGNAL snk_in : t_sosi;
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SIGNAL src_out : t_sosi;
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SIGNAL src_out : t_sosi;
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-- The default FIFO has ready latency RL = 1, need to use input RL + 1 words for the buf array, to go to output RL = 0 for show ahead FIFO
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-- The default FIFO has ready latency RL = 1, need to use input RL + 1 words for the buf array, to go to output RL = 0 for show ahead FIFO
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SIGNAL buf : t_sosi_arr(1 DOWNTO 0);
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SIGNAL buf : t_sosi_arr(1 DOWNTO 0);
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SIGNAL nxt_buf : t_sosi_arr(1 DOWNTO 0);
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SIGNAL nxt_buf : t_sosi_arr(1 DOWNTO 0);
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BEGIN
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BEGIN
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gen_wires : IF g_adapt=FALSE GENERATE
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gen_wires : IF g_adapt=FALSE GENERATE
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snk_out_ready <= src_in_ready;
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snk_out_ready <= src_in_ready;
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src_out_dat <= snk_in_dat;
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src_out_dat <= snk_in_dat;
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src_out_val <= snk_in_val;
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src_out_val <= snk_in_val;
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END GENERATE;
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END GENERATE;
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gen_adapt : IF g_adapt=TRUE GENERATE
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gen_adapt : IF g_adapt=TRUE GENERATE
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snk_in.data <= snk_in_dat;
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snk_in.data <= snk_in_dat;
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snk_in.valid <= snk_in_val;
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snk_in.valid <= snk_in_val;
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src_out_dat <= src_out.data;
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src_out_dat <= src_out.data;
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src_out_val <= src_out.valid;
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src_out_val <= src_out.valid;
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-- Buf[0] contains the FIFO output with zero ready latency
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-- Buf[0] contains the FIFO output with zero ready latency
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src_out <= buf(0);
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src_out <= buf(0);
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p_clk : PROCESS(rst, clk)
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p_clk : PROCESS(rst, clk)
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BEGIN
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BEGIN
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IF rst='1' THEN
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IF rst='1' THEN
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buf <= (OTHERS=>c_sosi_rst);
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buf <= (OTHERS=>c_sosi_rst);
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ELSIF rising_edge(clk) THEN
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ELSIF rising_edge(clk) THEN
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buf <= nxt_buf;
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buf <= nxt_buf;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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p_snk_out_ready : PROCESS(buf, src_in_ready, snk_in)
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p_snk_out_ready : PROCESS(buf, src_in_ready, snk_in)
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BEGIN
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BEGIN
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snk_out_ready <= '0';
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snk_out_ready <= '0';
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IF src_in_ready='1' THEN
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IF src_in_ready='1' THEN
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-- Default snk_out_ready when src_in_ready.
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-- Default snk_out_ready when src_in_ready.
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snk_out_ready <= '1';
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snk_out_ready <= '1';
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ELSE
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ELSE
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-- Extra snk_out_ready to look ahead for RL = 0.
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-- Extra snk_out_ready to look ahead for RL = 0.
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IF buf(0).valid='0' THEN
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IF buf(0).valid='0' THEN
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snk_out_ready <= '1';
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snk_out_ready <= '1';
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ELSIF buf(1).valid='0' THEN
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ELSIF buf(1).valid='0' THEN
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snk_out_ready <= NOT(snk_in.valid);
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snk_out_ready <= NOT(snk_in.valid);
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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p_buf : PROCESS(buf, src_in_ready, snk_in)
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p_buf : PROCESS(buf, src_in_ready, snk_in)
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BEGIN
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BEGIN
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-- Keep or shift the buf dependent on src_in_ready, no need to explicitly check buf().valid
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-- Keep or shift the buf dependent on src_in_ready, no need to explicitly check buf().valid
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nxt_buf <= buf;
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nxt_buf <= buf;
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IF src_in_ready='1' THEN
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IF src_in_ready='1' THEN
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nxt_buf(0) <= buf(1);
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nxt_buf(0) <= buf(1);
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nxt_buf(1).valid <= '0'; -- not strictly necessary, but robust
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nxt_buf(1).valid <= '0'; -- not strictly necessary, but robust
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END IF;
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END IF;
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-- Put input data at the first available location dependent on src_in_ready, no need to explicitly check snk_in_val
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-- Put input data at the first available location dependent on src_in_ready, no need to explicitly check snk_in_val
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IF buf(0).valid='0' THEN
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IF buf(0).valid='0' THEN
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nxt_buf(0) <= snk_in;
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nxt_buf(0) <= snk_in;
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ELSE
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ELSE
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IF buf(1).valid='0' THEN
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IF buf(1).valid='0' THEN
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IF src_in_ready='0' THEN
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IF src_in_ready='0' THEN
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nxt_buf(1) <= snk_in;
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nxt_buf(1) <= snk_in;
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ELSE
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ELSE
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nxt_buf(0) <= snk_in;
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nxt_buf(0) <= snk_in;
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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END GENERATE;
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END GENERATE;
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END rtl;
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END rtl;
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