-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright 2020
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- You may obtain a copy of the License at
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--
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Purpose:
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-- Purpose:
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-- Provide input ready control and use output ready control to the FIFO.
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-- Provide input ready control and use output ready control to the FIFO.
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-- Pass sop and eop along with the data through the FIFO if g_use_ctrl=TRUE.
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-- Pass sop and eop along with the data through the FIFO if g_use_ctrl=TRUE.
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-- Default the RL=1, use g_fifo_rl=0 for a the show ahead FIFO.
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-- Default the RL=1, use g_fifo_rl=0 for a the show ahead FIFO.
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-- Description:
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-- Description:
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-- Provide the sink ready for FIFO write control and use source ready for
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-- Provide the sink ready for FIFO write control and use source ready for
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-- FIFO read access. The sink ready output is derived from FIFO almost full.
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-- FIFO read access. The sink ready output is derived from FIFO almost full.
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-- Data without framing can use g_use_ctrl=FALSE to avoid implementing two
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-- Data without framing can use g_use_ctrl=FALSE to avoid implementing two
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-- data bits for sop and eop in the FIFO word width. Idem for g_use_sync,
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-- data bits for sop and eop in the FIFO word width. Idem for g_use_sync,
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-- g_use_empty, g_use_channel and g_use_error.
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-- g_use_empty, g_use_channel and g_use_error.
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-- Remark:
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-- Remark:
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-- . The bsn, empty, channel and error fields are valid at the sop and or eop.
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-- . The bsn, empty, channel and error fields are valid at the sop and or eop.
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-- Therefore alternatively these fields can be passed on through a separate
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-- Therefore alternatively these fields can be passed on through a separate
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-- FIFO, with only one entry per frame, to save FIFO memory in case
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-- FIFO, with only one entry per frame, to save FIFO memory in case
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-- concatenating them makes the FIFO word width larger than a standard
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-- concatenating them makes the FIFO word width larger than a standard
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-- memory data word width.
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-- memory data word width.
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-- . The FIFO makes that the src_in.ready and snk_out.ready are not
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-- . The FIFO makes that the src_in.ready and snk_out.ready are not
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-- combinatorially connected, so this can ease the timing closure for the
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-- combinatorially connected, so this can ease the timing closure for the
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-- ready signal.
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-- ready signal.
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LIBRARY IEEE, common_pkg_lib, dp_components_lib, common_fifo_lib, dp_pkg_lib, technology_lib;
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LIBRARY IEEE, common_pkg_lib, dp_components_lib, dp_pkg_lib;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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--USE technology_lib.technology_select_pkg.ALL;
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ENTITY dp_fifo_core IS
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ENTITY dp_fifo_core IS
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GENERIC (
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GENERIC (
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g_technology : NATURAL := c_tech_select_default;
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g_technology : NATURAL := 0;
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g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
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g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
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g_use_dual_clock : BOOLEAN := FALSE;
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g_use_dual_clock : BOOLEAN := FALSE;
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g_use_lut_sc : BOOLEAN := FALSE; -- when TRUE then force using LUTs instead of block RAM for single clock FIFO (bot available for dual clock FIFO)
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g_use_lut_sc : BOOLEAN := FALSE; -- when TRUE then force using LUTs instead of block RAM for single clock FIFO (bot available for dual clock FIFO)
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g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
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g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
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g_data_signed : BOOLEAN := FALSE; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
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g_data_signed : BOOLEAN := FALSE; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
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g_bsn_w : NATURAL := 1;
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g_bsn_w : NATURAL := 1;
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g_empty_w : NATURAL := 1;
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g_empty_w : NATURAL := 1;
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g_channel_w : NATURAL := 1;
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g_channel_w : NATURAL := 1;
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g_error_w : NATURAL := 1;
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g_error_w : NATURAL := 1;
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g_use_bsn : BOOLEAN := FALSE;
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g_use_bsn : BOOLEAN := FALSE;
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g_use_empty : BOOLEAN := FALSE;
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g_use_empty : BOOLEAN := FALSE;
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g_use_channel : BOOLEAN := FALSE;
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g_use_channel : BOOLEAN := FALSE;
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g_use_error : BOOLEAN := FALSE;
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g_use_error : BOOLEAN := FALSE;
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g_use_sync : BOOLEAN := FALSE;
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g_use_sync : BOOLEAN := FALSE;
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g_use_ctrl : BOOLEAN := TRUE; -- sop & eop
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g_use_ctrl : BOOLEAN := TRUE; -- sop & eop
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g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
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g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
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g_fifo_size : NATURAL := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
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g_fifo_size : NATURAL := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
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g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full
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g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full
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g_fifo_rl : NATURAL := 1
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g_fifo_rl : NATURAL := 1
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);
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);
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PORT (
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PORT (
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wr_rst : IN STD_LOGIC;
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wr_rst : IN STD_LOGIC;
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wr_clk : IN STD_LOGIC;
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wr_clk : IN STD_LOGIC;
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rd_rst : IN STD_LOGIC;
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rd_rst : IN STD_LOGIC;
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rd_clk : IN STD_LOGIC;
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rd_clk : IN STD_LOGIC;
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-- Monitor FIFO filling
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-- Monitor FIFO filling
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wr_ful : OUT STD_LOGIC; -- corresponds to the carry bit of wr_usedw when FIFO is full
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wr_ful : OUT STD_LOGIC; -- corresponds to the carry bit of wr_usedw when FIFO is full
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wr_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
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wr_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
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rd_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
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rd_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
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rd_emp : OUT STD_LOGIC;
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rd_emp : OUT STD_LOGIC;
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-- ST sink
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-- ST sink
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snk_out : OUT t_dp_siso;
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snk_out : OUT t_dp_siso;
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snk_in : IN t_dp_sosi;
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snk_in : IN t_dp_sosi;
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-- ST source
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-- ST source
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src_in : IN t_dp_siso;
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src_in : IN t_dp_siso;
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src_out : OUT t_dp_sosi
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src_out : OUT t_dp_sosi
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);
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);
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END dp_fifo_core;
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END dp_fifo_core;
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ARCHITECTURE str OF dp_fifo_core IS
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ARCHITECTURE str OF dp_fifo_core IS
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CONSTANT c_use_data : BOOLEAN := TRUE;
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CONSTANT c_use_data : BOOLEAN := TRUE;
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CONSTANT c_ctrl_w : NATURAL := 2; -- sop and eop
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CONSTANT c_ctrl_w : NATURAL := 2; -- sop and eop
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CONSTANT c_complex_w : NATURAL := smallest(c_dp_stream_dsp_data_w, g_data_w/2); -- needed to cope with g_data_w > 2*c_dp_stream_dsp_data_w
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CONSTANT c_complex_w : NATURAL := smallest(c_dp_stream_dsp_data_w, g_data_w/2); -- needed to cope with g_data_w > 2*c_dp_stream_dsp_data_w
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CONSTANT c_fifo_almost_full : NATURAL := g_fifo_size-g_fifo_af_margin; -- FIFO almost full level for snk_out.ready
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CONSTANT c_fifo_almost_full : NATURAL := g_fifo_size-g_fifo_af_margin; -- FIFO almost full level for snk_out.ready
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CONSTANT c_fifo_dat_w : NATURAL := func_slv_concat_w(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl,
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CONSTANT c_fifo_dat_w : NATURAL := func_slv_concat_w(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl,
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g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w); -- concat via FIFO
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g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w); -- concat via FIFO
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SIGNAL nxt_snk_out : t_dp_siso := c_dp_siso_rst;
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SIGNAL nxt_snk_out : t_dp_siso := c_dp_siso_rst;
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SIGNAL arst : STD_LOGIC;
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SIGNAL arst : STD_LOGIC;
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SIGNAL wr_data_complex : STD_LOGIC_VECTOR(2*c_complex_w-1 DOWNTO 0);
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SIGNAL wr_data_complex : STD_LOGIC_VECTOR(2*c_complex_w-1 DOWNTO 0);
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SIGNAL wr_data : STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
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SIGNAL wr_data : STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
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SIGNAL rd_data : STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
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SIGNAL rd_data : STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
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SIGNAL fifo_wr_dat : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0);
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SIGNAL fifo_wr_dat : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0);
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SIGNAL fifo_wr_req : STD_LOGIC;
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SIGNAL fifo_wr_req : STD_LOGIC;
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SIGNAL fifo_wr_ful : STD_LOGIC;
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SIGNAL fifo_wr_ful : STD_LOGIC;
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SIGNAL fifo_wr_usedw : STD_LOGIC_VECTOR(wr_usedw'RANGE);
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SIGNAL fifo_wr_usedw : STD_LOGIC_VECTOR(wr_usedw'RANGE);
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SIGNAL fifo_rd_dat : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
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SIGNAL fifo_rd_dat : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
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SIGNAL fifo_rd_val : STD_LOGIC;
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SIGNAL fifo_rd_val : STD_LOGIC;
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SIGNAL fifo_rd_req : STD_LOGIC;
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SIGNAL fifo_rd_req : STD_LOGIC;
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SIGNAL fifo_rd_emp : STD_LOGIC;
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SIGNAL fifo_rd_emp : STD_LOGIC;
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SIGNAL fifo_rd_usedw : STD_LOGIC_VECTOR(rd_usedw'RANGE);
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SIGNAL fifo_rd_usedw : STD_LOGIC_VECTOR(rd_usedw'RANGE);
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SIGNAL wr_sync : STD_LOGIC_VECTOR(0 DOWNTO 0);
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SIGNAL wr_sync : STD_LOGIC_VECTOR(0 DOWNTO 0);
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SIGNAL rd_sync : STD_LOGIC_VECTOR(0 DOWNTO 0);
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SIGNAL rd_sync : STD_LOGIC_VECTOR(0 DOWNTO 0);
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SIGNAL wr_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL wr_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL rd_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL rd_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL rd_siso : t_dp_siso;
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SIGNAL rd_siso : t_dp_siso;
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SIGNAL rd_sosi : t_dp_sosi := c_dp_sosi_rst; -- initialize default values for unused sosi fields
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SIGNAL rd_sosi : t_dp_sosi := c_dp_sosi_rst; -- initialize default values for unused sosi fields
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BEGIN
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BEGIN
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-- Output monitor FIFO filling
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-- Output monitor FIFO filling
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wr_ful <= fifo_wr_ful;
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wr_ful <= fifo_wr_ful;
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wr_usedw <= fifo_wr_usedw;
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wr_usedw <= fifo_wr_usedw;
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rd_usedw <= fifo_rd_usedw;
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rd_usedw <= fifo_rd_usedw;
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rd_emp <= fifo_rd_emp;
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rd_emp <= fifo_rd_emp;
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p_wr_clk: PROCESS(wr_clk, wr_rst)
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p_wr_clk: PROCESS(wr_clk, wr_rst)
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BEGIN
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BEGIN
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IF wr_rst='1' THEN
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IF wr_rst='1' THEN
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snk_out <= c_dp_siso_rst;
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snk_out <= c_dp_siso_rst;
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ELSIF rising_edge(wr_clk) THEN
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ELSIF rising_edge(wr_clk) THEN
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snk_out <= nxt_snk_out;
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snk_out <= nxt_snk_out;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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wr_sync(0) <= snk_in.sync;
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wr_sync(0) <= snk_in.sync;
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wr_ctrl <= snk_in.sop & snk_in.eop;
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wr_ctrl <= snk_in.sop & snk_in.eop;
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-- Assign the snk_in data field or concatenated complex fields to the FIFO wr_data depending on g_use_complex
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-- Assign the snk_in data field or concatenated complex fields to the FIFO wr_data depending on g_use_complex
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wr_data_complex <= snk_in.im(c_complex_w-1 DOWNTO 0) & snk_in.re(c_complex_w-1 DOWNTO 0);
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wr_data_complex <= snk_in.im(c_complex_w-1 DOWNTO 0) & snk_in.re(c_complex_w-1 DOWNTO 0);
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wr_data <= snk_in.data(g_data_w-1 DOWNTO 0) WHEN g_use_complex = FALSE ELSE RESIZE_UVEC(wr_data_complex, g_data_w);
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wr_data <= snk_in.data(g_data_w-1 DOWNTO 0) WHEN g_use_complex = FALSE ELSE RESIZE_UVEC(wr_data_complex, g_data_w);
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-- fifo wr wires
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-- fifo wr wires
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fifo_wr_req <= snk_in.valid;
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fifo_wr_req <= snk_in.valid;
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fifo_wr_dat <= func_slv_concat(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl,
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fifo_wr_dat <= func_slv_concat(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl,
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wr_data,
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wr_data,
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snk_in.bsn( g_bsn_w-1 DOWNTO 0),
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snk_in.bsn( g_bsn_w-1 DOWNTO 0),
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snk_in.empty( g_empty_w-1 DOWNTO 0),
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snk_in.empty( g_empty_w-1 DOWNTO 0),
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snk_in.channel(g_channel_w-1 DOWNTO 0),
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snk_in.channel(g_channel_w-1 DOWNTO 0),
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snk_in.err( g_error_w-1 DOWNTO 0),
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snk_in.err( g_error_w-1 DOWNTO 0),
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wr_sync,
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wr_sync,
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wr_ctrl);
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wr_ctrl);
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-- pass on frame level flow control
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-- pass on frame level flow control
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nxt_snk_out.xon <= src_in.xon;
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nxt_snk_out.xon <= src_in.xon;
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-- up stream use fifo almost full to control snk_out.ready
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-- up stream use fifo almost full to control snk_out.ready
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nxt_snk_out.ready <= '1' WHEN UNSIGNED(fifo_wr_usedw)<c_fifo_almost_full ELSE '0';
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nxt_snk_out.ready <= '1' WHEN UNSIGNED(fifo_wr_usedw)<c_fifo_almost_full ELSE '0';
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gen_common_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
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gen_common_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
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u_common_fifo_sc : ENTITY common_fifo_lib.common_fifo_sc
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u_common_fifo_sc : ENTITY work.common_fifo_sc
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GENERIC MAP (
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GENERIC MAP (
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g_technology => g_technology,
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g_technology => g_technology,
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g_note_is_ful => g_note_is_ful,
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g_note_is_ful => g_note_is_ful,
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g_use_lut => g_use_lut_sc,
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g_use_lut => g_use_lut_sc,
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g_dat_w => c_fifo_dat_w,
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g_dat_w => c_fifo_dat_w,
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g_nof_words => g_fifo_size
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g_nof_words => g_fifo_size
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)
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)
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PORT MAP (
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PORT MAP (
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rst => rd_rst,
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rst => rd_rst,
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clk => rd_clk,
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clk => rd_clk,
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wr_dat => fifo_wr_dat,
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wr_dat => fifo_wr_dat,
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wr_req => fifo_wr_req,
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wr_req => fifo_wr_req,
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wr_ful => fifo_wr_ful,
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wr_ful => fifo_wr_ful,
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rd_dat => fifo_rd_dat,
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rd_dat => fifo_rd_dat,
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rd_req => fifo_rd_req,
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rd_req => fifo_rd_req,
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rd_emp => fifo_rd_emp,
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rd_emp => fifo_rd_emp,
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rd_val => fifo_rd_val,
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rd_val => fifo_rd_val,
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usedw => fifo_rd_usedw
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usedw => fifo_rd_usedw
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);
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);
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fifo_wr_usedw <= fifo_rd_usedw;
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fifo_wr_usedw <= fifo_rd_usedw;
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END GENERATE;
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END GENERATE;
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gen_common_fifo_dc : IF g_use_dual_clock=TRUE GENERATE
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gen_common_fifo_dc : IF g_use_dual_clock=TRUE GENERATE
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u_common_fifo_dc : ENTITY common_fifo_lib.common_fifo_dc
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u_common_fifo_dc : ENTITY work.common_fifo_dc
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GENERIC MAP (
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GENERIC MAP (
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g_technology => g_technology,
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g_technology => g_technology,
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g_dat_w => c_fifo_dat_w,
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g_dat_w => c_fifo_dat_w,
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g_nof_words => g_fifo_size
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g_nof_words => g_fifo_size
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)
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)
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PORT MAP (
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PORT MAP (
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rst => arst,
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rst => arst,
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wr_clk => wr_clk,
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wr_clk => wr_clk,
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wr_dat => fifo_wr_dat,
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wr_dat => fifo_wr_dat,
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wr_req => fifo_wr_req,
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wr_req => fifo_wr_req,
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wr_ful => fifo_wr_ful,
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wr_ful => fifo_wr_ful,
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wrusedw => fifo_wr_usedw,
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wrusedw => fifo_wr_usedw,
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rd_clk => rd_clk,
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rd_clk => rd_clk,
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rd_dat => fifo_rd_dat,
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rd_dat => fifo_rd_dat,
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rd_req => fifo_rd_req,
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rd_req => fifo_rd_req,
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rd_emp => fifo_rd_emp,
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rd_emp => fifo_rd_emp,
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rdusedw => fifo_rd_usedw,
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rdusedw => fifo_rd_usedw,
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rd_val => fifo_rd_val
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rd_val => fifo_rd_val
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);
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);
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arst <= wr_rst OR rd_rst;
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arst <= wr_rst OR rd_rst;
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END GENERATE;
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END GENERATE;
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-- Extract the data from the wide FIFO output SLV. rd_data will be assigned to rd_sosi.data or rd_sosi.im & rd_sosi.re depending on g_use_complex.
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-- Extract the data from the wide FIFO output SLV. rd_data will be assigned to rd_sosi.data or rd_sosi.im & rd_sosi.re depending on g_use_complex.
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rd_data <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 0);
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rd_data <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 0);
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-- fifo rd wires
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-- fifo rd wires
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-- SISO
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-- SISO
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fifo_rd_req <= rd_siso.ready;
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fifo_rd_req <= rd_siso.ready;
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-- SOSI
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-- SOSI
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rd_sosi.data <= RESIZE_DP_SDATA(rd_data) WHEN g_data_signed=TRUE ELSE RESIZE_DP_DATA(rd_data);
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rd_sosi.data <= RESIZE_DP_SDATA(rd_data) WHEN g_data_signed=TRUE ELSE RESIZE_DP_DATA(rd_data);
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rd_sosi.re <= RESIZE_DP_DSP_DATA(rd_data( c_complex_w-1 DOWNTO 0));
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rd_sosi.re <= RESIZE_DP_DSP_DATA(rd_data( c_complex_w-1 DOWNTO 0));
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rd_sosi.im <= RESIZE_DP_DSP_DATA(rd_data(2*c_complex_w-1 DOWNTO c_complex_w));
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rd_sosi.im <= RESIZE_DP_DSP_DATA(rd_data(2*c_complex_w-1 DOWNTO c_complex_w));
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rd_sosi.bsn <= RESIZE_DP_BSN(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 1));
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rd_sosi.bsn <= RESIZE_DP_BSN(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 1));
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rd_sosi.empty <= RESIZE_DP_EMPTY(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 2));
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rd_sosi.empty <= RESIZE_DP_EMPTY(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 2));
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rd_sosi.channel <= RESIZE_DP_CHANNEL(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 3));
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rd_sosi.channel <= RESIZE_DP_CHANNEL(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 3));
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rd_sosi.err <= RESIZE_DP_ERROR(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 4));
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rd_sosi.err <= RESIZE_DP_ERROR(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 4));
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rd_sync <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 5);
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rd_sync <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 5);
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rd_ctrl <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 6);
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rd_ctrl <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 6);
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rd_sosi.sync <= fifo_rd_val AND rd_sync(0);
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rd_sosi.sync <= fifo_rd_val AND rd_sync(0);
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rd_sosi.valid <= fifo_rd_val;
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rd_sosi.valid <= fifo_rd_val;
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rd_sosi.sop <= fifo_rd_val AND rd_ctrl(1);
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rd_sosi.sop <= fifo_rd_val AND rd_ctrl(1);
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rd_sosi.eop <= fifo_rd_val AND rd_ctrl(0);
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rd_sosi.eop <= fifo_rd_val AND rd_ctrl(0);
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u_ready_latency : ENTITY dp_components_lib.dp_latency_adapter
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u_ready_latency : ENTITY dp_components_lib.dp_latency_adapter
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GENERIC MAP (
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GENERIC MAP (
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g_in_latency => 1,
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g_in_latency => 1,
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g_out_latency => g_fifo_rl
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g_out_latency => g_fifo_rl
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)
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)
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PORT MAP (
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PORT MAP (
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rst => rd_rst,
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rst => rd_rst,
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clk => rd_clk,
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clk => rd_clk,
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-- ST sink
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-- ST sink
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snk_out => rd_siso,
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snk_out => rd_siso,
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snk_in => rd_sosi,
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snk_in => rd_sosi,
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-- ST source
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-- ST source
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src_in => src_in,
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src_in => src_in,
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src_out => src_out
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src_out => src_out
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);
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);
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END str;
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END str;
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