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--------------------------------------------------------------------------------
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--
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--
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-- Copyright 2020
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- You may obtain a copy of the License at
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--
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee, common_pkg_lib, common_counter_lib, common_ram_lib;
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library ieee, common_pkg_lib, astron_counter_lib, astron_ram_lib;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use common_pkg_lib.common_pkg.all;
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use common_pkg_lib.common_pkg.all;
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use common_ram_lib.common_ram_pkg.all;
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use astron_ram_lib.common_ram_pkg.all;
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entity rTwoOrder is
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entity rTwoOrder is
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generic (
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generic (
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g_nof_points : natural := 8;
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g_nof_points : natural := 8;
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g_bit_flip : boolean := true;
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g_bit_flip : boolean := true;
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g_nof_chan : natural := 0
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g_nof_chan : natural := 0
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);
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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in_dat : in std_logic_vector;
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in_dat : in std_logic_vector;
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in_val : in std_logic;
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in_val : in std_logic;
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out_dat : out std_logic_vector;
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out_dat : out std_logic_vector;
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out_val : out std_logic
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out_val : out std_logic
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);
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);
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end entity rTwoOrder;
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end entity rTwoOrder;
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architecture rtl of rTwoOrder is
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architecture rtl of rTwoOrder is
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constant c_nof_channels : natural := 2**g_nof_chan;
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constant c_nof_channels : natural := 2**g_nof_chan;
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constant c_dat_w : natural := in_dat'length;
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constant c_dat_w : natural := in_dat'length;
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constant c_page_size : natural := g_nof_points*c_nof_channels;
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constant c_page_size : natural := g_nof_points*c_nof_channels;
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constant c_adr_points_w : natural := ceil_log2(g_nof_points);
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constant c_adr_points_w : natural := ceil_log2(g_nof_points);
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constant c_adr_chan_w : natural := g_nof_chan;
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constant c_adr_chan_w : natural := g_nof_chan;
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constant c_adr_tot_w : natural := c_adr_points_w + c_adr_chan_w;
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constant c_adr_tot_w : natural := c_adr_points_w + c_adr_chan_w;
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signal adr_points_cnt : std_logic_vector(c_adr_points_w -1 downto 0);
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signal adr_points_cnt : std_logic_vector(c_adr_points_w -1 downto 0);
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signal adr_chan_cnt : std_logic_vector(c_adr_chan_w -1 downto 0);
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signal adr_chan_cnt : std_logic_vector(c_adr_chan_w -1 downto 0);
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signal adr_tot_cnt : std_logic_vector(c_adr_tot_w -1 downto 0);
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signal adr_tot_cnt : std_logic_vector(c_adr_tot_w -1 downto 0);
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signal in_init : STD_LOGIC;
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signal in_init : STD_LOGIC;
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signal nxt_in_init : STD_LOGIC;
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signal nxt_in_init : STD_LOGIC;
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signal in_en : STD_LOGIC;
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signal in_en : STD_LOGIC;
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signal cnt_ena : std_logic;
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signal cnt_ena : std_logic;
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signal next_page : STD_LOGIC;
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signal next_page : STD_LOGIC;
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signal wr_en : STD_LOGIC;
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signal wr_en : STD_LOGIC;
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signal wr_adr : STD_LOGIC_VECTOR(c_adr_tot_w-1 DOWNTO 0);
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signal wr_adr : STD_LOGIC_VECTOR(c_adr_tot_w-1 DOWNTO 0);
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signal wr_dat : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
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signal wr_dat : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
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signal rd_en : STD_LOGIC;
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signal rd_en : STD_LOGIC;
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signal rd_adr : STD_LOGIC_VECTOR(c_adr_tot_w-1 DOWNTO 0);
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signal rd_adr : STD_LOGIC_VECTOR(c_adr_tot_w-1 DOWNTO 0);
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signal rd_dat : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
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signal rd_dat : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
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signal rd_val : STD_LOGIC;
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signal rd_val : STD_LOGIC;
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begin
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begin
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out_dat <= rd_dat;
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out_dat <= rd_dat;
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out_val <= rd_val;
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out_val <= rd_val;
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p_clk : process(clk, rst)
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p_clk : process(clk, rst)
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begin
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begin
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if rst='1' then
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if rst='1' then
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in_init <= '1';
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in_init <= '1';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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in_init <= nxt_in_init;
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in_init <= nxt_in_init;
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end if;
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end if;
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end process;
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end process;
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nxt_in_init <= '0' WHEN next_page='1' ELSE in_init; -- keep in_init active until the first block has been written
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nxt_in_init <= '0' WHEN next_page='1' ELSE in_init; -- keep in_init active until the first block has been written
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in_en <= NOT in_init; -- disable reading of the first block for convenience in verification, because it contains undefined values
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in_en <= NOT in_init; -- disable reading of the first block for convenience in verification, because it contains undefined values
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wr_dat <= in_dat;
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wr_dat <= in_dat;
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wr_en <= in_val;
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wr_en <= in_val;
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rd_en <= in_val AND in_en;
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rd_en <= in_val AND in_en;
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next_page <= '1' when unsigned(adr_tot_cnt) = c_page_size-1 and wr_en='1' else '0';
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next_page <= '1' when unsigned(adr_tot_cnt) = c_page_size-1 and wr_en='1' else '0';
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adr_tot_cnt <= adr_chan_cnt & adr_points_cnt;
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adr_tot_cnt <= adr_chan_cnt & adr_points_cnt;
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gen_bit_flip : if g_bit_flip=true generate
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gen_bit_flip : if g_bit_flip=true generate
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wr_adr <= adr_chan_cnt & flip(adr_points_cnt); -- flip the addresses to perform the reorder
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wr_adr <= adr_chan_cnt & flip(adr_points_cnt); -- flip the addresses to perform the reorder
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end generate;
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end generate;
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no_bit_flip : if g_bit_flip=false generate
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no_bit_flip : if g_bit_flip=false generate
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wr_adr <= adr_tot_cnt; -- do not flip the addresses for easier debugging with tb_rTwoOrder
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wr_adr <= adr_tot_cnt; -- do not flip the addresses for easier debugging with tb_rTwoOrder
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end generate;
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end generate;
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rd_adr <= adr_tot_cnt;
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rd_adr <= adr_tot_cnt;
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u_adr_point_cnt : entity common_counter_lib.common_counter
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u_adr_point_cnt : entity astron_counter_lib.common_counter
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generic map(
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generic map(
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g_latency => 1,
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g_latency => 1,
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g_init => 0,
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g_init => 0,
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g_width => ceil_log2(g_nof_points)
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g_width => ceil_log2(g_nof_points)
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)
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)
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PORT MAP (
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PORT MAP (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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cnt_en => cnt_ena,
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cnt_en => cnt_ena,
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count => adr_points_cnt
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count => adr_points_cnt
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);
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);
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-- Generate on c_nof_channels to avoid simulation warnings on TO_UINT(adr_chan_cnt) when adr_chan_cnt is a NULL array
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-- Generate on c_nof_channels to avoid simulation warnings on TO_UINT(adr_chan_cnt) when adr_chan_cnt is a NULL array
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one_chan : if c_nof_channels=1 generate
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one_chan : if c_nof_channels=1 generate
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cnt_ena <= '1' when in_val = '1' else '0';
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cnt_ena <= '1' when in_val = '1' else '0';
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end generate;
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end generate;
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more_chan : if c_nof_channels>1 generate
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more_chan : if c_nof_channels>1 generate
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cnt_ena <= '1' when in_val = '1' and TO_UINT(adr_chan_cnt) = c_nof_channels-1 else '0';
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cnt_ena <= '1' when in_val = '1' and TO_UINT(adr_chan_cnt) = c_nof_channels-1 else '0';
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end generate;
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end generate;
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u_adr_chan_cnt : entity common_counter_lib.common_counter
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u_adr_chan_cnt : entity astron_counter_lib.common_counter
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generic map(
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generic map(
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g_latency => 1,
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g_latency => 1,
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g_init => 0,
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g_init => 0,
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g_width => g_nof_chan
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g_width => g_nof_chan
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)
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)
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PORT MAP (
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PORT MAP (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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cnt_en => in_val,
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cnt_en => in_val,
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count => adr_chan_cnt
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count => adr_chan_cnt
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);
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);
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u_buff : ENTITY common_ram_lib.common_paged_ram_r_w
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u_buff : ENTITY astron_ram_lib.common_paged_ram_r_w
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GENERIC MAP (
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GENERIC MAP (
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g_str => "use_adr",
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g_str => "use_adr",
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g_data_w => c_dat_w,
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g_data_w => c_dat_w,
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g_nof_pages => 2,
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g_nof_pages => 2,
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g_page_sz => c_page_size,
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g_page_sz => c_page_size,
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g_wr_start_page => 0,
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g_wr_start_page => 0,
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g_rd_start_page => 1,
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g_rd_start_page => 1,
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g_rd_latency => 1
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g_rd_latency => 1
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)
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)
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PORT MAP (
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PORT MAP (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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wr_next_page => next_page,
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wr_next_page => next_page,
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wr_adr => wr_adr,
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wr_adr => wr_adr,
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wr_en => wr_en,
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wr_en => wr_en,
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wr_dat => wr_dat,
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wr_dat => wr_dat,
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rd_next_page => next_page,
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rd_next_page => next_page,
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rd_adr => rd_adr,
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rd_adr => rd_adr,
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rd_en => rd_en,
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rd_en => rd_en,
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rd_dat => rd_dat,
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rd_dat => rd_dat,
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rd_val => rd_val
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rd_val => rd_val
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);
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);
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end rtl;
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end rtl;
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