--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--
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--
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-- Copyright 2020
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- You may obtain a copy of the License at
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--
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Purpose: Pipelined radix 2 FFT
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-- Purpose: Pipelined radix 2 FFT
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-- Description: ASTRON-RP-755
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-- Description: ASTRON-RP-755
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-- Remarks: doc/readme.txt
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-- Remarks: doc/readme.txt
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library ieee, common_pkg_lib, common_requantize_lib;
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library ieee, common_pkg_lib, astron_requantize_lib;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use common_pkg_lib.common_pkg.all;
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use common_pkg_lib.common_pkg.all;
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use work.twiddlesPkg.all;
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use work.twiddlesPkg.all;
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use work.rTwoSDFPkg.all;
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use work.rTwoSDFPkg.all;
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entity rTwoSDF is
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entity rTwoSDF is
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generic (
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generic (
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-- generics for the FFT
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-- generics for the FFT
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g_nof_chan : natural := 0; -- Exponent of nr of subbands (0 means 1 subband)
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g_nof_chan : natural := 0; -- Exponent of nr of subbands (0 means 1 subband)
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g_use_reorder : boolean := true;
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g_use_reorder : boolean := true;
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g_in_dat_w : natural := 8; -- number of input bits
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g_in_dat_w : natural := 8; -- number of input bits
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g_out_dat_w : natural := 14; -- number of output bits
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g_out_dat_w : natural := 14; -- number of output bits
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g_stage_dat_w : natural := 18; -- number of bits used between the stages
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g_stage_dat_w : natural := 18; -- number of bits used between the stages
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g_guard_w : natural := 2; -- guard bits are used to avoid overflow in single FFT stage.
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g_guard_w : natural := 2; -- guard bits are used to avoid overflow in single FFT stage.
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g_nof_points : natural := 1024; -- N point FFT
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g_nof_points : natural := 1024; -- N point FFT
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-- generics for rTwoSDFStage
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-- generics for rTwoSDFStage
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g_pipeline : t_fft_pipeline := c_fft_pipeline
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g_pipeline : t_fft_pipeline := c_fft_pipeline
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);
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic := '0';
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rst : in std_logic := '0';
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in_re : in std_logic_vector(g_in_dat_w-1 downto 0);
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in_re : in std_logic_vector(g_in_dat_w-1 downto 0);
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in_im : in std_logic_vector(g_in_dat_w-1 downto 0);
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in_im : in std_logic_vector(g_in_dat_w-1 downto 0);
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in_val : in std_logic := '1';
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in_val : in std_logic := '1';
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out_re : out std_logic_vector(g_out_dat_w-1 downto 0);
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out_re : out std_logic_vector(g_out_dat_w-1 downto 0);
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out_im : out std_logic_vector(g_out_dat_w-1 downto 0);
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out_im : out std_logic_vector(g_out_dat_w-1 downto 0);
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out_val : out std_logic
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out_val : out std_logic
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);
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);
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end entity rTwoSDF;
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end entity rTwoSDF;
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architecture str of rTwoSDF is
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architecture str of rTwoSDF is
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constant c_nof_stages : natural := ceil_log2(g_nof_points);
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constant c_nof_stages : natural := ceil_log2(g_nof_points);
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constant c_stage_offset : natural := 0; -- In "normal" pipelined fft operation the stage offset is 0
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constant c_stage_offset : natural := 0; -- In "normal" pipelined fft operation the stage offset is 0
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constant c_twiddle_offset : natural := 0; -- In "normal" pipelined fft operation the twiddle offset is 0
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constant c_twiddle_offset : natural := 0; -- In "normal" pipelined fft operation the twiddle offset is 0
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-- Round last stage output to g_out_dat_w if g_out_dat_w < g_stage_dat_w else resize to g_out_dat_w
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-- Round last stage output to g_out_dat_w if g_out_dat_w < g_stage_dat_w else resize to g_out_dat_w
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constant c_out_scale_w : integer := g_stage_dat_w - g_out_dat_w; -- Estimate number of LSBs to round throw away when > 0 or insert when < 0
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constant c_out_scale_w : integer := g_stage_dat_w - g_out_dat_w; -- Estimate number of LSBs to round throw away when > 0 or insert when < 0
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-- Scale the input to make optimal use of the g_stage_dat_w of the stages, using a margin of g_guard_w to account for factor > 2 gain of the first stage
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-- Scale the input to make optimal use of the g_stage_dat_w of the stages, using a margin of g_guard_w to account for factor > 2 gain of the first stage
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constant c_in_scale_w : natural := g_stage_dat_w - g_guard_w - g_in_dat_w; -- use type natural instead of integer to implicitly ensure that the g_stage_dat_w >= g_input_dat_w
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constant c_in_scale_w : natural := g_stage_dat_w - g_guard_w - g_in_dat_w; -- use type natural instead of integer to implicitly ensure that the g_stage_dat_w >= g_input_dat_w
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-- number the stage instances from c_nof_stages:1
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-- number the stage instances from c_nof_stages:1
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-- . the data input for the first stage has index c_nof_stages
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-- . the data input for the first stage has index c_nof_stages
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-- . the data output of the last stage has index 0
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-- . the data output of the last stage has index 0
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type t_data_arr is array(c_nof_stages downto 0) of std_logic_vector(g_stage_dat_w-1 downto 0);
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type t_data_arr is array(c_nof_stages downto 0) of std_logic_vector(g_stage_dat_w-1 downto 0);
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signal data_re : t_data_arr;
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signal data_re : t_data_arr;
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signal data_im : t_data_arr;
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signal data_im : t_data_arr;
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signal data_val : std_logic_vector(c_nof_stages downto 0):= (others=>'0');
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signal data_val : std_logic_vector(c_nof_stages downto 0):= (others=>'0');
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signal out_cplx : std_logic_vector(2*g_stage_dat_w-1 downto 0);
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signal out_cplx : std_logic_vector(2*g_stage_dat_w-1 downto 0);
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signal raw_out_cplx : std_logic_vector(2*g_stage_dat_w-1 downto 0);
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signal raw_out_cplx : std_logic_vector(2*g_stage_dat_w-1 downto 0);
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signal raw_out_re : std_logic_vector(g_stage_dat_w-1 downto 0);
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signal raw_out_re : std_logic_vector(g_stage_dat_w-1 downto 0);
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signal raw_out_im : std_logic_vector(g_stage_dat_w-1 downto 0);
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signal raw_out_im : std_logic_vector(g_stage_dat_w-1 downto 0);
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signal raw_out_val : std_logic;
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signal raw_out_val : std_logic;
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begin
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begin
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-- Inputs
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-- Inputs
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data_re( c_nof_stages) <= scale_and_resize_svec(in_re, c_in_scale_w, g_stage_dat_w);
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data_re( c_nof_stages) <= scale_and_resize_svec(in_re, c_in_scale_w, g_stage_dat_w);
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data_im( c_nof_stages) <= scale_and_resize_svec(in_im, c_in_scale_w, g_stage_dat_w);
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data_im( c_nof_stages) <= scale_and_resize_svec(in_im, c_in_scale_w, g_stage_dat_w);
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data_val(c_nof_stages) <= in_val;
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data_val(c_nof_stages) <= in_val;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- pipelined FFT stages
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-- pipelined FFT stages
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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gen_fft: for stage in c_nof_stages downto 1 generate
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gen_fft: for stage in c_nof_stages downto 1 generate
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u_stage : entity work.rTwoSDFStage
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u_stage : entity work.rTwoSDFStage
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generic map (
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generic map (
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g_nof_chan => g_nof_chan,
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g_nof_chan => g_nof_chan,
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g_stage => stage,
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g_stage => stage,
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g_stage_offset => c_stage_offset,
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g_stage_offset => c_stage_offset,
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g_twiddle_offset => c_twiddle_offset,
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g_twiddle_offset => c_twiddle_offset,
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g_scale_enable => sel_a_b(stage <= g_guard_w, FALSE, TRUE), -- On average all stages have a gain factor of 2 therefore each stage needs to round 1 bit except for the last g_guard_w nof stages due to the input c_in_scale_w
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g_scale_enable => sel_a_b(stage <= g_guard_w, FALSE, TRUE), -- On average all stages have a gain factor of 2 therefore each stage needs to round 1 bit except for the last g_guard_w nof stages due to the input c_in_scale_w
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g_pipeline => g_pipeline
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g_pipeline => g_pipeline
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)
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)
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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in_re => data_re(stage),
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in_re => data_re(stage),
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in_im => data_im(stage),
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in_im => data_im(stage),
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in_val => data_val(stage),
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in_val => data_val(stage),
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out_re => data_re(stage-1),
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out_re => data_re(stage-1),
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out_im => data_im(stage-1),
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out_im => data_im(stage-1),
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out_val => data_val(stage-1)
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out_val => data_val(stage-1)
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);
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);
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end generate;
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end generate;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Optional output reorder
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-- Optional output reorder
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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no_reorder : if g_use_reorder=false generate
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no_reorder : if g_use_reorder=false generate
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raw_out_re <= data_re(0);
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raw_out_re <= data_re(0);
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raw_out_im <= data_im(0);
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raw_out_im <= data_im(0);
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raw_out_val <= data_val(0);
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raw_out_val <= data_val(0);
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end generate;
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end generate;
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gen_reorder : if g_use_reorder=true generate
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gen_reorder : if g_use_reorder=true generate
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raw_out_cplx <= data_im(0) & data_re(0);
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raw_out_cplx <= data_im(0) & data_re(0);
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raw_out_re <= out_cplx( g_stage_dat_w-1 downto 0);
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raw_out_re <= out_cplx( g_stage_dat_w-1 downto 0);
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raw_out_im <= out_cplx(2*g_stage_dat_w-1 downto g_stage_dat_w);
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raw_out_im <= out_cplx(2*g_stage_dat_w-1 downto g_stage_dat_w);
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u_cplx: entity work.rTwoOrder
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u_cplx: entity work.rTwoOrder
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generic map (
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generic map (
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g_nof_points => g_nof_points,
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g_nof_points => g_nof_points,
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g_nof_chan => g_nof_chan
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g_nof_chan => g_nof_chan
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)
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)
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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in_dat => raw_out_cplx,
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in_dat => raw_out_cplx,
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in_val => data_val(0),
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in_val => data_val(0),
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out_dat => out_cplx,
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out_dat => out_cplx,
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out_val => raw_out_val
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out_val => raw_out_val
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);
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);
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end generate;
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end generate;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- pipelined FFT output requantization
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-- pipelined FFT output requantization
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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u_requantize_re : entity common_requantize_lib.common_requantize
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u_requantize_re : entity astron_requantize_lib.common_requantize
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generic map (
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generic map (
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g_representation => "SIGNED",
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g_representation => "SIGNED",
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g_lsb_w => c_out_scale_w,
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g_lsb_w => c_out_scale_w,
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g_lsb_round => TRUE,
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g_lsb_round => TRUE,
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g_lsb_round_clip => FALSE,
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g_lsb_round_clip => FALSE,
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g_msb_clip => FALSE,
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g_msb_clip => FALSE,
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g_msb_clip_symmetric => FALSE,
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g_msb_clip_symmetric => FALSE,
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g_pipeline_remove_lsb => 0,
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g_pipeline_remove_lsb => 0,
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g_pipeline_remove_msb => 0,
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g_pipeline_remove_msb => 0,
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g_in_dat_w => g_stage_dat_w,
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g_in_dat_w => g_stage_dat_w,
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g_out_dat_w => g_out_dat_w
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g_out_dat_w => g_out_dat_w
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)
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)
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port map (
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port map (
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clk => clk,
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clk => clk,
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clken => '1',
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clken => '1',
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in_dat => raw_out_re,
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in_dat => raw_out_re,
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out_dat => out_re,
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out_dat => out_re,
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out_ovr => open
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out_ovr => open
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);
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);
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u_requantize_im : entity common_requantize_lib.common_requantize
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u_requantize_im : entity astron_requantize_lib.common_requantize
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generic map (
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generic map (
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g_representation => "SIGNED",
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g_representation => "SIGNED",
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g_lsb_w => c_out_scale_w,
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g_lsb_w => c_out_scale_w,
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g_lsb_round => TRUE,
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g_lsb_round => TRUE,
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g_lsb_round_clip => FALSE,
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g_lsb_round_clip => FALSE,
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g_msb_clip => FALSE,
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g_msb_clip => FALSE,
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g_msb_clip_symmetric => FALSE,
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g_msb_clip_symmetric => FALSE,
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g_pipeline_remove_lsb => 0,
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g_pipeline_remove_lsb => 0,
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g_pipeline_remove_msb => 0,
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g_pipeline_remove_msb => 0,
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g_in_dat_w => g_stage_dat_w,
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g_in_dat_w => g_stage_dat_w,
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g_out_dat_w => g_out_dat_w
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g_out_dat_w => g_out_dat_w
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)
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)
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port map (
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port map (
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clk => clk,
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clk => clk,
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clken => '1',
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clken => '1',
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in_dat => raw_out_im,
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in_dat => raw_out_im,
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out_dat => out_im,
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out_dat => out_im,
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out_ovr => open
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out_ovr => open
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);
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);
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-- Valid Output
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-- Valid Output
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out_val <= raw_out_val;
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out_val <= raw_out_val;
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end str;
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end str;
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