-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright 2020
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- You may obtain a copy of the License at
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--
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY IEEE, technology_lib;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE work.common_ram_pkg.ALL;
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USE work.common_ram_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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--USE technology_lib.technology_select_pkg.ALL;
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ENTITY common_ram_r_w IS
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ENTITY common_ram_r_w IS
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GENERIC (
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GENERIC (
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g_technology : NATURAL := c_tech_select_default;
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g_technology : NATURAL := 0;
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g_ram : t_c_mem := c_mem_ram;
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g_ram : t_c_mem := c_mem_ram;
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g_init_file : STRING := "UNUSED";
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g_init_file : STRING := "UNUSED";
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g_true_dual_port : BOOLEAN := TRUE
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g_true_dual_port : BOOLEAN := TRUE
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);
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);
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PORT (
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PORT (
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rst : IN STD_LOGIC := '0';
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rst : IN STD_LOGIC := '0';
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clk : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clken : IN STD_LOGIC := '1';
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clken : IN STD_LOGIC := '1';
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wr_en : IN STD_LOGIC := '0';
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wr_en : IN STD_LOGIC := '0';
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wr_adr : IN STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0');
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wr_adr : IN STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0');
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wr_dat : IN STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
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wr_dat : IN STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
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rd_en : IN STD_LOGIC := '1';
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rd_en : IN STD_LOGIC := '1';
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rd_adr : IN STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0);
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rd_adr : IN STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0);
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rd_dat : OUT STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0);
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rd_dat : OUT STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0);
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rd_val : OUT STD_LOGIC
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rd_val : OUT STD_LOGIC
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);
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);
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END common_ram_r_w;
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END common_ram_r_w;
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ARCHITECTURE str OF common_ram_r_w IS
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ARCHITECTURE str OF common_ram_r_w IS
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BEGIN
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BEGIN
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-- Use port a only for write
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-- Use port a only for write
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-- Use port b only for read
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-- Use port b only for read
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u_rw_rw : ENTITY work.common_ram_rw_rw
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u_rw_rw : ENTITY work.common_ram_rw_rw
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GENERIC MAP (
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GENERIC MAP (
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g_technology => g_technology,
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g_technology => g_technology,
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g_ram => g_ram,
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g_ram => g_ram,
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g_init_file => g_init_file,
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g_init_file => g_init_file,
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g_true_dual_port => g_true_dual_port
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g_true_dual_port => g_true_dual_port
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)
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)
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PORT MAP (
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PORT MAP (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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clken => clken,
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clken => clken,
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wr_en_a => wr_en,
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wr_en_a => wr_en,
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wr_en_b => '0',
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wr_en_b => '0',
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wr_dat_a => wr_dat,
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wr_dat_a => wr_dat,
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--wr_dat_b => (OTHERS=>'0'),
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--wr_dat_b => (OTHERS=>'0'),
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adr_a => wr_adr,
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adr_a => wr_adr,
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adr_b => rd_adr,
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adr_b => rd_adr,
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rd_en_a => '0',
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rd_en_a => '0',
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rd_en_b => rd_en,
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rd_en_b => rd_en,
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rd_dat_a => OPEN,
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rd_dat_a => OPEN,
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rd_dat_b => rd_dat,
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rd_dat_b => rd_dat,
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rd_val_a => OPEN,
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rd_val_a => OPEN,
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rd_val_b => rd_val
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rd_val_b => rd_val
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);
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);
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END str;
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END str;
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