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URL https://opencores.org/ocsvn/astron_ram/astron_ram/trunk

Subversion Repositories astron_ram

[/] [astron_ram/] [trunk/] [ip_stratixiv_ram_crw_crw.vhd] - Diff between revs 2 and 4

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Rev 2 Rev 4 
-- megafunction wizard: %RAM: 2-PORT%
 
-- megafunction wizard: %RAM: 2-PORT%
 
-- GENERATION: STANDARD
 
-- GENERATION: STANDARD
 
-- VERSION: WM1.0
 
-- VERSION: WM1.0
 
-- MODULE: altsyncram 
-- MODULE: altsyncram 
 
 
 
 
-- ============================================================
 
-- ============================================================
 
-- File Name: ip_stratixiv_ram_crw_crw.vhd
 
-- File Name: ip_stratixiv_ram_crw_crw.vhd
 
-- Megafunction Name(s):
 
-- Megafunction Name(s):
 
--                      altsyncram
 
--                      altsyncram
 
--
 
--
 
-- Simulation Library Files(s):
 
-- Simulation Library Files(s):
 
--                      altera_mf
 
--                      altera_mf
 
-- ============================================================
 
-- ============================================================
 
-- ************************************************************
 
-- ************************************************************
 
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 
--
 
--
 
-- 10.0 Build 218 06/27/2010 SJ Full Version
 
-- 10.0 Build 218 06/27/2010 SJ Full Version
 
-- ************************************************************
 
-- ************************************************************
 
 
 
 
 
 
 
 
 
--Copyright (C) 1991-2010 Altera Corporation
 
--Copyright (C) 1991-2010 Altera Corporation
 
--Your use of Altera Corporation's design tools, logic functions 
--Your use of Altera Corporation's design tools, logic functions 
--and other software and tools, and its AMPP partner logic 
--and other software and tools, and its AMPP partner logic 
--functions, and any output files from any of the foregoing 
--functions, and any output files from any of the foregoing 
--(including device programming or simulation files), and any 
--(including device programming or simulation files), and any 
--associated documentation or information are expressly subject 
--associated documentation or information are expressly subject 
--to the terms and conditions of the Altera Program License 
--to the terms and conditions of the Altera Program License 
--Subscription Agreement, Altera MegaCore Function License 
--Subscription Agreement, Altera MegaCore Function License 
--Agreement, or other applicable license agreement, including, 
--Agreement, or other applicable license agreement, including, 
--without limitation, that your use is for the sole purpose of 
--without limitation, that your use is for the sole purpose of 
--programming logic devices manufactured by Altera and sold by 
--programming logic devices manufactured by Altera and sold by 
--Altera or its authorized distributors.  Please refer to the 
--Altera or its authorized distributors.  Please refer to the 
--applicable agreement for further details.
 
--applicable agreement for further details.
 
 
 
 
 
 
 
 
 
LIBRARY ieee;
 
LIBRARY ieee, common_pkg_lib;
 
USE ieee.std_logic_1164.all;
 
USE ieee.std_logic_1164.all;
 
 
 
USE common_pkg_lib.common_pkg.ALL;
 
 
 
 
 
LIBRARY altera_mf;
 
LIBRARY altera_mf;
 
USE altera_mf.all;
 
USE altera_mf.all;
 
 
 
 
 
LIBRARY technology_lib;
 
--LIBRARY technology_lib;
 
USE technology_lib.technology_pkg.ALL;
 
--USE technology_lib.technology_pkg.ALL;
 
 
 
 
 
ENTITY ip_stratixiv_ram_crw_crw IS
 
ENTITY ip_stratixiv_ram_crw_crw IS
 
  GENERIC (
 
  GENERIC (
 
    g_adr_w      : NATURAL := 5;
 
    g_adr_w      : NATURAL := 5;
 
    g_dat_w      : NATURAL := 8;
 
    g_dat_w      : NATURAL := 8;
 
    g_nof_words  : NATURAL := 2**5;
 
    g_nof_words  : NATURAL := 2**5;
 
    g_rd_latency : NATURAL := 2;  -- choose 1 or 2
 
    g_rd_latency : NATURAL := 2;  -- choose 1 or 2
 
    g_init_file  : STRING  := "UNUSED"
 
    g_init_file  : STRING  := "UNUSED"
 
  );
 
  );
 
        PORT
 
        PORT
 
        (
 
        (
 
                address_a               : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
 
                address_a               : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
 
                address_b               : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
 
                address_b               : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
 
                clock_a         : IN STD_LOGIC  := '1';
 
                clock_a         : IN STD_LOGIC  := '1';
 
                clock_b         : IN STD_LOGIC ;
 
                clock_b         : IN STD_LOGIC ;
 
                data_a          : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
                data_a          : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
                data_b          : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
                data_b          : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
                enable_a                : IN STD_LOGIC  := '1';
 
                enable_a                : IN STD_LOGIC  := '1';
 
                enable_b                : IN STD_LOGIC  := '1';
 
                enable_b                : IN STD_LOGIC  := '1';
 
                rden_a          : IN STD_LOGIC  := '1';
 
                rden_a          : IN STD_LOGIC  := '1';
 
                rden_b          : IN STD_LOGIC  := '1';
 
                rden_b          : IN STD_LOGIC  := '1';
 
                wren_a          : IN STD_LOGIC  := '0';
 
                wren_a          : IN STD_LOGIC  := '0';
 
                wren_b          : IN STD_LOGIC  := '0';
 
                wren_b          : IN STD_LOGIC  := '0';
 
                q_a             : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
                q_a             : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
                q_b             : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
 
                q_b             : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
 
        );
 
        );
 
END ip_stratixiv_ram_crw_crw;
 
END ip_stratixiv_ram_crw_crw;
 
 
 
 
 
 
 
 
 
ARCHITECTURE SYN OF ip_stratixiv_ram_crw_crw IS
 
ARCHITECTURE SYN OF ip_stratixiv_ram_crw_crw IS
 
 
 
 
 
  CONSTANT c_outdata_reg_a : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK0");
 
  CONSTANT c_outdata_reg_a : STRING := sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK0");
 
  CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
 
  CONSTANT c_outdata_reg_b : STRING := sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
 
 
 
 
 
        SIGNAL sub_wire0        : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
        SIGNAL sub_wire0        : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
        SIGNAL sub_wire1        : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
        SIGNAL sub_wire1        : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
 
 
 
 
 
 
 
 
 
 
 
 
        COMPONENT altsyncram
 
        COMPONENT altsyncram
 
        GENERIC (
 
        GENERIC (
 
                address_reg_b           : STRING;
 
                address_reg_b           : STRING;
 
                clock_enable_input_a            : STRING;
 
                clock_enable_input_a            : STRING;
 
                clock_enable_input_b            : STRING;
 
                clock_enable_input_b            : STRING;
 
                clock_enable_output_a           : STRING;
 
                clock_enable_output_a           : STRING;
 
                clock_enable_output_b           : STRING;
 
                clock_enable_output_b           : STRING;
 
                indata_reg_b            : STRING;
 
                indata_reg_b            : STRING;
 
                init_file               : STRING;
 
                init_file               : STRING;
 
                intended_device_family          : STRING;
 
                intended_device_family          : STRING;
 
                lpm_type                : STRING;
 
                lpm_type                : STRING;
 
                numwords_a              : NATURAL;
 
                numwords_a              : NATURAL;
 
                numwords_b              : NATURAL;
 
                numwords_b              : NATURAL;
 
                operation_mode          : STRING;
 
                operation_mode          : STRING;
 
                outdata_aclr_a          : STRING;
 
                outdata_aclr_a          : STRING;
 
                outdata_aclr_b          : STRING;
 
                outdata_aclr_b          : STRING;
 
                outdata_reg_a           : STRING;
 
                outdata_reg_a           : STRING;
 
                outdata_reg_b           : STRING;
 
                outdata_reg_b           : STRING;
 
                power_up_uninitialized          : STRING;
 
                power_up_uninitialized          : STRING;
 
                read_during_write_mode_port_a           : STRING;
 
                read_during_write_mode_port_a           : STRING;
 
                read_during_write_mode_port_b           : STRING;
 
                read_during_write_mode_port_b           : STRING;
 
                widthad_a               : NATURAL;
 
                widthad_a               : NATURAL;
 
                widthad_b               : NATURAL;
 
                widthad_b               : NATURAL;
 
                width_a         : NATURAL;
 
                width_a         : NATURAL;
 
                width_b         : NATURAL;
 
                width_b         : NATURAL;
 
                width_byteena_a         : NATURAL;
 
                width_byteena_a         : NATURAL;
 
                width_byteena_b         : NATURAL;
 
                width_byteena_b         : NATURAL;
 
                wrcontrol_wraddress_reg_b               : STRING
 
                wrcontrol_wraddress_reg_b               : STRING
 
        );
 
        );
 
        PORT (
 
        PORT (
 
                        clocken0        : IN STD_LOGIC ;
 
                        clocken0        : IN STD_LOGIC ;
 
                        clocken1        : IN STD_LOGIC ;
 
                        clocken1        : IN STD_LOGIC ;
 
                        wren_a  : IN STD_LOGIC ;
 
                        wren_a  : IN STD_LOGIC ;
 
                        rden_a  : IN STD_LOGIC ;
 
                        rden_a  : IN STD_LOGIC ;
 
                        clock0  : IN STD_LOGIC ;
 
                        clock0  : IN STD_LOGIC ;
 
                        wren_b  : IN STD_LOGIC ;
 
                        wren_b  : IN STD_LOGIC ;
 
                        rden_b  : IN STD_LOGIC ;
 
                        rden_b  : IN STD_LOGIC ;
 
                        clock1  : IN STD_LOGIC ;
 
                        clock1  : IN STD_LOGIC ;
 
                        address_a       : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
 
                        address_a       : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
 
                        address_b       : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
 
                        address_b       : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
 
                        q_a     : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
                        q_a     : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
                        q_b     : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
                        q_b     : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
                        data_a  : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
                        data_a  : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
                        data_b  : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
 
                        data_b  : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
 
        );
 
        );
 
        END COMPONENT;
 
        END COMPONENT;
 
 
 
 
 
BEGIN
 
BEGIN
 
        q_a    <= sub_wire0(g_dat_w-1 DOWNTO 0);
 
        q_a    <= sub_wire0(g_dat_w-1 DOWNTO 0);
 
        q_b    <= sub_wire1(g_dat_w-1 DOWNTO 0);
 
        q_b    <= sub_wire1(g_dat_w-1 DOWNTO 0);
 
 
 
 
 
        altsyncram_component : altsyncram
 
        altsyncram_component : altsyncram
 
        GENERIC MAP (
 
        GENERIC MAP (
 
                address_reg_b => "CLOCK1",
 
                address_reg_b => "CLOCK1",
 
                clock_enable_input_a => "NORMAL",
 
                clock_enable_input_a => "NORMAL",
 
                clock_enable_input_b => "NORMAL",
 
                clock_enable_input_b => "NORMAL",
 
                clock_enable_output_a => "BYPASS",
 
                clock_enable_output_a => "BYPASS",
 
                clock_enable_output_b => "BYPASS",
 
                clock_enable_output_b => "BYPASS",
 
                indata_reg_b => "CLOCK1",
 
                indata_reg_b => "CLOCK1",
 
                init_file => g_init_file,
 
                init_file => g_init_file,
 
                intended_device_family => "Stratix IV",
 
                intended_device_family => "Stratix IV",
 
                lpm_type => "altsyncram",
 
                lpm_type => "altsyncram",
 
                numwords_a => g_nof_words,
 
                numwords_a => g_nof_words,
 
                numwords_b => g_nof_words,
 
                numwords_b => g_nof_words,
 
                operation_mode => "BIDIR_DUAL_PORT",
 
                operation_mode => "BIDIR_DUAL_PORT",
 
                outdata_aclr_a => "NONE",
 
                outdata_aclr_a => "NONE",
 
                outdata_aclr_b => "NONE",
 
                outdata_aclr_b => "NONE",
 
                outdata_reg_a => c_outdata_reg_a,
 
                outdata_reg_a => c_outdata_reg_a,
 
                outdata_reg_b => c_outdata_reg_b,
 
                outdata_reg_b => c_outdata_reg_b,
 
                power_up_uninitialized => "FALSE",
 
                power_up_uninitialized => "FALSE",
 
                read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
 
                read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
 
                read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
 
                read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
 
                widthad_a => g_adr_w,
 
                widthad_a => g_adr_w,
 
                widthad_b => g_adr_w,
 
                widthad_b => g_adr_w,
 
                width_a => g_dat_w,
 
                width_a => g_dat_w,
 
                width_b => g_dat_w,
 
                width_b => g_dat_w,
 
                width_byteena_a => 1,
 
                width_byteena_a => 1,
 
                width_byteena_b => 1,
 
                width_byteena_b => 1,
 
                wrcontrol_wraddress_reg_b => "CLOCK1"
 
                wrcontrol_wraddress_reg_b => "CLOCK1"
 
        )
 
        )
 
        PORT MAP (
 
        PORT MAP (
 
                clocken0 => enable_a,
 
                clocken0 => enable_a,
 
                clocken1 => enable_b,
 
                clocken1 => enable_b,
 
                wren_a => wren_a,
 
                wren_a => wren_a,
 
                rden_a => rden_a,
 
                rden_a => rden_a,
 
                clock0 => clock_a,
 
                clock0 => clock_a,
 
                wren_b => wren_b,
 
                wren_b => wren_b,
 
                rden_b => rden_b,
 
                rden_b => rden_b,
 
                clock1 => clock_b,
 
                clock1 => clock_b,
 
                address_a => address_a,
 
                address_a => address_a,
 
                address_b => address_b,
 
                address_b => address_b,
 
                data_a => data_a,
 
                data_a => data_a,
 
                data_b => data_b,
 
                data_b => data_b,
 
                q_a => sub_wire0,
 
                q_a => sub_wire0,
 
                q_b => sub_wire1
 
                q_b => sub_wire1
 
        );
 
        );
 
 
 
 
 
 
 
 
 
 
 
 
 
END SYN;
 
END SYN;
 
 
 
 
 
-- ============================================================
 
-- ============================================================
 
-- CNX file retrieval info
 
-- CNX file retrieval info
 
-- ============================================================
 
-- ============================================================
 
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
 
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
 
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
 
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
 
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
 
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
 
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
 
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
 
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
 
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
 
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
 
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
 
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
 
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
 
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
 
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
 
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
 
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
 
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
 
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
 
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
 
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
 
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
 
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
 
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
 
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
 
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
 
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
 
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
 
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
 
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
 
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
 
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
 
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
 
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
 
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
 
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
 
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
 
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
 
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
 
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
 
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
 
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
 
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
 
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
 
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
 
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
 
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
 
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
 
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
 
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
 
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
 
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "576"
 
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "576"
 
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
 
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
 
-- Retrieval info: PRIVATE: MIFfilename STRING "fft_3n1024sin.hex"
 
-- Retrieval info: PRIVATE: MIFfilename STRING "fft_3n1024sin.hex"
 
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
 
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
 
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
 
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
 
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
 
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
 
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
 
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
 
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
 
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
 
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
 
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
 
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
 
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
 
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
 
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
 
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
 
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
 
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
 
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
 
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
 
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
 
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
 
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
 
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
 
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
 
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "18"
 
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "18"
 
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "18"
 
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "18"
 
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "18"
 
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "18"
 
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "18"
 
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "18"
 
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
 
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
 
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
 
-- Retrieval info: PRIVATE: enable NUMERIC "1"
 
-- Retrieval info: PRIVATE: enable NUMERIC "1"
 
-- Retrieval info: PRIVATE: rden NUMERIC "1"
 
-- Retrieval info: PRIVATE: rden NUMERIC "1"
 
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
 
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
 
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
 
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
 
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
 
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
 
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
 
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
 
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
 
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
 
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
 
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
 
-- Retrieval info: CONSTANT: INIT_FILE STRING "fft_3n1024sin.hex"
 
-- Retrieval info: CONSTANT: INIT_FILE STRING "fft_3n1024sin.hex"
 
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
 
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
 
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
 
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
 
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
 
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
 
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
 
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
 
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
 
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
 
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
 
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
 
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
 
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
 
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
 
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
 
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
 
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
 
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
 
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
 
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
 
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
 
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
 
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
 
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
 
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
 
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
 
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
 
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
 
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
 
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
 
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
 
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
 
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
 
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
 
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
 
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
 
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
 
-- Retrieval info: USED_PORT: address_a 0 0 5 0 INPUT NODEFVAL "address_a[4..0]"
 
-- Retrieval info: USED_PORT: address_a 0 0 5 0 INPUT NODEFVAL "address_a[4..0]"
 
-- Retrieval info: USED_PORT: address_b 0 0 5 0 INPUT NODEFVAL "address_b[4..0]"
 
-- Retrieval info: USED_PORT: address_b 0 0 5 0 INPUT NODEFVAL "address_b[4..0]"
 
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
 
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
 
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
 
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
 
-- Retrieval info: USED_PORT: data_a 0 0 18 0 INPUT NODEFVAL "data_a[17..0]"
 
-- Retrieval info: USED_PORT: data_a 0 0 18 0 INPUT NODEFVAL "data_a[17..0]"
 
-- Retrieval info: USED_PORT: data_b 0 0 18 0 INPUT NODEFVAL "data_b[17..0]"
 
-- Retrieval info: USED_PORT: data_b 0 0 18 0 INPUT NODEFVAL "data_b[17..0]"
 
-- Retrieval info: USED_PORT: enable_a 0 0 0 0 INPUT VCC "enable_a"
 
-- Retrieval info: USED_PORT: enable_a 0 0 0 0 INPUT VCC "enable_a"
 
-- Retrieval info: USED_PORT: enable_b 0 0 0 0 INPUT VCC "enable_b"
 
-- Retrieval info: USED_PORT: enable_b 0 0 0 0 INPUT VCC "enable_b"
 
-- Retrieval info: USED_PORT: q_a 0 0 18 0 OUTPUT NODEFVAL "q_a[17..0]"
 
-- Retrieval info: USED_PORT: q_a 0 0 18 0 OUTPUT NODEFVAL "q_a[17..0]"
 
-- Retrieval info: USED_PORT: q_b 0 0 18 0 OUTPUT NODEFVAL "q_b[17..0]"
 
-- Retrieval info: USED_PORT: q_b 0 0 18 0 OUTPUT NODEFVAL "q_b[17..0]"
 
-- Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a"
 
-- Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a"
 
-- Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b"
 
-- Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b"
 
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
 
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
 
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
 
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
 
-- Retrieval info: CONNECT: @address_a 0 0 5 0 address_a 0 0 5 0
 
-- Retrieval info: CONNECT: @address_a 0 0 5 0 address_a 0 0 5 0
 
-- Retrieval info: CONNECT: @address_b 0 0 5 0 address_b 0 0 5 0
 
-- Retrieval info: CONNECT: @address_b 0 0 5 0 address_b 0 0 5 0
 
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
 
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
 
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
 
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
 
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable_a 0 0 0 0
 
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable_a 0 0 0 0
 
-- Retrieval info: CONNECT: @clocken1 0 0 0 0 enable_b 0 0 0 0
 
-- Retrieval info: CONNECT: @clocken1 0 0 0 0 enable_b 0 0 0 0
 
-- Retrieval info: CONNECT: @data_a 0 0 18 0 data_a 0 0 18 0
 
-- Retrieval info: CONNECT: @data_a 0 0 18 0 data_a 0 0 18 0
 
-- Retrieval info: CONNECT: @data_b 0 0 18 0 data_b 0 0 18 0
 
-- Retrieval info: CONNECT: @data_b 0 0 18 0 data_b 0 0 18 0
 
-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0
 
-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0
 
-- Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0
 
-- Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0
 
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
 
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
 
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
 
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
 
-- Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0
 
-- Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0
 
-- Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0
 
-- Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0
 
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw.vhd TRUE
 
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw.vhd TRUE
 
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw.inc FALSE
 
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw.inc FALSE
 
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw.cmp TRUE
 
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw.cmp TRUE
 
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw.bsf FALSE
 
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw.bsf FALSE
 
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw_inst.vhd FALSE
 
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw_inst.vhd FALSE
 
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw_waveforms.html TRUE
 
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw_waveforms.html TRUE
 
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw_wave*.jpg FALSE
 
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw_wave*.jpg FALSE
 
-- Retrieval info: LIB_FILE: altera_mf
 
-- Retrieval info: LIB_FILE: altera_mf
 
 
 
 

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