-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- Copyright (C) 2010
|
-- Copyright 2020
|
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
|
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
|
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
|
|
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
|
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
|
--
|
--
|
-- This program is free software: you can redistribute it and/or modify
|
-- Licensed under the Apache License, Version 2.0 (the "License");
|
-- it under the terms of the GNU General Public License as published by
|
-- you may not use this file except in compliance with the License.
|
-- the Free Software Foundation, either version 3 of the License, or
|
-- You may obtain a copy of the License at
|
-- (at your option) any later version.
|
|
--
|
--
|
-- This program is distributed in the hope that it will be useful,
|
-- http://www.apache.org/licenses/LICENSE-2.0
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
-- GNU General Public License for more details.
|
|
--
|
--
|
-- You should have received a copy of the GNU General Public License
|
-- Unless required by applicable law or agreed to in writing, software
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
-- distributed under the License is distributed on an "AS IS" BASIS,
|
|
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
-- See the License for the specific language governing permissions and
|
|
-- limitations under the License.
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
LIBRARY IEEE, common_pkg_lib;
|
LIBRARY IEEE, common_pkg_lib;
|
USE IEEE.std_logic_1164.ALL;
|
USE IEEE.std_logic_1164.ALL;
|
USE IEEE.numeric_std.ALL;
|
USE IEEE.numeric_std.ALL;
|
USE common_pkg_lib.common_pkg.ALL;
|
USE common_pkg_lib.common_pkg.ALL;
|
USE common_pkg_lib.tb_common_pkg.ALL;
|
USE common_pkg_lib.tb_common_pkg.ALL;
|
|
|
-- Purpose: Test bench for common_paged_ram_crw_crw
|
-- Purpose: Test bench for common_paged_ram_crw_crw
|
--
|
--
|
-- Features:
|
-- Features:
|
-- . Use c_gap_sz = 0 to try writing and reading multiple page without idle
|
-- . Use c_gap_sz = 0 to try writing and reading multiple page without idle
|
-- cycles
|
-- cycles
|
-- . Most applications use c_nof_pages = 2, but use > 2 is supported too.
|
-- . Most applications use c_nof_pages = 2, but use > 2 is supported too.
|
--
|
--
|
-- Usage:
|
-- Usage:
|
-- > as 10
|
-- > as 10
|
-- > run -all
|
-- > run -all
|
|
|
|
|
ENTITY tb_common_paged_ram_crw_crw IS
|
ENTITY tb_common_paged_ram_crw_crw IS
|
END tb_common_paged_ram_crw_crw;
|
END tb_common_paged_ram_crw_crw;
|
|
|
ARCHITECTURE tb OF tb_common_paged_ram_crw_crw IS
|
ARCHITECTURE tb OF tb_common_paged_ram_crw_crw IS
|
|
|
CONSTANT clk_period : TIME := 10 ns;
|
CONSTANT clk_period : TIME := 10 ns;
|
|
|
CONSTANT c_data_w : NATURAL := 8;
|
CONSTANT c_data_w : NATURAL := 8;
|
CONSTANT c_nof_pages : NATURAL := 2; -- >= 2
|
CONSTANT c_nof_pages : NATURAL := 2; -- >= 2
|
CONSTANT c_page_sz : NATURAL := 8;
|
CONSTANT c_page_sz : NATURAL := 8;
|
CONSTANT c_start_page_a : NATURAL := 0;
|
CONSTANT c_start_page_a : NATURAL := 0;
|
CONSTANT c_start_page_b : NATURAL := 1;
|
CONSTANT c_start_page_b : NATURAL := 1;
|
CONSTANT c_gap_sz : NATURAL := 0; -- >= 0
|
CONSTANT c_gap_sz : NATURAL := 0; -- >= 0
|
CONSTANT c_rl : NATURAL := 1;
|
CONSTANT c_rl : NATURAL := 1;
|
|
|
SIGNAL rst : STD_LOGIC;
|
SIGNAL rst : STD_LOGIC;
|
SIGNAL clk : STD_LOGIC := '1';
|
SIGNAL clk : STD_LOGIC := '1';
|
SIGNAL tb_end : STD_LOGIC := '0';
|
SIGNAL tb_end : STD_LOGIC := '0';
|
|
|
-- DUT
|
-- DUT
|
SIGNAL next_page : STD_LOGIC;
|
SIGNAL next_page : STD_LOGIC;
|
|
|
SIGNAL next_page_a : STD_LOGIC;
|
SIGNAL next_page_a : STD_LOGIC;
|
SIGNAL adr_a : STD_LOGIC_VECTOR(ceil_log2(c_page_sz)-1 DOWNTO 0) := (OTHERS=>'0');
|
SIGNAL adr_a : STD_LOGIC_VECTOR(ceil_log2(c_page_sz)-1 DOWNTO 0) := (OTHERS=>'0');
|
SIGNAL wr_en_a : STD_LOGIC;
|
SIGNAL wr_en_a : STD_LOGIC;
|
SIGNAL wr_dat_a : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0) := (OTHERS=>'0');
|
SIGNAL wr_dat_a : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0) := (OTHERS=>'0');
|
|
|
SIGNAL next_page_b : STD_LOGIC;
|
SIGNAL next_page_b : STD_LOGIC;
|
SIGNAL adr_b : STD_LOGIC_VECTOR(ceil_log2(c_page_sz)-1 DOWNTO 0) := (OTHERS=>'0');
|
SIGNAL adr_b : STD_LOGIC_VECTOR(ceil_log2(c_page_sz)-1 DOWNTO 0) := (OTHERS=>'0');
|
SIGNAL rd_en_b : STD_LOGIC := '0';
|
SIGNAL rd_en_b : STD_LOGIC := '0';
|
|
|
SIGNAL mux_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
|
SIGNAL mux_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
|
SIGNAL mux_rd_val_b : STD_LOGIC;
|
SIGNAL mux_rd_val_b : STD_LOGIC;
|
|
|
SIGNAL adr_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
|
SIGNAL adr_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
|
SIGNAL adr_rd_val_b : STD_LOGIC;
|
SIGNAL adr_rd_val_b : STD_LOGIC;
|
|
|
SIGNAL ofs_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
|
SIGNAL ofs_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
|
SIGNAL ofs_rd_val_b : STD_LOGIC;
|
SIGNAL ofs_rd_val_b : STD_LOGIC;
|
|
|
-- Verify
|
-- Verify
|
SIGNAL verify_en : STD_LOGIC;
|
SIGNAL verify_en : STD_LOGIC;
|
SIGNAL ready : STD_LOGIC := '1';
|
SIGNAL ready : STD_LOGIC := '1';
|
|
|
SIGNAL prev_mux_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
|
SIGNAL prev_mux_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
|
SIGNAL prev_adr_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
|
SIGNAL prev_adr_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
|
SIGNAL prev_ofs_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
|
SIGNAL prev_ofs_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
|
|
|
BEGIN
|
BEGIN
|
|
|
clk <= NOT clk AND NOT tb_end AFTER clk_period/2;
|
clk <= NOT clk AND NOT tb_end AFTER clk_period/2;
|
rst <= '1', '0' AFTER clk_period*7;
|
rst <= '1', '0' AFTER clk_period*7;
|
|
|
verify_en <= '0', '1' AFTER clk_period*(15+(c_nof_pages-1)*c_page_sz);
|
verify_en <= '0', '1' AFTER clk_period*(15+(c_nof_pages-1)*c_page_sz);
|
|
|
-- Apply stimuli via port 'a', do write 'a' and read 'b', and derive the 'b' stimuli from the 'a' stimuli with 1 clock cycle latency
|
-- Apply stimuli via port 'a', do write 'a' and read 'b', and derive the 'b' stimuli from the 'a' stimuli with 1 clock cycle latency
|
next_page_a <= next_page;
|
next_page_a <= next_page;
|
next_page_b <= next_page WHEN rising_edge(clk);
|
next_page_b <= next_page WHEN rising_edge(clk);
|
|
|
wr_dat_a <= INCR_UVEC(wr_dat_a, 1) WHEN rising_edge(clk) AND wr_en_a='1';
|
wr_dat_a <= INCR_UVEC(wr_dat_a, 1) WHEN rising_edge(clk) AND wr_en_a='1';
|
adr_a <= INCR_UVEC( adr_a, 1) WHEN rising_edge(clk) AND wr_en_a='1';
|
adr_a <= INCR_UVEC( adr_a, 1) WHEN rising_edge(clk) AND wr_en_a='1';
|
adr_b <= adr_a WHEN rising_edge(clk);
|
adr_b <= adr_a WHEN rising_edge(clk);
|
rd_en_b <= wr_en_a WHEN rising_edge(clk);
|
rd_en_b <= wr_en_a WHEN rising_edge(clk);
|
|
|
p_stimuli : PROCESS
|
p_stimuli : PROCESS
|
BEGIN
|
BEGIN
|
next_page <= '0';
|
next_page <= '0';
|
wr_en_a <= '0';
|
wr_en_a <= '0';
|
proc_common_wait_until_low(clk, rst);
|
proc_common_wait_until_low(clk, rst);
|
proc_common_wait_some_cycles(clk, 3);
|
proc_common_wait_some_cycles(clk, 3);
|
|
|
-- Access the pages several times
|
-- Access the pages several times
|
FOR I IN 0 TO c_nof_pages*3 LOOP
|
FOR I IN 0 TO c_nof_pages*3 LOOP
|
wr_en_a <= '1';
|
wr_en_a <= '1';
|
proc_common_wait_some_cycles(clk, c_page_sz-1);
|
proc_common_wait_some_cycles(clk, c_page_sz-1);
|
next_page <= '1';
|
next_page <= '1';
|
proc_common_wait_some_cycles(clk, 1);
|
proc_common_wait_some_cycles(clk, 1);
|
next_page <= '0';
|
next_page <= '0';
|
wr_en_a <= '0';
|
wr_en_a <= '0';
|
proc_common_wait_some_cycles(clk, c_gap_sz); -- optinal gap between the pages
|
proc_common_wait_some_cycles(clk, c_gap_sz); -- optinal gap between the pages
|
END LOOP;
|
END LOOP;
|
|
|
wr_en_a <= '0';
|
wr_en_a <= '0';
|
proc_common_wait_some_cycles(clk, c_page_sz);
|
proc_common_wait_some_cycles(clk, c_page_sz);
|
tb_end <= '1';
|
tb_end <= '1';
|
WAIT;
|
WAIT;
|
END PROCESS;
|
END PROCESS;
|
|
|
u_dut_mux : ENTITY work.common_paged_ram_crw_crw
|
u_dut_mux : ENTITY work.common_paged_ram_crw_crw
|
GENERIC MAP (
|
GENERIC MAP (
|
g_str => "use_mux",
|
g_str => "use_mux",
|
g_data_w => c_data_w,
|
g_data_w => c_data_w,
|
g_nof_pages => c_nof_pages,
|
g_nof_pages => c_nof_pages,
|
g_page_sz => c_page_sz,
|
g_page_sz => c_page_sz,
|
g_start_page_a => c_start_page_a,
|
g_start_page_a => c_start_page_a,
|
g_start_page_b => c_start_page_b
|
g_start_page_b => c_start_page_b
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
rst_a => rst,
|
rst_a => rst,
|
rst_b => rst,
|
rst_b => rst,
|
clk_a => clk,
|
clk_a => clk,
|
clk_b => clk,
|
clk_b => clk,
|
clken_a => '1',
|
clken_a => '1',
|
clken_b => '1',
|
clken_b => '1',
|
next_page_a => next_page_a,
|
next_page_a => next_page_a,
|
adr_a => adr_a,
|
adr_a => adr_a,
|
wr_en_a => wr_en_a,
|
wr_en_a => wr_en_a,
|
wr_dat_a => wr_dat_a,
|
wr_dat_a => wr_dat_a,
|
rd_en_a => '0',
|
rd_en_a => '0',
|
rd_dat_a => OPEN,
|
rd_dat_a => OPEN,
|
rd_val_a => OPEN,
|
rd_val_a => OPEN,
|
next_page_b => next_page_b,
|
next_page_b => next_page_b,
|
adr_b => adr_b,
|
adr_b => adr_b,
|
wr_en_b => '0',
|
wr_en_b => '0',
|
wr_dat_b => (OTHERS=>'0'),
|
wr_dat_b => (OTHERS=>'0'),
|
rd_en_b => rd_en_b,
|
rd_en_b => rd_en_b,
|
rd_dat_b => mux_rd_dat_b,
|
rd_dat_b => mux_rd_dat_b,
|
rd_val_b => mux_rd_val_b
|
rd_val_b => mux_rd_val_b
|
);
|
);
|
|
|
u_dut_adr : ENTITY work.common_paged_ram_crw_crw
|
u_dut_adr : ENTITY work.common_paged_ram_crw_crw
|
GENERIC MAP (
|
GENERIC MAP (
|
g_str => "use_adr",
|
g_str => "use_adr",
|
g_data_w => c_data_w,
|
g_data_w => c_data_w,
|
g_nof_pages => c_nof_pages,
|
g_nof_pages => c_nof_pages,
|
g_page_sz => c_page_sz,
|
g_page_sz => c_page_sz,
|
g_start_page_a => c_start_page_a,
|
g_start_page_a => c_start_page_a,
|
g_start_page_b => c_start_page_b
|
g_start_page_b => c_start_page_b
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
rst_a => rst,
|
rst_a => rst,
|
rst_b => rst,
|
rst_b => rst,
|
clk_a => clk,
|
clk_a => clk,
|
clk_b => clk,
|
clk_b => clk,
|
clken_a => '1',
|
clken_a => '1',
|
clken_b => '1',
|
clken_b => '1',
|
next_page_a => next_page_a,
|
next_page_a => next_page_a,
|
adr_a => adr_a,
|
adr_a => adr_a,
|
wr_en_a => wr_en_a,
|
wr_en_a => wr_en_a,
|
wr_dat_a => wr_dat_a,
|
wr_dat_a => wr_dat_a,
|
rd_en_a => '0',
|
rd_en_a => '0',
|
rd_dat_a => OPEN,
|
rd_dat_a => OPEN,
|
rd_val_a => OPEN,
|
rd_val_a => OPEN,
|
next_page_b => next_page_b,
|
next_page_b => next_page_b,
|
adr_b => adr_b,
|
adr_b => adr_b,
|
wr_en_b => '0',
|
wr_en_b => '0',
|
wr_dat_b => (OTHERS=>'0'),
|
wr_dat_b => (OTHERS=>'0'),
|
rd_en_b => rd_en_b,
|
rd_en_b => rd_en_b,
|
rd_dat_b => adr_rd_dat_b,
|
rd_dat_b => adr_rd_dat_b,
|
rd_val_b => adr_rd_val_b
|
rd_val_b => adr_rd_val_b
|
);
|
);
|
|
|
u_dut_ofs : ENTITY work.common_paged_ram_crw_crw
|
u_dut_ofs : ENTITY work.common_paged_ram_crw_crw
|
GENERIC MAP (
|
GENERIC MAP (
|
g_str => "use_ofs",
|
g_str => "use_ofs",
|
g_data_w => c_data_w,
|
g_data_w => c_data_w,
|
g_nof_pages => c_nof_pages,
|
g_nof_pages => c_nof_pages,
|
g_page_sz => c_page_sz,
|
g_page_sz => c_page_sz,
|
g_start_page_a => c_start_page_a,
|
g_start_page_a => c_start_page_a,
|
g_start_page_b => c_start_page_b
|
g_start_page_b => c_start_page_b
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
rst_a => rst,
|
rst_a => rst,
|
rst_b => rst,
|
rst_b => rst,
|
clk_a => clk,
|
clk_a => clk,
|
clk_b => clk,
|
clk_b => clk,
|
clken_a => '1',
|
clken_a => '1',
|
clken_b => '1',
|
clken_b => '1',
|
next_page_a => next_page_a,
|
next_page_a => next_page_a,
|
adr_a => adr_a,
|
adr_a => adr_a,
|
wr_en_a => wr_en_a,
|
wr_en_a => wr_en_a,
|
wr_dat_a => wr_dat_a,
|
wr_dat_a => wr_dat_a,
|
rd_en_a => '0',
|
rd_en_a => '0',
|
rd_dat_a => OPEN,
|
rd_dat_a => OPEN,
|
rd_val_a => OPEN,
|
rd_val_a => OPEN,
|
next_page_b => next_page_b,
|
next_page_b => next_page_b,
|
adr_b => adr_b,
|
adr_b => adr_b,
|
wr_en_b => '0',
|
wr_en_b => '0',
|
wr_dat_b => (OTHERS=>'0'),
|
wr_dat_b => (OTHERS=>'0'),
|
rd_en_b => rd_en_b,
|
rd_en_b => rd_en_b,
|
rd_dat_b => ofs_rd_dat_b,
|
rd_dat_b => ofs_rd_dat_b,
|
rd_val_b => ofs_rd_val_b
|
rd_val_b => ofs_rd_val_b
|
);
|
);
|
|
|
-- Verify that the read data is incrementing data
|
-- Verify that the read data is incrementing data
|
proc_common_verify_data(c_rl, clk, verify_en, ready, mux_rd_val_b, mux_rd_dat_b, prev_mux_rd_dat_b);
|
proc_common_verify_data(c_rl, clk, verify_en, ready, mux_rd_val_b, mux_rd_dat_b, prev_mux_rd_dat_b);
|
proc_common_verify_data(c_rl, clk, verify_en, ready, adr_rd_val_b, adr_rd_dat_b, prev_adr_rd_dat_b);
|
proc_common_verify_data(c_rl, clk, verify_en, ready, adr_rd_val_b, adr_rd_dat_b, prev_adr_rd_dat_b);
|
proc_common_verify_data(c_rl, clk, verify_en, ready, ofs_rd_val_b, ofs_rd_dat_b, prev_ofs_rd_dat_b);
|
proc_common_verify_data(c_rl, clk, verify_en, ready, ofs_rd_val_b, ofs_rd_dat_b, prev_ofs_rd_dat_b);
|
|
|
-- Verify that the read data is the same for all three DUT variants
|
-- Verify that the read data is the same for all three DUT variants
|
p_verify_equal : PROCESS(clk)
|
p_verify_equal : PROCESS(clk)
|
BEGIN
|
BEGIN
|
IF rising_edge(clk) THEN
|
IF rising_edge(clk) THEN
|
IF UNSIGNED(mux_rd_dat_b) /= UNSIGNED(adr_rd_dat_b) OR UNSIGNED(mux_rd_dat_b) /= UNSIGNED(ofs_rd_dat_b) THEN
|
IF UNSIGNED(mux_rd_dat_b) /= UNSIGNED(adr_rd_dat_b) OR UNSIGNED(mux_rd_dat_b) /= UNSIGNED(ofs_rd_dat_b) THEN
|
REPORT "DUT : read data differs between two implementations" SEVERITY ERROR;
|
REPORT "DUT : read data differs between two implementations" SEVERITY ERROR;
|
END IF;
|
END IF;
|
IF mux_rd_val_b /= adr_rd_val_b OR mux_rd_val_b /= ofs_rd_val_b THEN
|
IF mux_rd_val_b /= adr_rd_val_b OR mux_rd_val_b /= ofs_rd_val_b THEN
|
REPORT "DUT : read valid differs between two implementations" SEVERITY ERROR;
|
REPORT "DUT : read valid differs between two implementations" SEVERITY ERROR;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
END tb;
|
END tb;
|
|
|