-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright 2020
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- You may obtain a copy of the License at
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--
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib, common_ram_lib, common_mult_lib, technology_lib;
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LIBRARY IEEE, common_pkg_lib, astron_ram_lib, astron_multiplier_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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--USE technology_lib.technology_select_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_ram_lib.common_ram_pkg.ALL;
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USE astron_ram_lib.common_ram_pkg.ALL;
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-- Purpose:
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-- Purpose:
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-- Maintain a set of accumulators and output their values at every in_sync.
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-- Maintain a set of accumulators and output their values at every in_sync.
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-- Description:
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-- Description:
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-- . The products of two input streams are accumulated per block. The block
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-- . The products of two input streams are accumulated per block. The block
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-- size is g_nof_mux*g_nof_stat. The nof accumulators is equal to the block
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-- size is g_nof_mux*g_nof_stat. The nof accumulators is equal to the block
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-- size. The nof blocks that get accumulated depends on in_sync, because a
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-- size. The nof blocks that get accumulated depends on in_sync, because a
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-- new accumulation starts every time when in_sync pulses. Also when in_sync
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-- new accumulation starts every time when in_sync pulses. Also when in_sync
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-- pulses then after some latency the accumulation values of the previous
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-- pulses then after some latency the accumulation values of the previous
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-- in_sync interval become available at the out_* ports.
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-- in_sync interval become available at the out_* ports.
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-- . If g_complex = FALSE then only the real power statistic out_re is calculated,
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-- . If g_complex = FALSE then only the real power statistic out_re is calculated,
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-- else also the imaginary power statistic out_im. The real power statistic
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-- else also the imaginary power statistic out_im. The real power statistic
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-- is used for auto power calulations of a complex input, by connecting the
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-- is used for auto power calulations of a complex input, by connecting the
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-- signal to both input a and b. The imaginary is power statistic is used when
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-- signal to both input a and b. The imaginary is power statistic is used when
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-- the cross power needs to be calculated between 2 different complex inputs.
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-- the cross power needs to be calculated between 2 different complex inputs.
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-- Remarks:
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-- Remarks:
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-- . The required accumulator width depends the input data width and the nof of
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-- . The required accumulator width depends the input data width and the nof of
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-- block, i.e. the nof accumulations. E.g. for 18b*18b = 36b products and
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-- block, i.e. the nof accumulations. E.g. for 18b*18b = 36b products and
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-- 200000 accumulations yielding 18b bit growth so in total 36b+18b = 54b for
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-- 200000 accumulations yielding 18b bit growth so in total 36b+18b = 54b for
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-- the accumulators.
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-- the accumulators.
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-- . The nof accumulators determines the size (c_mem_acc) of the internal
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-- . The nof accumulators determines the size (c_mem_acc) of the internal
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-- accumulator memory.
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-- accumulator memory.
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-- . Using g_nof_mux>1 allows distinghuising different streams with a block.
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-- . Using g_nof_mux>1 allows distinghuising different streams with a block.
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-- The g_nof_mux does not impact the address range instead it impacts the
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-- The g_nof_mux does not impact the address range instead it impacts the
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-- out_val_m strobes that can be used as wr_en to the corresponding statistics
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-- out_val_m strobes that can be used as wr_en to the corresponding statistics
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-- output register in a range of g_nof_mux statistics output registers.
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-- output register in a range of g_nof_mux statistics output registers.
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ENTITY st_calc IS
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ENTITY st_calc IS
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GENERIC (
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GENERIC (
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g_technology : NATURAL := c_tech_select_default;
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g_technology : NATURAL := 0;
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g_nof_mux : NATURAL := 1;
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g_nof_mux : NATURAL := 1;
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g_nof_stat : NATURAL := 512;
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g_nof_stat : NATURAL := 512;
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g_in_dat_w : NATURAL := 18; -- = input data width
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g_in_dat_w : NATURAL := 18; -- = input data width
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g_out_dat_w : NATURAL := 54; -- = accumulator width for the input data products, so >> 2*g_in_dat_w
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g_out_dat_w : NATURAL := 54; -- = accumulator width for the input data products, so >> 2*g_in_dat_w
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g_out_adr_w : NATURAL := 9; -- = ceil_log2(g_nof_stat)
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g_out_adr_w : NATURAL := 9; -- = ceil_log2(g_nof_stat)
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g_complex : BOOLEAN := FALSE
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g_complex : BOOLEAN := FALSE
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);
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);
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PORT (
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PORT (
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rst : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clken : IN STD_LOGIC := '1';
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clken : IN STD_LOGIC := '1';
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in_ar : IN STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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in_ar : IN STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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in_ai : IN STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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in_ai : IN STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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in_br : IN STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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in_br : IN STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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in_bi : IN STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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in_bi : IN STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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in_val : IN STD_LOGIC;
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in_val : IN STD_LOGIC;
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in_sync : IN STD_LOGIC;
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in_sync : IN STD_LOGIC;
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out_adr : OUT STD_LOGIC_VECTOR(g_out_adr_w-1 DOWNTO 0);
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out_adr : OUT STD_LOGIC_VECTOR(g_out_adr_w-1 DOWNTO 0);
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out_re : OUT STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
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out_re : OUT STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
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out_im : OUT STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
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out_im : OUT STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
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out_val : OUT STD_LOGIC; -- Use when g_nof_mux = 1, else leave OPEN
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out_val : OUT STD_LOGIC; -- Use when g_nof_mux = 1, else leave OPEN
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out_val_m : OUT STD_LOGIC_VECTOR(g_nof_mux-1 DOWNTO 0) -- Use when g_nof_mux > 1, else leave OPEN
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out_val_m : OUT STD_LOGIC_VECTOR(g_nof_mux-1 DOWNTO 0) -- Use when g_nof_mux > 1, else leave OPEN
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);
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);
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END;
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END;
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ARCHITECTURE str OF st_calc IS
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ARCHITECTURE str OF st_calc IS
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CONSTANT c_mux_w : NATURAL := true_log2(g_nof_mux);
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CONSTANT c_mux_w : NATURAL := true_log2(g_nof_mux);
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CONSTANT c_adr_w : NATURAL := c_mux_w+g_out_adr_w; -- = = ceil_log2(g_nof_mux*g_nof_stat)
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CONSTANT c_adr_w : NATURAL := c_mux_w+g_out_adr_w; -- = = ceil_log2(g_nof_mux*g_nof_stat)
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CONSTANT c_dly_rd : NATURAL := 2;
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CONSTANT c_dly_rd : NATURAL := 2;
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CONSTANT c_dly_mul : NATURAL := 3;
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CONSTANT c_dly_mul : NATURAL := 3;
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CONSTANT c_dly_acc : NATURAL := 2;
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CONSTANT c_dly_acc : NATURAL := 2;
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CONSTANT c_dly_out : NATURAL := 0;
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CONSTANT c_dly_out : NATURAL := 0;
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CONSTANT c_mult_w : NATURAL := 2*g_in_dat_w;
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CONSTANT c_mult_w : NATURAL := 2*g_in_dat_w;
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CONSTANT c_acc_w : NATURAL := g_out_dat_w;
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CONSTANT c_acc_w : NATURAL := g_out_dat_w;
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CONSTANT c_acc_hold_load : BOOLEAN := TRUE;
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CONSTANT c_acc_hold_load : BOOLEAN := TRUE;
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CONSTANT c_rd_latency : NATURAL := 2;
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CONSTANT c_rd_latency : NATURAL := 2;
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CONSTANT c_mem_acc : t_c_mem := (c_rd_latency, c_adr_w, c_acc_w, g_nof_mux*g_nof_stat, 'X'); -- 1 M9K
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CONSTANT c_mem_acc : t_c_mem := (c_rd_latency, c_adr_w, c_acc_w, g_nof_mux*g_nof_stat, 'X'); -- 1 M9K
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SIGNAL mult_re : STD_LOGIC_VECTOR(c_mult_w-1 DOWNTO 0);
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SIGNAL mult_re : STD_LOGIC_VECTOR(c_mult_w-1 DOWNTO 0);
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SIGNAL mult_im : STD_LOGIC_VECTOR(c_mult_w-1 DOWNTO 0);
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SIGNAL mult_im : STD_LOGIC_VECTOR(c_mult_w-1 DOWNTO 0);
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SIGNAL reg_ar : STD_LOGIC_VECTOR(in_ar'RANGE);
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SIGNAL reg_ar : STD_LOGIC_VECTOR(in_ar'RANGE);
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SIGNAL reg_ai : STD_LOGIC_VECTOR(in_ai'RANGE);
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SIGNAL reg_ai : STD_LOGIC_VECTOR(in_ai'RANGE);
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SIGNAL reg_br : STD_LOGIC_VECTOR(in_br'RANGE);
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SIGNAL reg_br : STD_LOGIC_VECTOR(in_br'RANGE);
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SIGNAL reg_bi : STD_LOGIC_VECTOR(in_bi'RANGE);
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SIGNAL reg_bi : STD_LOGIC_VECTOR(in_bi'RANGE);
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SIGNAL reg_val : STD_LOGIC;
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SIGNAL reg_val : STD_LOGIC;
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SIGNAL reg_sync : STD_LOGIC;
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SIGNAL reg_sync : STD_LOGIC;
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SIGNAL nxt_reg_ar : STD_LOGIC_VECTOR(in_ar'RANGE);
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SIGNAL nxt_reg_ar : STD_LOGIC_VECTOR(in_ar'RANGE);
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SIGNAL nxt_reg_ai : STD_LOGIC_VECTOR(in_ai'RANGE);
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SIGNAL nxt_reg_ai : STD_LOGIC_VECTOR(in_ai'RANGE);
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SIGNAL nxt_reg_br : STD_LOGIC_VECTOR(in_br'RANGE);
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SIGNAL nxt_reg_br : STD_LOGIC_VECTOR(in_br'RANGE);
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SIGNAL nxt_reg_bi : STD_LOGIC_VECTOR(in_bi'RANGE);
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SIGNAL nxt_reg_bi : STD_LOGIC_VECTOR(in_bi'RANGE);
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SIGNAL nxt_reg_val : STD_LOGIC;
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SIGNAL nxt_reg_val : STD_LOGIC;
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SIGNAL nxt_reg_sync : STD_LOGIC;
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SIGNAL nxt_reg_sync : STD_LOGIC;
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SIGNAL acc_load : STD_LOGIC;
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SIGNAL acc_load : STD_LOGIC;
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SIGNAL rd_en : STD_LOGIC;
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SIGNAL rd_en : STD_LOGIC;
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SIGNAL rd_adr : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0);
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SIGNAL rd_adr : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0);
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SIGNAL rd_re : STD_LOGIC_VECTOR(c_acc_w-1 DOWNTO 0);
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SIGNAL rd_re : STD_LOGIC_VECTOR(c_acc_w-1 DOWNTO 0);
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SIGNAL rd_im : STD_LOGIC_VECTOR(c_acc_w-1 DOWNTO 0);
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SIGNAL rd_im : STD_LOGIC_VECTOR(c_acc_w-1 DOWNTO 0);
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SIGNAL wr_en : STD_LOGIC;
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SIGNAL wr_en : STD_LOGIC;
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SIGNAL wr_adr : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0);
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SIGNAL wr_adr : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0);
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SIGNAL wr_re : STD_LOGIC_VECTOR(c_acc_w-1 DOWNTO 0);
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SIGNAL wr_re : STD_LOGIC_VECTOR(c_acc_w-1 DOWNTO 0);
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SIGNAL wr_im : STD_LOGIC_VECTOR(c_acc_w-1 DOWNTO 0);
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SIGNAL wr_im : STD_LOGIC_VECTOR(c_acc_w-1 DOWNTO 0);
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SIGNAL out_adr_m : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0);
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SIGNAL out_adr_m : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0);
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BEGIN
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BEGIN
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regs: PROCESS(rst,clk)
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regs: PROCESS(rst,clk)
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BEGIN
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BEGIN
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IF rst='1' THEN
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IF rst='1' THEN
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reg_ar <= (OTHERS => '0');
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reg_ar <= (OTHERS => '0');
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reg_ai <= (OTHERS => '0');
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reg_ai <= (OTHERS => '0');
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reg_br <= (OTHERS => '0');
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reg_br <= (OTHERS => '0');
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reg_bi <= (OTHERS => '0');
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reg_bi <= (OTHERS => '0');
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reg_val <= '0';
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reg_val <= '0';
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reg_sync <= '0';
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reg_sync <= '0';
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ELSIF rising_edge(clk) THEN
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ELSIF rising_edge(clk) THEN
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reg_ar <= nxt_reg_ar;
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reg_ar <= nxt_reg_ar;
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reg_ai <= nxt_reg_ai;
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reg_ai <= nxt_reg_ai;
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reg_br <= nxt_reg_br;
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reg_br <= nxt_reg_br;
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reg_bi <= nxt_reg_bi;
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reg_bi <= nxt_reg_bi;
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reg_val <= nxt_reg_val;
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reg_val <= nxt_reg_val;
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reg_sync <= nxt_reg_sync;
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reg_sync <= nxt_reg_sync;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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nxt_reg_ar <= in_ar WHEN in_val='1' ELSE reg_ar;
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nxt_reg_ar <= in_ar WHEN in_val='1' ELSE reg_ar;
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nxt_reg_ai <= in_ai WHEN in_val='1' ELSE reg_ai;
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nxt_reg_ai <= in_ai WHEN in_val='1' ELSE reg_ai;
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nxt_reg_br <= in_br WHEN in_val='1' ELSE reg_br;
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nxt_reg_br <= in_br WHEN in_val='1' ELSE reg_br;
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nxt_reg_bi <= in_bi WHEN in_val='1' ELSE reg_bi;
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nxt_reg_bi <= in_bi WHEN in_val='1' ELSE reg_bi;
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nxt_reg_val <= in_val;
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nxt_reg_val <= in_val;
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nxt_reg_sync <= in_sync;
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nxt_reg_sync <= in_sync;
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-- ctrl block: generates all ctrl signals
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-- ctrl block: generates all ctrl signals
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ctrl: ENTITY work.st_ctrl
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ctrl: ENTITY work.st_ctrl
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GENERIC MAP (
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GENERIC MAP (
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g_nof_mux => g_nof_mux,
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g_nof_mux => g_nof_mux,
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g_nof_stat => g_nof_stat,
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g_nof_stat => g_nof_stat,
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g_adr_w => c_adr_w,
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g_adr_w => c_adr_w,
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g_dly_rd => c_dly_rd,
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g_dly_rd => c_dly_rd,
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g_dly_mul => c_dly_mul,
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g_dly_mul => c_dly_mul,
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g_dly_acc => c_dly_acc,
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g_dly_acc => c_dly_acc,
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g_dly_out => c_dly_out
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g_dly_out => c_dly_out
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)
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)
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PORT MAP (
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PORT MAP (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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in_sync => reg_sync,
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in_sync => reg_sync,
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in_val => reg_val,
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in_val => reg_val,
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rd_en => rd_en,
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rd_en => rd_en,
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rd_adr => rd_adr,
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rd_adr => rd_adr,
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rd_val => OPEN,
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rd_val => OPEN,
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mult_val => OPEN,
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mult_val => OPEN,
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acc_load => acc_load,
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acc_load => acc_load,
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wr_en => wr_en,
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wr_en => wr_en,
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wr_adr => wr_adr,
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wr_adr => wr_adr,
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out_val => out_val,
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out_val => out_val,
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out_val_m => out_val_m,
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out_val_m => out_val_m,
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out_adr => out_adr_m
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out_adr => out_adr_m
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);
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);
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out_adr <= out_adr_m(c_adr_w-1 DOWNTO c_mux_w);
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out_adr <= out_adr_m(c_adr_w-1 DOWNTO c_mux_w);
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-- complex multiplier: computes a * conj(b)
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-- complex multiplier: computes a * conj(b)
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--mul: ENTITY common_lib.common_complex_mult(str)
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--mul: ENTITY common_lib.common_complex_mult(str)
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mul: ENTITY common_mult_lib.common_complex_mult
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mul: ENTITY astron_multiplier_lib.common_complex_mult
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GENERIC MAP (
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GENERIC MAP (
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g_technology => g_technology,
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g_technology => g_technology,
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g_variant => "IP",
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g_variant => "IP",
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g_in_a_w => in_ar'LENGTH,
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g_in_a_w => in_ar'LENGTH,
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g_in_b_w => in_br'LENGTH,
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g_in_b_w => in_br'LENGTH,
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g_out_p_w => mult_re'LENGTH,
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g_out_p_w => mult_re'LENGTH,
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g_conjugate_b => TRUE, -- use conjugate product for cross power
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g_conjugate_b => TRUE, -- use conjugate product for cross power
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g_pipeline_input => 1,
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g_pipeline_input => 1,
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g_pipeline_product => 0,
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g_pipeline_product => 0,
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g_pipeline_adder => 1,
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g_pipeline_adder => 1,
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g_pipeline_output => 1 -- 1+0+1+1 = 3 = c_dly_mul
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g_pipeline_output => 1 -- 1+0+1+1 = 3 = c_dly_mul
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)
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)
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PORT MAP (
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PORT MAP (
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clk => clk,
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clk => clk,
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clken => clken,
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clken => clken,
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in_ar => reg_ar,
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in_ar => reg_ar,
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in_ai => reg_ai,
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in_ai => reg_ai,
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in_br => reg_br,
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in_br => reg_br,
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in_bi => reg_bi,
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in_bi => reg_bi,
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out_pr => mult_re,
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out_pr => mult_re,
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out_pi => mult_im
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out_pi => mult_im
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);
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);
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-- accumulator for real part
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-- accumulator for real part
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acc_re: ENTITY work.st_acc
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acc_re: ENTITY work.st_acc
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GENERIC MAP (
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GENERIC MAP (
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g_dat_w => c_mult_w,
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g_dat_w => c_mult_w,
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g_acc_w => c_acc_w,
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g_acc_w => c_acc_w,
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g_hold_load => c_acc_hold_load,
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g_hold_load => c_acc_hold_load,
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g_pipeline_input => 1,
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g_pipeline_input => 1,
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g_pipeline_output => c_dly_acc-1
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g_pipeline_output => c_dly_acc-1
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)
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)
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PORT MAP (
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PORT MAP (
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clk => clk,
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clk => clk,
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clken => clken,
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clken => clken,
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in_load => acc_load,
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in_load => acc_load,
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in_dat => mult_re,
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in_dat => mult_re,
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in_acc => rd_re,
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in_acc => rd_re,
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out_acc => wr_re
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out_acc => wr_re
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);
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);
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|
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-- accumulator memory for real part
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-- accumulator memory for real part
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ram_re: ENTITY common_ram_lib.common_ram_r_w
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ram_re: ENTITY astron_ram_lib.common_ram_r_w
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GENERIC MAP (
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GENERIC MAP (
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g_technology => g_technology,
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g_technology => g_technology,
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g_ram => c_mem_acc,
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g_ram => c_mem_acc,
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g_init_file => "UNUSED"
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g_init_file => "UNUSED"
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)
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)
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PORT MAP (
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PORT MAP (
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rst => rst,
|
rst => rst,
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clk => clk,
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clk => clk,
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clken => clken,
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clken => clken,
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wr_en => wr_en,
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wr_en => wr_en,
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wr_adr => wr_adr,
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wr_adr => wr_adr,
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wr_dat => wr_re,
|
wr_dat => wr_re,
|
rd_en => rd_en,
|
rd_en => rd_en,
|
rd_adr => rd_adr,
|
rd_adr => rd_adr,
|
rd_dat => rd_re,
|
rd_dat => rd_re,
|
rd_val => OPEN
|
rd_val => OPEN
|
);
|
);
|
|
|
out_re <= rd_re; -- c_dly_out = 0
|
out_re <= rd_re; -- c_dly_out = 0
|
|
|
-- imaginary part is optional
|
-- imaginary part is optional
|
no_im: IF g_complex=FALSE GENERATE
|
no_im: IF g_complex=FALSE GENERATE
|
out_im <= (OTHERS => '0');
|
out_im <= (OTHERS => '0');
|
END GENERATE;
|
END GENERATE;
|
|
|
gen_im: IF g_complex=TRUE GENERATE
|
gen_im: IF g_complex=TRUE GENERATE
|
-- accumulator
|
-- accumulator
|
acc_im: ENTITY work.st_acc
|
acc_im: ENTITY work.st_acc
|
GENERIC MAP (
|
GENERIC MAP (
|
g_dat_w => c_mult_w,
|
g_dat_w => c_mult_w,
|
g_acc_w => c_acc_w,
|
g_acc_w => c_acc_w,
|
g_hold_load => c_acc_hold_load,
|
g_hold_load => c_acc_hold_load,
|
g_pipeline_input => 1,
|
g_pipeline_input => 1,
|
g_pipeline_output => c_dly_acc-1
|
g_pipeline_output => c_dly_acc-1
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
clk => clk,
|
clk => clk,
|
clken => clken,
|
clken => clken,
|
in_load => acc_load,
|
in_load => acc_load,
|
in_dat => mult_im,
|
in_dat => mult_im,
|
in_acc => rd_im,
|
in_acc => rd_im,
|
out_acc => wr_im
|
out_acc => wr_im
|
);
|
);
|
|
|
-- dual port memory
|
-- dual port memory
|
ram_im: ENTITY common_ram_lib.common_ram_r_w
|
ram_im: ENTITY astron_ram_lib.common_ram_r_w
|
GENERIC MAP (
|
GENERIC MAP (
|
g_technology => g_technology,
|
g_technology => g_technology,
|
g_ram => c_mem_acc,
|
g_ram => c_mem_acc,
|
g_init_file => "UNUSED"
|
g_init_file => "UNUSED"
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
rst => rst,
|
rst => rst,
|
clk => clk,
|
clk => clk,
|
clken => clken,
|
clken => clken,
|
wr_en => wr_en,
|
wr_en => wr_en,
|
wr_adr => wr_adr,
|
wr_adr => wr_adr,
|
wr_dat => wr_im,
|
wr_dat => wr_im,
|
rd_en => rd_en,
|
rd_en => rd_en,
|
rd_adr => rd_adr,
|
rd_adr => rd_adr,
|
rd_dat => rd_im,
|
rd_dat => rd_im,
|
rd_val => OPEN
|
rd_val => OPEN
|
);
|
);
|
|
|
out_im <= rd_im; -- c_dly_out = 0
|
out_im <= rd_im; -- c_dly_out = 0
|
END GENERATE;
|
END GENERATE;
|
|
|
END str;
|
END str;
|
|
|