-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright 2020
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- You may obtain a copy of the License at
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--
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib, common_ram_lib, common_counter_lib, mm_lib, technology_lib, dp_pkg_lib;
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LIBRARY IEEE, common_pkg_lib, astron_ram_lib, astron_counter_lib, astron_mm_lib, dp_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_ram_lib.common_ram_pkg.ALL;
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USE astron_ram_lib.common_ram_pkg.ALL;
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USE mm_lib.common_field_pkg.ALL;
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USE astron_mm_lib.common_field_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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--USE technology_lib.technology_select_pkg.ALL;
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-- Purpose:
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-- Purpose:
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-- Store the (auto)power statistics of a complex input stream with
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-- Store the (auto)power statistics of a complex input stream with
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-- blocks of nof_stat multiplexed subbands into a MM register.
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-- blocks of nof_stat multiplexed subbands into a MM register.
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-- Description:
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-- Description:
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--
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--
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-- When the treshold register is set to 0 the statistics will be auto-
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-- When the treshold register is set to 0 the statistics will be auto-
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-- correlations.
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-- correlations.
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-- In case the treshold register is set to a non-zero value, it allows
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-- In case the treshold register is set to a non-zero value, it allows
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-- to create a sample & hold function for the a-input of the multiplier.
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-- to create a sample & hold function for the a-input of the multiplier.
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-- The a-input of the multiplier is updated every "treshold" clockcycle.
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-- The a-input of the multiplier is updated every "treshold" clockcycle.
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-- Thereby cross statistics can be created.
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-- Thereby cross statistics can be created.
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--
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--
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-- After each sync the MM register gets updated with the (auto) power statistics
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-- After each sync the MM register gets updated with the (auto) power statistics
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-- of the previous sync interval. The length of the sync interval determines
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-- of the previous sync interval. The length of the sync interval determines
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-- the nof accumlations per statistic, hence the integration time. See st_calc
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-- the nof accumlations per statistic, hence the integration time. See st_calc
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-- for more details.
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-- for more details.
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-- Remarks:
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-- Remarks:
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-- . The in_sync is assumed to be a pulse an interpreted directly.
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-- . The in_sync is assumed to be a pulse an interpreted directly.
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-- . The MM register is single page RAM to save memory resources. Therefore
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-- . The MM register is single page RAM to save memory resources. Therefore
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-- just after the sync its contents is undefined when it gets written, but
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-- just after the sync its contents is undefined when it gets written, but
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-- after that its contents remains stable for the rest of the sync interval.
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-- after that its contents remains stable for the rest of the sync interval.
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-- Therefore it is not necessary to use a dual page register that swaps at
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-- Therefore it is not necessary to use a dual page register that swaps at
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-- the sync.
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-- the sync.
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-- . The minimum g_nof_stat = 8. Lower values lead to simulation errors. This is
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-- . The minimum g_nof_stat = 8. Lower values lead to simulation errors. This is
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-- due to the read latency of 2 of the accumulation memory in the st_calc entity.
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-- due to the read latency of 2 of the accumulation memory in the st_calc entity.
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ENTITY st_sst IS
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ENTITY st_sst IS
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GENERIC (
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GENERIC (
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g_technology : NATURAL := c_tech_select_default;
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g_technology : NATURAL := 0;
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g_nof_stat : NATURAL := 512; -- nof accumulators
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g_nof_stat : NATURAL := 512; -- nof accumulators
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g_xst_enable : BOOLEAN := FALSE; -- when set to true, an extra memory is instantiated to hold the imaginary part of the cross-correlation results
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g_xst_enable : BOOLEAN := FALSE; -- when set to true, an extra memory is instantiated to hold the imaginary part of the cross-correlation results
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g_in_data_w : NATURAL := 18; -- width o dth edata to be accumulated
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g_in_data_w : NATURAL := 18; -- width o dth edata to be accumulated
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g_stat_data_w : NATURAL := 54; -- statistics accumulator width
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g_stat_data_w : NATURAL := 54; -- statistics accumulator width
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g_stat_data_sz : NATURAL := 2 -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
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g_stat_data_sz : NATURAL := 2 -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
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);
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);
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PORT (
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PORT (
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mm_rst : IN STD_LOGIC;
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mm_rst : IN STD_LOGIC;
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mm_clk : IN STD_LOGIC;
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mm_clk : IN STD_LOGIC;
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dp_rst : IN STD_LOGIC;
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dp_rst : IN STD_LOGIC;
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dp_clk : IN STD_LOGIC;
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dp_clk : IN STD_LOGIC;
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-- Streaming
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-- Streaming
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in_complex : IN t_dp_sosi; -- Complex input data
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in_complex : IN t_dp_sosi; -- Complex input data
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-- Memory Mapped
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-- Memory Mapped
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ram_st_sst_mosi : IN t_mem_mosi;
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ram_st_sst_mosi : IN t_mem_mosi;
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ram_st_sst_miso : OUT t_mem_miso;
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ram_st_sst_miso : OUT t_mem_miso;
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reg_st_sst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
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reg_st_sst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
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reg_st_sst_miso : OUT t_mem_miso := c_mem_miso_rst
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reg_st_sst_miso : OUT t_mem_miso := c_mem_miso_rst
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);
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);
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END st_sst;
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END st_sst;
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ARCHITECTURE str OF st_sst IS
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ARCHITECTURE str OF st_sst IS
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CONSTANT c_nof_stat_w : NATURAL := ceil_log2(g_nof_stat);
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CONSTANT c_nof_stat_w : NATURAL := ceil_log2(g_nof_stat);
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CONSTANT c_nof_word : NATURAL := g_stat_data_sz*g_nof_stat;
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CONSTANT c_nof_word : NATURAL := g_stat_data_sz*g_nof_stat;
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CONSTANT c_nof_word_w : NATURAL := ceil_log2(c_nof_word);
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CONSTANT c_nof_word_w : NATURAL := ceil_log2(c_nof_word);
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CONSTANT g_stat_word_w : NATURAL := g_stat_data_sz*c_word_w;
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CONSTANT g_stat_word_w : NATURAL := g_stat_data_sz*c_word_w;
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CONSTANT zeros : STD_LOGIC_VECTOR(c_nof_stat_w-1 DOWNTO 0) := (OTHERS => '0');
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CONSTANT zeros : STD_LOGIC_VECTOR(c_nof_stat_w-1 DOWNTO 0) := (OTHERS => '0');
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-- Statistics register
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-- Statistics register
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CONSTANT c_mm_ram : t_c_mem := (latency => 1,
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CONSTANT c_mm_ram : t_c_mem := (latency => 1,
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adr_w => c_nof_word_w,
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adr_w => c_nof_word_w,
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dat_w => c_word_w,
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dat_w => c_word_w,
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nof_dat => c_nof_word,
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nof_dat => c_nof_word,
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init_sl => '0'); -- MM side : sla_in, sla_out
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init_sl => '0'); -- MM side : sla_in, sla_out
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CONSTANT c_stat_ram : t_c_mem := (latency => 1,
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CONSTANT c_stat_ram : t_c_mem := (latency => 1,
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adr_w => c_nof_stat_w,
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adr_w => c_nof_stat_w,
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dat_w => g_stat_word_w,
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dat_w => g_stat_word_w,
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nof_dat => g_nof_stat,
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nof_dat => g_nof_stat,
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init_sl => '0'); -- ST side : stat_mosi
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init_sl => '0'); -- ST side : stat_mosi
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CONSTANT c_field_arr : t_common_field_arr(0 DOWNTO 0) := (0=> ( field_name_pad("treshold"), "RW", c_nof_stat_w, field_default(0) ));
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CONSTANT c_field_arr : t_common_field_arr(0 DOWNTO 0) := (0=> ( field_name_pad("treshold"), "RW", c_nof_stat_w, field_default(0) ));
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SIGNAL mm_fields_out : STD_LOGIC_VECTOR(field_slv_out_len(c_field_arr)-1 DOWNTO 0);
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SIGNAL mm_fields_out : STD_LOGIC_VECTOR(field_slv_out_len(c_field_arr)-1 DOWNTO 0);
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SIGNAL treshold : STD_LOGIC_VECTOR(c_nof_stat_w-1 DOWNTO 0);
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SIGNAL treshold : STD_LOGIC_VECTOR(c_nof_stat_w-1 DOWNTO 0);
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TYPE reg_type IS RECORD
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TYPE reg_type IS RECORD
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in_sosi_reg : t_dp_sosi;
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in_sosi_reg : t_dp_sosi;
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in_a_re : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO 0);
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in_a_re : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO 0);
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in_a_im : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO 0);
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in_a_im : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO 0);
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END RECORD;
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END RECORD;
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SIGNAL r, rin : reg_type;
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SIGNAL r, rin : reg_type;
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SIGNAL in_sync : STD_LOGIC;
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SIGNAL in_sync : STD_LOGIC;
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SIGNAL stat_data_re : STD_LOGIC_VECTOR(g_stat_data_w-1 DOWNTO 0);
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SIGNAL stat_data_re : STD_LOGIC_VECTOR(g_stat_data_w-1 DOWNTO 0);
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SIGNAL stat_data_im : STD_LOGIC_VECTOR(g_stat_data_w-1 DOWNTO 0);
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SIGNAL stat_data_im : STD_LOGIC_VECTOR(g_stat_data_w-1 DOWNTO 0);
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SIGNAL wrdata_re : STD_LOGIC_VECTOR(c_mem_data_w-1 DOWNTO 0);
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SIGNAL wrdata_re : STD_LOGIC_VECTOR(c_mem_data_w-1 DOWNTO 0);
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SIGNAL wrdata_im : STD_LOGIC_VECTOR(c_mem_data_w-1 DOWNTO 0);
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SIGNAL wrdata_im : STD_LOGIC_VECTOR(c_mem_data_w-1 DOWNTO 0);
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SIGNAL stat_mosi : t_mem_mosi;
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SIGNAL stat_mosi : t_mem_mosi;
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SIGNAL count : STD_LOGIC_VECTOR(c_nof_stat_w-1 DOWNTO 0);
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SIGNAL count : STD_LOGIC_VECTOR(c_nof_stat_w-1 DOWNTO 0);
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SIGNAL ram_st_sst_mosi_arr : t_mem_mosi_arr(c_nof_complex-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
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SIGNAL ram_st_sst_mosi_arr : t_mem_mosi_arr(c_nof_complex-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
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SIGNAL ram_st_sst_miso_arr : t_mem_miso_arr(c_nof_complex-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
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SIGNAL ram_st_sst_miso_arr : t_mem_miso_arr(c_nof_complex-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
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BEGIN
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BEGIN
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Register map for the treshold register
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-- Register map for the treshold register
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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register_map : ENTITY mm_lib.mm_fields
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register_map : ENTITY astron_mm_lib.mm_fields
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GENERIC MAP(
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GENERIC MAP(
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g_cross_clock_domain => TRUE,
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g_cross_clock_domain => TRUE,
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g_field_arr => c_field_arr
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g_field_arr => c_field_arr
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)
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)
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PORT MAP (
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PORT MAP (
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mm_rst => mm_rst,
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mm_rst => mm_rst,
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mm_clk => mm_clk,
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mm_clk => mm_clk,
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mm_mosi => reg_st_sst_mosi,
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mm_mosi => reg_st_sst_mosi,
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mm_miso => reg_st_sst_miso,
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mm_miso => reg_st_sst_miso,
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slv_rst => dp_rst,
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slv_rst => dp_rst,
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slv_clk => dp_clk,
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slv_clk => dp_clk,
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slv_out => mm_fields_out
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slv_out => mm_fields_out
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);
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);
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treshold <= mm_fields_out(field_hi(c_field_arr, "treshold") DOWNTO field_lo(c_field_arr, "treshold"));
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treshold <= mm_fields_out(field_hi(c_field_arr, "treshold") DOWNTO field_lo(c_field_arr, "treshold"));
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Input registers and preparation of the input data for the multiplier.
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-- Input registers and preparation of the input data for the multiplier.
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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comb : PROCESS(r, dp_rst, in_complex, count, treshold)
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comb : PROCESS(r, dp_rst, in_complex, count, treshold)
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VARIABLE v : reg_type;
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VARIABLE v : reg_type;
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BEGIN
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BEGIN
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v := r;
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v := r;
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v.in_sosi_reg := in_complex;
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v.in_sosi_reg := in_complex;
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IF(count = zeros OR treshold = zeros) THEN
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IF(count = zeros OR treshold = zeros) THEN
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v.in_a_re := in_complex.re(g_in_data_w-1 DOWNTO 0);
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v.in_a_re := in_complex.re(g_in_data_w-1 DOWNTO 0);
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v.in_a_im := in_complex.im(g_in_data_w-1 DOWNTO 0);
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v.in_a_im := in_complex.im(g_in_data_w-1 DOWNTO 0);
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END IF;
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END IF;
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IF(dp_rst = '1') THEN
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IF(dp_rst = '1') THEN
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v.in_a_re := (OTHERS => '0');
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v.in_a_re := (OTHERS => '0');
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v.in_a_im := (OTHERS => '0');
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v.in_a_im := (OTHERS => '0');
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END IF;
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END IF;
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rin <= v;
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rin <= v;
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END PROCESS comb;
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END PROCESS comb;
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regs : PROCESS(dp_clk)
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regs : PROCESS(dp_clk)
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BEGIN
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BEGIN
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IF rising_edge(dp_clk) THEN
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IF rising_edge(dp_clk) THEN
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r <= rin;
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r <= rin;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Counter used to detect when treshold is reached in order to load new
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-- Counter used to detect when treshold is reached in order to load new
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-- input vlaues for the multiplier.
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-- input vlaues for the multiplier.
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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treshold_cnt : ENTITY common_counter_lib.common_counter
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treshold_cnt : ENTITY astron_counter_lib.common_counter
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GENERIC MAP(
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GENERIC MAP(
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g_latency => 1,
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g_latency => 1,
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g_init => 0,
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g_init => 0,
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g_width => c_nof_stat_w,
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g_width => c_nof_stat_w,
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g_max => 0,
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g_max => 0,
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g_step_size => 1
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g_step_size => 1
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)
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)
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PORT MAP (
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PORT MAP (
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rst => dp_rst,
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rst => dp_rst,
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clk => dp_clk,
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clk => dp_clk,
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cnt_clr => in_complex.eop,
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cnt_clr => in_complex.eop,
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cnt_en => in_complex.valid,
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cnt_en => in_complex.valid,
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cnt_max => treshold,
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cnt_max => treshold,
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count => count
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count => count
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);
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);
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in_sync <= in_complex.sync;
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in_sync <= in_complex.sync;
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st_calc : ENTITY work.st_calc
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st_calc : ENTITY work.st_calc
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GENERIC MAP (
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GENERIC MAP (
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g_technology => g_technology,
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g_technology => g_technology,
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g_nof_mux => 1,
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g_nof_mux => 1,
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g_nof_stat => g_nof_stat,
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g_nof_stat => g_nof_stat,
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g_in_dat_w => g_in_data_w,
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g_in_dat_w => g_in_data_w,
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g_out_dat_w => g_stat_data_w,
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g_out_dat_w => g_stat_data_w,
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g_out_adr_w => c_nof_stat_w,
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g_out_adr_w => c_nof_stat_w,
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g_complex => g_xst_enable
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g_complex => g_xst_enable
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)
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)
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PORT MAP (
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PORT MAP (
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rst => dp_rst,
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rst => dp_rst,
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clk => dp_clk,
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clk => dp_clk,
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in_ar => r.in_a_re,
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in_ar => r.in_a_re,
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in_ai => r.in_a_im,
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in_ai => r.in_a_im,
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in_br => r.in_sosi_reg.re(g_in_data_w-1 DOWNTO 0),
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in_br => r.in_sosi_reg.re(g_in_data_w-1 DOWNTO 0),
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in_bi => r.in_sosi_reg.im(g_in_data_w-1 DOWNTO 0),
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in_bi => r.in_sosi_reg.im(g_in_data_w-1 DOWNTO 0),
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in_val => r.in_sosi_reg.valid,
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in_val => r.in_sosi_reg.valid,
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in_sync => in_sync,
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in_sync => in_sync,
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out_adr => stat_mosi.address(c_stat_ram.adr_w-1 DOWNTO 0),
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out_adr => stat_mosi.address(c_stat_ram.adr_w-1 DOWNTO 0),
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out_re => stat_data_re,
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out_re => stat_data_re,
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out_im => stat_data_im,
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out_im => stat_data_im,
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out_val => stat_mosi.wr,
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out_val => stat_mosi.wr,
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out_val_m => OPEN
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out_val_m => OPEN
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);
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);
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|
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wrdata_re <= RESIZE_MEM_UDATA(stat_data_re);
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wrdata_re <= RESIZE_MEM_UDATA(stat_data_re);
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wrdata_im <= RESIZE_MEM_UDATA(stat_data_im);
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wrdata_im <= RESIZE_MEM_UDATA(stat_data_im);
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|
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stat_reg_re : ENTITY common_ram_lib.common_ram_crw_crw_ratio
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stat_reg_re : ENTITY astron_ram_lib.common_ram_crw_crw_ratio
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GENERIC MAP (
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GENERIC MAP (
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g_technology => g_technology,
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g_technology => g_technology,
|
g_ram_a => c_mm_ram,
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g_ram_a => c_mm_ram,
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g_ram_b => c_stat_ram,
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g_ram_b => c_stat_ram,
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g_init_file => "UNUSED"
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g_init_file => "UNUSED"
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)
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)
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PORT MAP (
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PORT MAP (
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rst_a => mm_rst,
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rst_a => mm_rst,
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clk_a => mm_clk,
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clk_a => mm_clk,
|
|
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rst_b => dp_rst,
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rst_b => dp_rst,
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clk_b => dp_clk,
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clk_b => dp_clk,
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|
|
wr_en_a => ram_st_sst_mosi_arr(0).wr, -- only for diagnostic purposes, typically statistics are read only
|
wr_en_a => ram_st_sst_mosi_arr(0).wr, -- only for diagnostic purposes, typically statistics are read only
|
wr_dat_a => ram_st_sst_mosi_arr(0).wrdata(c_mm_ram.dat_w-1 DOWNTO 0),
|
wr_dat_a => ram_st_sst_mosi_arr(0).wrdata(c_mm_ram.dat_w-1 DOWNTO 0),
|
adr_a => ram_st_sst_mosi_arr(0).address(c_mm_ram.adr_w-1 DOWNTO 0),
|
adr_a => ram_st_sst_mosi_arr(0).address(c_mm_ram.adr_w-1 DOWNTO 0),
|
rd_en_a => ram_st_sst_mosi_arr(0).rd,
|
rd_en_a => ram_st_sst_mosi_arr(0).rd,
|
rd_dat_a => ram_st_sst_miso_arr(0).rddata(c_mm_ram.dat_w-1 DOWNTO 0),
|
rd_dat_a => ram_st_sst_miso_arr(0).rddata(c_mm_ram.dat_w-1 DOWNTO 0),
|
rd_val_a => ram_st_sst_miso_arr(0).rdval,
|
rd_val_a => ram_st_sst_miso_arr(0).rdval,
|
|
|
wr_en_b => stat_mosi.wr,
|
wr_en_b => stat_mosi.wr,
|
wr_dat_b => wrdata_re(c_stat_ram.dat_w-1 DOWNTO 0),
|
wr_dat_b => wrdata_re(c_stat_ram.dat_w-1 DOWNTO 0),
|
adr_b => stat_mosi.address(c_stat_ram.adr_w-1 DOWNTO 0),
|
adr_b => stat_mosi.address(c_stat_ram.adr_w-1 DOWNTO 0),
|
rd_en_b => '0',
|
rd_en_b => '0',
|
rd_dat_b => OPEN,
|
rd_dat_b => OPEN,
|
rd_val_b => OPEN
|
rd_val_b => OPEN
|
);
|
);
|
|
|
gen_re: IF g_xst_enable=FALSE GENERATE
|
gen_re: IF g_xst_enable=FALSE GENERATE
|
ram_st_sst_mosi_arr(0) <= ram_st_sst_mosi;
|
ram_st_sst_mosi_arr(0) <= ram_st_sst_mosi;
|
ram_st_sst_miso <= ram_st_sst_miso_arr(0);
|
ram_st_sst_miso <= ram_st_sst_miso_arr(0);
|
END GENERATE;
|
END GENERATE;
|
|
|
gen_im: IF g_xst_enable=TRUE GENERATE
|
gen_im: IF g_xst_enable=TRUE GENERATE
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
-- COMBINE MEMORY MAPPED INTERFACES
|
-- COMBINE MEMORY MAPPED INTERFACES
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
-- Combine the internal array of mm interfaces for both real
|
-- Combine the internal array of mm interfaces for both real
|
-- and imaginary part.
|
-- and imaginary part.
|
u_mem_mux_select : entity mm_lib.common_mem_mux
|
u_mem_mux_select : entity astron_mm_lib.common_mem_mux
|
generic map (
|
generic map (
|
g_nof_mosi => c_nof_complex,
|
g_nof_mosi => c_nof_complex,
|
g_mult_addr_w => c_nof_word_w
|
g_mult_addr_w => c_nof_word_w
|
)
|
)
|
port map (
|
port map (
|
mosi => ram_st_sst_mosi,
|
mosi => ram_st_sst_mosi,
|
miso => ram_st_sst_miso,
|
miso => ram_st_sst_miso,
|
mosi_arr => ram_st_sst_mosi_arr,
|
mosi_arr => ram_st_sst_mosi_arr,
|
miso_arr => ram_st_sst_miso_arr
|
miso_arr => ram_st_sst_miso_arr
|
);
|
);
|
|
|
stat_reg_im : ENTITY common_ram_lib.common_ram_crw_crw_ratio
|
stat_reg_im : ENTITY astron_ram_lib.common_ram_crw_crw_ratio
|
GENERIC MAP (
|
GENERIC MAP (
|
g_technology => g_technology,
|
g_technology => g_technology,
|
g_ram_a => c_mm_ram,
|
g_ram_a => c_mm_ram,
|
g_ram_b => c_stat_ram,
|
g_ram_b => c_stat_ram,
|
g_init_file => "UNUSED"
|
g_init_file => "UNUSED"
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
rst_a => mm_rst,
|
rst_a => mm_rst,
|
clk_a => mm_clk,
|
clk_a => mm_clk,
|
|
|
rst_b => dp_rst,
|
rst_b => dp_rst,
|
clk_b => dp_clk,
|
clk_b => dp_clk,
|
|
|
wr_en_a => ram_st_sst_mosi_arr(1).wr, -- only for diagnostic purposes, typically statistics are read only
|
wr_en_a => ram_st_sst_mosi_arr(1).wr, -- only for diagnostic purposes, typically statistics are read only
|
wr_dat_a => ram_st_sst_mosi_arr(1).wrdata(c_mm_ram.dat_w-1 DOWNTO 0),
|
wr_dat_a => ram_st_sst_mosi_arr(1).wrdata(c_mm_ram.dat_w-1 DOWNTO 0),
|
adr_a => ram_st_sst_mosi_arr(1).address(c_mm_ram.adr_w-1 DOWNTO 0),
|
adr_a => ram_st_sst_mosi_arr(1).address(c_mm_ram.adr_w-1 DOWNTO 0),
|
rd_en_a => ram_st_sst_mosi_arr(1).rd,
|
rd_en_a => ram_st_sst_mosi_arr(1).rd,
|
rd_dat_a => ram_st_sst_miso_arr(1).rddata(c_mm_ram.dat_w-1 DOWNTO 0),
|
rd_dat_a => ram_st_sst_miso_arr(1).rddata(c_mm_ram.dat_w-1 DOWNTO 0),
|
rd_val_a => ram_st_sst_miso_arr(1).rdval,
|
rd_val_a => ram_st_sst_miso_arr(1).rdval,
|
|
|
wr_en_b => stat_mosi.wr,
|
wr_en_b => stat_mosi.wr,
|
wr_dat_b => wrdata_im(c_stat_ram.dat_w-1 DOWNTO 0),
|
wr_dat_b => wrdata_im(c_stat_ram.dat_w-1 DOWNTO 0),
|
adr_b => stat_mosi.address(c_stat_ram.adr_w-1 DOWNTO 0),
|
adr_b => stat_mosi.address(c_stat_ram.adr_w-1 DOWNTO 0),
|
rd_en_b => '0',
|
rd_en_b => '0',
|
rd_dat_b => OPEN,
|
rd_dat_b => OPEN,
|
rd_val_b => OPEN
|
rd_val_b => OPEN
|
);
|
);
|
|
|
END GENERATE;
|
END GENERATE;
|
|
|
END str;
|
END str;
|
|
|