--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--
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--
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-- Copyright 2020
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- You may obtain a copy of the License at
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--
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--
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--
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-- Purpose: The fft_r2_bf_par describes a parallel complex butterfly.
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-- Purpose: The fft_r2_bf_par describes a parallel complex butterfly.
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--
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--
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-- Description: Output x is defined as x+y
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-- Description: Output x is defined as x+y
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-- Output y is defined as (x-y)*W
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-- Output y is defined as (x-y)*W
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--
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--
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--
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--
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-- Remarks:
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-- Remarks:
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--
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--
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library ieee, common_pkg_lib, common_components_lib, common_requantize_lib, rTwoSDF_lib;
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library ieee, common_pkg_lib, common_components_lib, astron_requantize_lib, astron_r2sdf_fft_lib;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use common_pkg_lib.common_pkg.all;
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use common_pkg_lib.common_pkg.all;
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use common_pkg_lib.common_str_pkg.all;
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use common_pkg_lib.common_str_pkg.all;
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use rTwoSDF_lib.twiddlesPkg.all;
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use astron_r2sdf_fft_lib.twiddlesPkg.all;
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use rTwoSDF_lib.rTwoSDFPkg.all;
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use astron_r2sdf_fft_lib.rTwoSDFPkg.all;
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use work.fft_pkg.all;
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use work.fft_pkg.all;
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|
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entity fft_r2_bf_par is
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entity fft_r2_bf_par is
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generic (
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generic (
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g_stage : natural := 3;
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g_stage : natural := 3;
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g_element : natural := 1;
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g_element : natural := 1;
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g_scale_enable : boolean := TRUE;
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g_scale_enable : boolean := TRUE;
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-- internal pipeline settings
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-- internal pipeline settings
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g_pipeline : t_fft_pipeline := c_fft_pipeline -- defined in rTwoSDF_lib.rTwoSDFPkg
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g_pipeline : t_fft_pipeline := c_fft_pipeline -- defined in astron_r2sdf_fft_lib.rTwoSDFPkg
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);
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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x_in_re : in std_logic_vector;
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x_in_re : in std_logic_vector;
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x_in_im : in std_logic_vector;
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x_in_im : in std_logic_vector;
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y_in_re : in std_logic_vector;
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y_in_re : in std_logic_vector;
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y_in_im : in std_logic_vector;
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y_in_im : in std_logic_vector;
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in_val : in std_logic;
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in_val : in std_logic;
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x_out_re : out std_logic_vector;
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x_out_re : out std_logic_vector;
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x_out_im : out std_logic_vector;
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x_out_im : out std_logic_vector;
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y_out_re : out std_logic_vector;
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y_out_re : out std_logic_vector;
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y_out_im : out std_logic_vector;
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y_out_im : out std_logic_vector;
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out_val : out std_logic
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out_val : out std_logic
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);
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);
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end entity fft_r2_bf_par;
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end entity fft_r2_bf_par;
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architecture str of fft_r2_bf_par is
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architecture str of fft_r2_bf_par is
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-- The amplification factor per stage is 2, therefor bit growth defintion of 1.
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-- The amplification factor per stage is 2, therefor bit growth defintion of 1.
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-- Scale enable is defined by generic.
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-- Scale enable is defined by generic.
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constant c_stage_bit_growth : natural := sel_a_b(g_scale_enable, 1, 0);
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constant c_stage_bit_growth : natural := sel_a_b(g_scale_enable, 1, 0);
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constant c_out_dat_w : natural := x_out_re'length; -- re and im have same width
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constant c_out_dat_w : natural := x_out_re'length; -- re and im have same width
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constant c_bf_in_a_zdly : natural := 0; -- No delays in bf_stage, since they only apply to one in- or output
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constant c_bf_in_a_zdly : natural := 0; -- No delays in bf_stage, since they only apply to one in- or output
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constant c_bf_out_b_zdly : natural := 0; -- No delays in bf_stage, since they only apply to one in- or output
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constant c_bf_out_b_zdly : natural := 0; -- No delays in bf_stage, since they only apply to one in- or output
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signal sum_re : std_logic_vector(x_out_re'range);
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signal sum_re : std_logic_vector(x_out_re'range);
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signal sum_im : std_logic_vector(x_out_im'range);
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signal sum_im : std_logic_vector(x_out_im'range);
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signal sum_quant_re : std_logic_vector(x_out_re'range);
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signal sum_quant_re : std_logic_vector(x_out_re'range);
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signal sum_quant_im : std_logic_vector(x_out_im'range);
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signal sum_quant_im : std_logic_vector(x_out_im'range);
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signal dif_re : std_logic_vector(y_out_re'range);
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signal dif_re : std_logic_vector(y_out_re'range);
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signal dif_im : std_logic_vector(y_out_im'range);
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signal dif_im : std_logic_vector(y_out_im'range);
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signal dif_out_re : std_logic_vector(y_out_re'range);
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signal dif_out_re : std_logic_vector(y_out_re'range);
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signal dif_out_im : std_logic_vector(y_out_im'range);
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signal dif_out_im : std_logic_vector(y_out_im'range);
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signal bf_sum_complex : std_logic_vector(c_nof_complex*c_out_dat_w-1 downto 0);
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signal bf_sum_complex : std_logic_vector(c_nof_complex*c_out_dat_w-1 downto 0);
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signal bf_sum_complex_dly : std_logic_vector(bf_sum_complex'range);
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signal bf_sum_complex_dly : std_logic_vector(bf_sum_complex'range);
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signal bf_dif_complex : std_logic_vector(c_nof_complex*c_out_dat_w-1 downto 0);
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signal bf_dif_complex : std_logic_vector(c_nof_complex*c_out_dat_w-1 downto 0);
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signal bf_dif_complex_dly : std_logic_vector(bf_dif_complex'range);
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signal bf_dif_complex_dly : std_logic_vector(bf_dif_complex'range);
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signal weight_addr : std_logic_vector(g_stage-1 downto 1);
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signal weight_addr : std_logic_vector(g_stage-1 downto 1);
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signal weight_re : wTyp;
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signal weight_re : wTyp;
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signal weight_im : wTyp;
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signal weight_im : wTyp;
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signal mul_out_re : std_logic_vector(y_out_re'range);
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signal mul_out_re : std_logic_vector(y_out_re'range);
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signal mul_out_im : std_logic_vector(y_out_im'range);
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signal mul_out_im : std_logic_vector(y_out_im'range);
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signal mul_quant_re : std_logic_vector(y_out_re'range);
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signal mul_quant_re : std_logic_vector(y_out_re'range);
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signal mul_quant_im : std_logic_vector(y_out_im'range);
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signal mul_quant_im : std_logic_vector(y_out_im'range);
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signal mul_out_val : std_logic;
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signal mul_out_val : std_logic;
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signal mul_in_val : std_logic;
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signal mul_in_val : std_logic;
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begin
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begin
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- complex butterfly
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-- complex butterfly
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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u_bf_re : entity rTwoSDF_lib.rTwoBF
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u_bf_re : entity astron_r2sdf_fft_lib.rTwoBF
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generic map (
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generic map (
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g_in_a_zdly => c_bf_in_a_zdly,
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g_in_a_zdly => c_bf_in_a_zdly,
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g_out_d_zdly => c_bf_out_b_zdly
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g_out_d_zdly => c_bf_out_b_zdly
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)
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)
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port map (
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port map (
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clk => clk,
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clk => clk,
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in_a => x_in_re,
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in_a => x_in_re,
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in_b => y_in_re,
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in_b => y_in_re,
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in_sel => '1',
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in_sel => '1',
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in_val => in_val,
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in_val => in_val,
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out_c => sum_re,
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out_c => sum_re,
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out_d => dif_re
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out_d => dif_re
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);
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);
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u_bf_im : entity rTwoSDF_lib.rTwoBF
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u_bf_im : entity astron_r2sdf_fft_lib.rTwoBF
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generic map (
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generic map (
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g_in_a_zdly => c_bf_in_a_zdly,
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g_in_a_zdly => c_bf_in_a_zdly,
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g_out_d_zdly => c_bf_out_b_zdly
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g_out_d_zdly => c_bf_out_b_zdly
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)
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)
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port map (
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port map (
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clk => clk,
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clk => clk,
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in_a => x_in_im,
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in_a => x_in_im,
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in_b => y_in_im,
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in_b => y_in_im,
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in_sel => '1',
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in_sel => '1',
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in_val => in_val,
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in_val => in_val,
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out_c => sum_im,
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out_c => sum_im,
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out_d => dif_im
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out_d => dif_im
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);
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);
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- requantize x output
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-- requantize x output
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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u_requantize_x_re : entity common_requantize_lib.common_requantize
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u_requantize_x_re : entity astron_requantize_lib.common_requantize
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generic map (
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generic map (
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g_representation => "SIGNED",
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g_representation => "SIGNED",
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g_lsb_w => c_stage_bit_growth,
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g_lsb_w => c_stage_bit_growth,
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g_lsb_round => TRUE,
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g_lsb_round => TRUE,
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g_lsb_round_clip => FALSE,
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g_lsb_round_clip => FALSE,
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g_msb_clip => FALSE,
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g_msb_clip => FALSE,
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g_msb_clip_symmetric => FALSE,
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g_msb_clip_symmetric => FALSE,
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g_pipeline_remove_lsb => 0,
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g_pipeline_remove_lsb => 0,
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g_pipeline_remove_msb => 0,
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g_pipeline_remove_msb => 0,
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g_in_dat_w => sum_re'LENGTH,
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g_in_dat_w => sum_re'LENGTH,
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g_out_dat_w => sum_quant_re'LENGTH
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g_out_dat_w => sum_quant_re'LENGTH
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)
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)
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port map (
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port map (
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clk => clk,
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clk => clk,
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clken => '1',
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clken => '1',
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in_dat => sum_re,
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in_dat => sum_re,
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out_dat => sum_quant_re,
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out_dat => sum_quant_re,
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out_ovr => open
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out_ovr => open
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);
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);
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u_requantize_x_im : entity common_requantize_lib.common_requantize
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u_requantize_x_im : entity astron_requantize_lib.common_requantize
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generic map (
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generic map (
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g_representation => "SIGNED",
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g_representation => "SIGNED",
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g_lsb_w => c_stage_bit_growth,
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g_lsb_w => c_stage_bit_growth,
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g_lsb_round => TRUE,
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g_lsb_round => TRUE,
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g_lsb_round_clip => FALSE,
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g_lsb_round_clip => FALSE,
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g_msb_clip => FALSE,
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g_msb_clip => FALSE,
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g_msb_clip_symmetric => FALSE,
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g_msb_clip_symmetric => FALSE,
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g_pipeline_remove_lsb => 0,
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g_pipeline_remove_lsb => 0,
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g_pipeline_remove_msb => 0,
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g_pipeline_remove_msb => 0,
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g_in_dat_w => sum_im'LENGTH,
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g_in_dat_w => sum_im'LENGTH,
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g_out_dat_w => sum_quant_im'LENGTH
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g_out_dat_w => sum_quant_im'LENGTH
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)
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)
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port map (
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port map (
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clk => clk,
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clk => clk,
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clken => '1',
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clken => '1',
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in_dat => sum_im,
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in_dat => sum_im,
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out_dat => sum_quant_im,
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out_dat => sum_quant_im,
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out_ovr => open
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out_ovr => open
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);
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);
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Butterfly output pipelining: the sum output (output C)
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-- Butterfly output pipelining: the sum output (output C)
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--
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--
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-- The instantiated pipeline for the sum output takes into account the
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-- The instantiated pipeline for the sum output takes into account the
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-- bf_lat + mul_lat + stage_lat. Output of the pipeline is directly connected
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-- bf_lat + mul_lat + stage_lat. Output of the pipeline is directly connected
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-- to the output.
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-- to the output.
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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bf_sum_complex <= sum_quant_im & sum_quant_re;
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bf_sum_complex <= sum_quant_im & sum_quant_re;
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u_pipeline_sum : entity common_components_lib.common_pipeline
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u_pipeline_sum : entity common_components_lib.common_pipeline
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generic map (
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generic map (
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g_pipeline => g_pipeline.bf_lat + g_pipeline.mul_lat + g_pipeline.stage_lat,
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g_pipeline => g_pipeline.bf_lat + g_pipeline.mul_lat + g_pipeline.stage_lat,
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g_in_dat_w => bf_sum_complex'length,
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g_in_dat_w => bf_sum_complex'length,
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g_out_dat_w => bf_sum_complex'length
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g_out_dat_w => bf_sum_complex'length
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)
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)
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port map (
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port map (
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clk => clk,
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clk => clk,
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in_dat => bf_sum_complex,
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in_dat => bf_sum_complex,
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out_dat => bf_sum_complex_dly
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out_dat => bf_sum_complex_dly
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);
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);
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-- connect to the output.
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-- connect to the output.
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x_out_re <= bf_sum_complex_dly( c_out_dat_w-1 downto 0);
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x_out_re <= bf_sum_complex_dly( c_out_dat_w-1 downto 0);
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x_out_im <= bf_sum_complex_dly(2*c_out_dat_w-1 downto c_out_dat_w);
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x_out_im <= bf_sum_complex_dly(2*c_out_dat_w-1 downto c_out_dat_w);
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Butterfly output pipelining: the dif output (output D)
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-- Butterfly output pipelining: the dif output (output D)
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--
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--
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-- The dif output requires only the bf_lat pipelining. The data of the dif
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-- The dif output requires only the bf_lat pipelining. The data of the dif
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-- output is than fed to the multiplier.
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-- output is than fed to the multiplier.
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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bf_dif_complex <= dif_im & dif_re;
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bf_dif_complex <= dif_im & dif_re;
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u_pipeline_dif : entity common_components_lib.common_pipeline
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u_pipeline_dif : entity common_components_lib.common_pipeline
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generic map (
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generic map (
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g_pipeline => g_pipeline.bf_lat,
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g_pipeline => g_pipeline.bf_lat,
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g_in_dat_w => bf_dif_complex'length,
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g_in_dat_w => bf_dif_complex'length,
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g_out_dat_w => bf_dif_complex'length
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g_out_dat_w => bf_dif_complex'length
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)
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)
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port map (
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port map (
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clk => clk,
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clk => clk,
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in_dat => bf_dif_complex,
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in_dat => bf_dif_complex,
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out_dat => bf_dif_complex_dly
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out_dat => bf_dif_complex_dly
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);
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);
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|
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dif_out_re <= bf_dif_complex_dly( c_out_dat_w-1 downto 0);
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dif_out_re <= bf_dif_complex_dly( c_out_dat_w-1 downto 0);
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dif_out_im <= bf_dif_complex_dly(2*c_out_dat_w-1 downto c_out_dat_w);
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dif_out_im <= bf_dif_complex_dly(2*c_out_dat_w-1 downto c_out_dat_w);
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|
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- In_valid pipelining. The in_val signal must be pipelined for bf_lat cycles
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-- In_valid pipelining. The in_val signal must be pipelined for bf_lat cycles
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-- before it drives to the multiplier.
|
-- before it drives to the multiplier.
|
------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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u_val_bf_lat : entity common_components_lib.common_pipeline_sl
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u_val_bf_lat : entity common_components_lib.common_pipeline_sl
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generic map (
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generic map (
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g_pipeline => g_pipeline.bf_lat
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g_pipeline => g_pipeline.bf_lat
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)
|
)
|
port map (
|
port map (
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clk => clk,
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clk => clk,
|
in_dat => in_val,
|
in_dat => in_val,
|
out_dat => mul_in_val
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out_dat => mul_in_val
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);
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);
|
|
|
------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- twiddle multiplication
|
-- twiddle multiplication
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
u_TwiddleMult: entity rTwoSDF_lib.rTwoWMul
|
u_TwiddleMult: entity astron_r2sdf_fft_lib.rTwoWMul
|
generic map (
|
generic map (
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g_stage => g_stage,
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g_stage => g_stage,
|
g_lat => g_pipeline.mul_lat
|
g_lat => g_pipeline.mul_lat
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)
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)
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
weight_re => weight_re,
|
weight_re => weight_re,
|
weight_im => weight_im,
|
weight_im => weight_im,
|
in_re => dif_out_re,
|
in_re => dif_out_re,
|
in_im => dif_out_im,
|
in_im => dif_out_im,
|
in_val => mul_in_val,
|
in_val => mul_in_val,
|
in_sel => '1', -- Always select the multiplier output
|
in_sel => '1', -- Always select the multiplier output
|
out_re => mul_out_re,
|
out_re => mul_out_re,
|
out_im => mul_out_im,
|
out_im => mul_out_im,
|
out_val => mul_out_val
|
out_val => mul_out_val
|
);
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);
|
|
|
weight_re <= wRe(wMap(g_element, g_stage));
|
weight_re <= wRe(wMap(g_element, g_stage));
|
weight_im <= wIm(wMap(g_element, g_stage));
|
weight_im <= wIm(wMap(g_element, g_stage));
|
|
|
print_str("Parallel: [stage = " & integer'image(g_stage) & " [element = " & integer'image(g_element) & "] " & "[index = " & integer'image(wMap(g_element, g_stage)) & "] " );
|
print_str("Parallel: [stage = " & integer'image(g_stage) & " [element = " & integer'image(g_element) & "] " & "[index = " & integer'image(wMap(g_element, g_stage)) & "] " );
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- requantize y output
|
-- requantize y output
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
u_requantize_y_re : entity common_requantize_lib.common_requantize
|
u_requantize_y_re : entity astron_requantize_lib.common_requantize
|
generic map (
|
generic map (
|
g_representation => "SIGNED",
|
g_representation => "SIGNED",
|
g_lsb_w => c_stage_bit_growth,
|
g_lsb_w => c_stage_bit_growth,
|
g_lsb_round => TRUE,
|
g_lsb_round => TRUE,
|
g_lsb_round_clip => FALSE,
|
g_lsb_round_clip => FALSE,
|
g_msb_clip => FALSE,
|
g_msb_clip => FALSE,
|
g_msb_clip_symmetric => FALSE,
|
g_msb_clip_symmetric => FALSE,
|
g_pipeline_remove_lsb => 0,
|
g_pipeline_remove_lsb => 0,
|
g_pipeline_remove_msb => 0,
|
g_pipeline_remove_msb => 0,
|
g_in_dat_w => mul_out_re'LENGTH,
|
g_in_dat_w => mul_out_re'LENGTH,
|
g_out_dat_w => mul_quant_re'LENGTH
|
g_out_dat_w => mul_quant_re'LENGTH
|
)
|
)
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
clken => '1',
|
clken => '1',
|
in_dat => mul_out_re,
|
in_dat => mul_out_re,
|
out_dat => mul_quant_re,
|
out_dat => mul_quant_re,
|
out_ovr => open
|
out_ovr => open
|
);
|
);
|
|
|
u_requantize_y_im : entity common_requantize_lib.common_requantize
|
u_requantize_y_im : entity astron_requantize_lib.common_requantize
|
generic map (
|
generic map (
|
g_representation => "SIGNED",
|
g_representation => "SIGNED",
|
g_lsb_w => c_stage_bit_growth,
|
g_lsb_w => c_stage_bit_growth,
|
g_lsb_round => TRUE,
|
g_lsb_round => TRUE,
|
g_lsb_round_clip => FALSE,
|
g_lsb_round_clip => FALSE,
|
g_msb_clip => FALSE,
|
g_msb_clip => FALSE,
|
g_msb_clip_symmetric => FALSE,
|
g_msb_clip_symmetric => FALSE,
|
g_pipeline_remove_lsb => 0,
|
g_pipeline_remove_lsb => 0,
|
g_pipeline_remove_msb => 0,
|
g_pipeline_remove_msb => 0,
|
g_in_dat_w => mul_out_im'LENGTH,
|
g_in_dat_w => mul_out_im'LENGTH,
|
g_out_dat_w => mul_quant_im'LENGTH
|
g_out_dat_w => mul_quant_im'LENGTH
|
)
|
)
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
clken => '1',
|
clken => '1',
|
in_dat => mul_out_im,
|
in_dat => mul_out_im,
|
out_dat => mul_quant_im,
|
out_dat => mul_quant_im,
|
out_ovr => open
|
out_ovr => open
|
);
|
);
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- output
|
-- output
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
u_y_re_stage_lat : entity common_components_lib.common_pipeline
|
u_y_re_stage_lat : entity common_components_lib.common_pipeline
|
generic map (
|
generic map (
|
g_pipeline => g_pipeline.stage_lat,
|
g_pipeline => g_pipeline.stage_lat,
|
g_in_dat_w => mul_quant_re'LENGTH,
|
g_in_dat_w => mul_quant_re'LENGTH,
|
g_out_dat_w => y_out_re'LENGTH
|
g_out_dat_w => y_out_re'LENGTH
|
)
|
)
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
in_dat => mul_quant_re,
|
in_dat => mul_quant_re,
|
out_dat => y_out_re
|
out_dat => y_out_re
|
);
|
);
|
|
|
u_y_im_stage_lat : entity common_components_lib.common_pipeline
|
u_y_im_stage_lat : entity common_components_lib.common_pipeline
|
generic map (
|
generic map (
|
g_pipeline => g_pipeline.stage_lat,
|
g_pipeline => g_pipeline.stage_lat,
|
g_in_dat_w => mul_quant_im'LENGTH,
|
g_in_dat_w => mul_quant_im'LENGTH,
|
g_out_dat_w => y_out_im'LENGTH
|
g_out_dat_w => y_out_im'LENGTH
|
)
|
)
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
in_dat => mul_quant_im,
|
in_dat => mul_quant_im,
|
out_dat => y_out_im
|
out_dat => y_out_im
|
);
|
);
|
|
|
u_val_stage_lat : entity common_components_lib.common_pipeline_sl
|
u_val_stage_lat : entity common_components_lib.common_pipeline_sl
|
generic map (
|
generic map (
|
g_pipeline => g_pipeline.stage_lat
|
g_pipeline => g_pipeline.stage_lat
|
)
|
)
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
in_dat => mul_out_val,
|
in_dat => mul_out_val,
|
out_dat => out_val
|
out_dat => out_val
|
);
|
);
|
|
|
end str;
|
end str;
|
|
|