--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--
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--
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-- Copyright 2020
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- You may obtain a copy of the License at
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--
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--
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--
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-- Purpose: The fft_sepa_wide unit performs the separate function on the
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-- Purpose: The fft_sepa_wide unit performs the separate function on the
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-- output of a complex wideband fft in order to extract the spectrum
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-- output of a complex wideband fft in order to extract the spectrum
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-- of the two real inputs A and B. Where A was fed to the real input
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-- of the two real inputs A and B. Where A was fed to the real input
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-- of the complext wfft and B was fed to the imaginary input.
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-- of the complext wfft and B was fed to the imaginary input.
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--
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--
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--
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--
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-- Description: The incoming data is stored in a dual paged ram. For each output
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-- Description: The incoming data is stored in a dual paged ram. For each output
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-- of the complex wfft a unique dual paged ram is instantiated. Once
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-- of the complex wfft a unique dual paged ram is instantiated. Once
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-- the first page is written, the unit will read the data from the
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-- the first page is written, the unit will read the data from the
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-- memory.
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-- memory.
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-- The read process reads the memories in such a way that pairs of
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-- The read process reads the memories in such a way that pairs of
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-- data are created that are required to generate the correct outputs.
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-- data are created that are required to generate the correct outputs.
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-- The data pairs are offered to the ZIP units that serialize the pairs.
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-- The data pairs are offered to the ZIP units that serialize the pairs.
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-- The serialized data is then offered to the separate units that outputs
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-- The serialized data is then offered to the separate units that outputs
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-- the separated data in an interleaved stream: A, B, A, B etc (for both real and imaginary part)
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-- the separated data in an interleaved stream: A, B, A, B etc (for both real and imaginary part)
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-- The last stage contains pipeline stages that are required for allignment
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-- The last stage contains pipeline stages that are required for allignment
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-- and additional pipeling.
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-- and additional pipeling.
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--
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--
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library ieee, common_pkg_lib, common_counter_lib, common_components_lib, common_ram_lib, common_multiplexer_lib;
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library ieee, common_pkg_lib, astron_counter_lib, common_components_lib, astron_ram_lib, astron_multiplexer_lib;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use common_pkg_lib.common_pkg.all;
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use common_pkg_lib.common_pkg.all;
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use work.fft_pkg.all;
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use work.fft_pkg.all;
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entity fft_sepa_wide is
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entity fft_sepa_wide is
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generic (
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generic (
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g_fft : t_fft := c_fft -- generics for the FFT
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g_fft : t_fft := c_fft -- generics for the FFT
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);
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic := '0';
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rst : in std_logic := '0';
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in_re_arr : in t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
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in_re_arr : in t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
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in_im_arr : in t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
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in_im_arr : in t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
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in_val : in std_logic := '1';
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in_val : in std_logic := '1';
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out_re_arr : out t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
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out_re_arr : out t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
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out_im_arr : out t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
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out_im_arr : out t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
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out_val : out std_logic
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out_val : out std_logic
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);
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);
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end entity fft_sepa_wide;
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end entity fft_sepa_wide;
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architecture rtl of fft_sepa_wide is
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architecture rtl of fft_sepa_wide is
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constant c_pipeline_output : natural := 0; -- no need for extra pipeline output, because output is already registered
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constant c_pipeline_output : natural := 0; -- no need for extra pipeline output, because output is already registered
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constant c_page_size : natural := g_fft.nof_points/g_fft.wb_factor; -- Size of the memories
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constant c_page_size : natural := g_fft.nof_points/g_fft.wb_factor; -- Size of the memories
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constant c_nof_pages : natural := 2; -- The number of pages in each ram.
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constant c_nof_pages : natural := 2; -- The number of pages in each ram.
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constant c_dat_w : natural := c_nof_complex*g_fft.stage_dat_w; -- Data width for the internal vectors where real and imag are combined.
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constant c_dat_w : natural := c_nof_complex*g_fft.stage_dat_w; -- Data width for the internal vectors where real and imag are combined.
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constant c_adr_w : natural := ceil_log2(c_page_size); -- Address width of the rams
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constant c_adr_w : natural := ceil_log2(c_page_size); -- Address width of the rams
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constant c_nof_streams : natural := 2; -- Number of inputstreams for the zip units
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constant c_nof_streams : natural := 2; -- Number of inputstreams for the zip units
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type t_dat_arr is array(integer range <> ) of std_logic_vector(c_dat_w-1 downto 0);
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type t_dat_arr is array(integer range <> ) of std_logic_vector(c_dat_w-1 downto 0);
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type t_rd_adr_arr is array(integer range <> ) of std_logic_vector(c_adr_w-1 downto 0);
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type t_rd_adr_arr is array(integer range <> ) of std_logic_vector(c_adr_w-1 downto 0);
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type t_zip_in_matrix is array(integer range <> ) of t_slv_64_arr(1 downto 0); -- Every Zip unit has two inputs.
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type t_zip_in_matrix is array(integer range <> ) of t_slv_64_arr(1 downto 0); -- Every Zip unit has two inputs.
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signal next_page : std_logic; -- Active high signal to force a page-swap in the memories
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signal next_page : std_logic; -- Active high signal to force a page-swap in the memories
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signal wr_en : std_logic; -- The write enable signal for the memories
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signal wr_en : std_logic; -- The write enable signal for the memories
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signal wr_adr : std_logic_vector(c_adr_w-1 downto 0); -- The write address
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signal wr_adr : std_logic_vector(c_adr_w-1 downto 0); -- The write address
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signal wr_dat : t_dat_arr(g_fft.wb_factor-1 downto 0); -- Array of data to be written to memory
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signal wr_dat : t_dat_arr(g_fft.wb_factor-1 downto 0); -- Array of data to be written to memory
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signal rd_dat_arr : t_dat_arr(g_fft.wb_factor-1 downto 0); -- Array of data that is read from memory
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signal rd_dat_arr : t_dat_arr(g_fft.wb_factor-1 downto 0); -- Array of data that is read from memory
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signal rd_adr_arr : t_rd_adr_arr(1 downto 0); -- There are two different read addresses.
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signal rd_adr_arr : t_rd_adr_arr(1 downto 0); -- There are two different read addresses.
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signal zip_in_matrix : t_zip_in_matrix(g_fft.wb_factor-1 downto 0); -- Matrix that contains the inputs for zip units
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signal zip_in_matrix : t_zip_in_matrix(g_fft.wb_factor-1 downto 0); -- Matrix that contains the inputs for zip units
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signal zip_in_val : std_logic_vector(g_fft.wb_factor-1 downto 0); -- Vector that holds the data input valids for the zip units
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signal zip_in_val : std_logic_vector(g_fft.wb_factor-1 downto 0); -- Vector that holds the data input valids for the zip units
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signal zip_out_dat_arr : t_dat_arr(g_fft.wb_factor-1 downto 0); -- Array that holds the outputs of all zip units.
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signal zip_out_dat_arr : t_dat_arr(g_fft.wb_factor-1 downto 0); -- Array that holds the outputs of all zip units.
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signal zip_out_val : std_logic_vector(g_fft.wb_factor-1 downto 0); -- Vector that holds the output valids of the zip units
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signal zip_out_val : std_logic_vector(g_fft.wb_factor-1 downto 0); -- Vector that holds the output valids of the zip units
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signal sep_out_dat_arr : t_dat_arr(g_fft.wb_factor-1 downto 0); -- Array that holds the outputs of the separation blocks
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signal sep_out_dat_arr : t_dat_arr(g_fft.wb_factor-1 downto 0); -- Array that holds the outputs of the separation blocks
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signal sep_out_val_vec : std_logic_vector(g_fft.wb_factor-1 downto 0); -- Vector containing the datavalids from the separation blocks
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signal sep_out_val_vec : std_logic_vector(g_fft.wb_factor-1 downto 0); -- Vector containing the datavalids from the separation blocks
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signal out_dat_arr : t_dat_arr(g_fft.wb_factor-1 downto 0); -- Array that holds the ouput values, where real and imag are concatenated
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signal out_dat_arr : t_dat_arr(g_fft.wb_factor-1 downto 0); -- Array that holds the ouput values, where real and imag are concatenated
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type state_type is (s_idle, s_read);
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type state_type is (s_idle, s_read);
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type reg_type is record
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type reg_type is record
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switch : std_logic; -- Toggle register used for separate functionalilty
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switch : std_logic; -- Toggle register used for separate functionalilty
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count_up : natural range 0 to c_page_size; -- An upwards counter for read addressing
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count_up : natural range 0 to c_page_size; -- An upwards counter for read addressing
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count_down : natural range 0 to c_page_size; -- A downwards counter for read addressing
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count_down : natural range 0 to c_page_size; -- A downwards counter for read addressing
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val_odd : std_logic; -- Register that drives the in_valid of the odd zip units
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val_odd : std_logic; -- Register that drives the in_valid of the odd zip units
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val_even : std_logic; -- Register that drives the in_valid of the even zip units
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val_even : std_logic; -- Register that drives the in_valid of the even zip units
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state : state_type; -- The state machine.
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state : state_type; -- The state machine.
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end record;
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end record;
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signal r, rin : reg_type;
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signal r, rin : reg_type;
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begin
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begin
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---------------------------------------------------------------
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---------------------------------------------------------------
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-- DUAL PAGED RAMS
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-- DUAL PAGED RAMS
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---------------------------------------------------------------
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---------------------------------------------------------------
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-- Prepare the data for the dual paged memory. Real and imaginary part are concatenated into one vector.
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-- Prepare the data for the dual paged memory. Real and imaginary part are concatenated into one vector.
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gen_prep_write_data : for I in 0 to g_fft.wb_factor-1 generate
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gen_prep_write_data : for I in 0 to g_fft.wb_factor-1 generate
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wr_dat(I) <= in_im_arr(I)(g_fft.stage_dat_w-1 downto 0) & in_re_arr(I)(g_fft.stage_dat_w-1 downto 0);
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wr_dat(I) <= in_im_arr(I)(g_fft.stage_dat_w-1 downto 0) & in_re_arr(I)(g_fft.stage_dat_w-1 downto 0);
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end generate;
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end generate;
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-- Prepare the write control signals for the memories.
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-- Prepare the write control signals for the memories.
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wr_en <= in_val;
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wr_en <= in_val;
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next_page <= '1' when unsigned(wr_adr) = c_page_size-1 and wr_en='1' else '0';
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next_page <= '1' when unsigned(wr_adr) = c_page_size-1 and wr_en='1' else '0';
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-- Counter will generate the write address
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-- Counter will generate the write address
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u_wr_adr_cnt : entity common_counter_lib.common_counter
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u_wr_adr_cnt : entity astron_counter_lib.common_counter
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generic map(
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generic map(
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g_latency => 1,
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g_latency => 1,
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g_init => 0,
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g_init => 0,
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g_width => c_adr_w
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g_width => c_adr_w
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)
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)
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port map (
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port map (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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cnt_en => in_val,
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cnt_en => in_val,
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count => wr_adr
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count => wr_adr
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);
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);
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-- Instantiation of the rams.
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-- Instantiation of the rams.
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gen_dual_paged_rams : for I in g_fft.wb_factor - 1 downto 0 generate
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gen_dual_paged_rams : for I in g_fft.wb_factor - 1 downto 0 generate
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u_buff : entity common_ram_lib.common_paged_ram_r_w
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u_buff : entity astron_ram_lib.common_paged_ram_r_w
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generic map (
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generic map (
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g_str => "use_adr",
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g_str => "use_adr",
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g_data_w => c_dat_w,
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g_data_w => c_dat_w,
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g_nof_pages => c_nof_pages,
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g_nof_pages => c_nof_pages,
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g_page_sz => c_page_size,
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g_page_sz => c_page_size,
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g_wr_start_page => 0,
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g_wr_start_page => 0,
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g_rd_start_page => 1,
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g_rd_start_page => 1,
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g_rd_latency => 1
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g_rd_latency => 1
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)
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)
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port map (
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port map (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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wr_next_page => next_page,
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wr_next_page => next_page,
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wr_adr => wr_adr,
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wr_adr => wr_adr,
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wr_en => wr_en,
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wr_en => wr_en,
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wr_dat => wr_dat(I),
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wr_dat => wr_dat(I),
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rd_next_page => next_page,
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rd_next_page => next_page,
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rd_adr => rd_adr_arr(I/(g_fft.wb_factor/2)),
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rd_adr => rd_adr_arr(I/(g_fft.wb_factor/2)),
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rd_en => '1',
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rd_en => '1',
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rd_dat => rd_dat_arr(I),
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rd_dat => rd_dat_arr(I),
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rd_val => open
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rd_val => open
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);
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);
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end generate;
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end generate;
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-- Compose the read-addresses for the memories.
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-- Compose the read-addresses for the memories.
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-- The first address toggles between the value of count_up and the value of count_up + offset.
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-- The first address toggles between the value of count_up and the value of count_up + offset.
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-- The second address toggles between the value of count_down and the value of count_down + offset.
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-- The second address toggles between the value of count_down and the value of count_down + offset.
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-- Note that the RESIZE_UVEC function generates the modulo(N) addressing.(The MSB is thrown away).
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-- Note that the RESIZE_UVEC function generates the modulo(N) addressing.(The MSB is thrown away).
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rd_adr_arr(0) <= RESIZE_UVEC(TO_UVEC(r.count_up, c_adr_w+1), c_adr_w) when r.switch = '0' else RESIZE_UVEC(TO_UVEC(r.count_up + c_page_size/2, c_adr_w+1), c_adr_w);
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rd_adr_arr(0) <= RESIZE_UVEC(TO_UVEC(r.count_up, c_adr_w+1), c_adr_w) when r.switch = '0' else RESIZE_UVEC(TO_UVEC(r.count_up + c_page_size/2, c_adr_w+1), c_adr_w);
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rd_adr_arr(1) <= RESIZE_UVEC(TO_UVEC(r.count_down, c_adr_w+1), c_adr_w) when r.switch = '0' else RESIZE_UVEC(TO_UVEC(r.count_down + c_page_size/2, c_adr_w+1), c_adr_w);
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rd_adr_arr(1) <= RESIZE_UVEC(TO_UVEC(r.count_down, c_adr_w+1), c_adr_w) when r.switch = '0' else RESIZE_UVEC(TO_UVEC(r.count_down + c_page_size/2, c_adr_w+1), c_adr_w);
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---------------------------------------------------------------
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---------------------------------------------------------------
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-- ZIP UNITS AND SEPARATORS
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-- ZIP UNITS AND SEPARATORS
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---------------------------------------------------------------
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---------------------------------------------------------------
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-- Compose the input matrix for the zip units. Each zip unit receives the
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-- Compose the input matrix for the zip units. Each zip unit receives the
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-- data of two different memories at the same time in order to allign the data
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-- data of two different memories at the same time in order to allign the data
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-- properly (in serial) for the separation units. Every zip unit receives data
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-- properly (in serial) for the separation units. Every zip unit receives data
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-- once every two clock cylces.
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-- once every two clock cylces.
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gen_compose_zip_matrix : for I in g_fft.wb_factor/2 - 1 downto 0 generate
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gen_compose_zip_matrix : for I in g_fft.wb_factor/2 - 1 downto 0 generate
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zip_in_matrix(2*I)(0) (c_dat_w-1 downto 0) <= rd_dat_arr(I);
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zip_in_matrix(2*I)(0) (c_dat_w-1 downto 0) <= rd_dat_arr(I);
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zip_in_matrix(2*I)(1) (c_dat_w-1 downto 0) <= rd_dat_arr((g_fft.wb_factor-I) rem g_fft.wb_factor) when r.count_up = 0 else rd_dat_arr(g_fft.wb_factor-1-I);
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zip_in_matrix(2*I)(1) (c_dat_w-1 downto 0) <= rd_dat_arr((g_fft.wb_factor-I) rem g_fft.wb_factor) when r.count_up = 0 else rd_dat_arr(g_fft.wb_factor-1-I);
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zip_in_matrix(2*I+1)(0)(c_dat_w-1 downto 0) <= rd_dat_arr(I);
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zip_in_matrix(2*I+1)(0)(c_dat_w-1 downto 0) <= rd_dat_arr(I);
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zip_in_matrix(2*I+1)(1)(c_dat_w-1 downto 0) <= rd_dat_arr(g_fft.wb_factor-1-I);
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zip_in_matrix(2*I+1)(1)(c_dat_w-1 downto 0) <= rd_dat_arr(g_fft.wb_factor-1-I);
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zip_in_val(2*I) <= r.val_even;
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zip_in_val(2*I) <= r.val_even;
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zip_in_val(2*I+1) <= r.val_odd;
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zip_in_val(2*I+1) <= r.val_odd;
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end generate;
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end generate;
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-- The instantiation of the zip units and the separation units.
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-- The instantiation of the zip units and the separation units.
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-- The output of the zip units is connected to the input of the
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-- The output of the zip units is connected to the input of the
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-- adjacent separate unit.
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-- adjacent separate unit.
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gen_separators : for I in g_fft.wb_factor - 1 downto 0 generate
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gen_separators : for I in g_fft.wb_factor - 1 downto 0 generate
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u_zipper : entity common_multiplexer_lib.common_zip
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u_zipper : entity astron_multiplexer_lib.common_zip
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generic map (
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generic map (
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g_nof_streams => c_nof_streams,
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g_nof_streams => c_nof_streams,
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g_dat_w => c_dat_w
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g_dat_w => c_dat_w
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)
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)
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port map (
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port map (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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in_val => zip_in_val(I),
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in_val => zip_in_val(I),
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in_dat_arr => zip_in_matrix(I),
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in_dat_arr => zip_in_matrix(I),
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out_val => zip_out_val(I),
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out_val => zip_out_val(I),
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out_dat => zip_out_dat_arr(I)
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out_dat => zip_out_dat_arr(I)
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);
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);
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u_separate : entity work.fft_sepa
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u_separate : entity work.fft_sepa
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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in_dat => zip_out_dat_arr(I),
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in_dat => zip_out_dat_arr(I),
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in_val => zip_out_val(I),
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in_val => zip_out_val(I),
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out_dat => sep_out_dat_arr(I),
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out_dat => sep_out_dat_arr(I),
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out_val => sep_out_val_vec(I)
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out_val => sep_out_val_vec(I)
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);
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);
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end generate;
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end generate;
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|
|
---------------------------------------------------------------
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---------------------------------------------------------------
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-- READ MEMORIES PROCESS
|
-- READ MEMORIES PROCESS
|
---------------------------------------------------------------
|
---------------------------------------------------------------
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-- This process creates the read addresses for the dual page memories and
|
-- This process creates the read addresses for the dual page memories and
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-- the fellow toggle signals. It also controls the starting and stopping
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-- the fellow toggle signals. It also controls the starting and stopping
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-- of the data stream.
|
-- of the data stream.
|
comb : process(r, rst, next_page)
|
comb : process(r, rst, next_page)
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variable v : reg_type;
|
variable v : reg_type;
|
begin
|
begin
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|
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v := r;
|
v := r;
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|
|
case r.state is
|
case r.state is
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when s_idle =>
|
when s_idle =>
|
v.switch := '0';
|
v.switch := '0';
|
v.val_odd := '0';
|
v.val_odd := '0';
|
v.val_even := '0';
|
v.val_even := '0';
|
v.count_up := 0;
|
v.count_up := 0;
|
v.count_down := c_page_size;
|
v.count_down := c_page_size;
|
if(next_page = '1') then -- Check if next page is asserted, meaning first page is written)
|
if(next_page = '1') then -- Check if next page is asserted, meaning first page is written)
|
v.state := s_read;
|
v.state := s_read;
|
end if;
|
end if;
|
|
|
when s_read =>
|
when s_read =>
|
if(r.switch = '0') then -- Toggle the switch register from 0 to 1
|
if(r.switch = '0') then -- Toggle the switch register from 0 to 1
|
v.switch := '1';
|
v.switch := '1';
|
end if;
|
end if;
|
|
|
if(r.switch = '1') then -- Toggle the switch register from 1 to 0
|
if(r.switch = '1') then -- Toggle the switch register from 1 to 0
|
v.switch := '0';
|
v.switch := '0';
|
v.count_up := r.count_up + 1; -- Increment the upwards counter
|
v.count_up := r.count_up + 1; -- Increment the upwards counter
|
v.count_down := r.count_down - 1; -- Decrease the downwards counter
|
v.count_down := r.count_down - 1; -- Decrease the downwards counter
|
end if;
|
end if;
|
|
|
if(next_page = '1') then -- Both counters are reset on page turn.
|
if(next_page = '1') then -- Both counters are reset on page turn.
|
v.count_up := 0;
|
v.count_up := 0;
|
v.count_down := c_page_size;
|
v.count_down := c_page_size;
|
elsif(v.count_up = c_page_size/2) then -- Pagereading is done, but there is not yet new data available (Note that the value of variable v is checked here)
|
elsif(v.count_up = c_page_size/2) then -- Pagereading is done, but there is not yet new data available (Note that the value of variable v is checked here)
|
v.state := s_idle; -- then go back to idle.
|
v.state := s_idle; -- then go back to idle.
|
end if;
|
end if;
|
|
|
v.val_odd := r.switch; -- Assignment of the odd and even markers
|
v.val_odd := r.switch; -- Assignment of the odd and even markers
|
v.val_even := not(r.switch);
|
v.val_even := not(r.switch);
|
|
|
when others =>
|
when others =>
|
v.state := s_idle;
|
v.state := s_idle;
|
|
|
end case;
|
end case;
|
|
|
if(rst = '1') then
|
if(rst = '1') then
|
v.switch := '0';
|
v.switch := '0';
|
v.count_up := 0;
|
v.count_up := 0;
|
v.count_down := 0;
|
v.count_down := 0;
|
v.val_odd := '0';
|
v.val_odd := '0';
|
v.val_even := '0';
|
v.val_even := '0';
|
v.state := s_idle;
|
v.state := s_idle;
|
end if;
|
end if;
|
|
|
rin <= v;
|
rin <= v;
|
|
|
end process comb;
|
end process comb;
|
|
|
regs : process(clk)
|
regs : process(clk)
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
r <= rin;
|
r <= rin;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
-- OUTPUT STAGE: ALIGNMENT AND PIPELINE STAGES
|
-- OUTPUT STAGE: ALIGNMENT AND PIPELINE STAGES
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
gen_align_and_pipeline_stages : for I in g_fft.wb_factor/2 - 1 downto 0 generate
|
gen_align_and_pipeline_stages : for I in g_fft.wb_factor/2 - 1 downto 0 generate
|
u_output_pipeline_align : entity common_components_lib.common_pipeline
|
u_output_pipeline_align : entity common_components_lib.common_pipeline
|
generic map (
|
generic map (
|
g_pipeline => c_pipeline_output + 1, -- Pipeline + one stage for allignment
|
g_pipeline => c_pipeline_output + 1, -- Pipeline + one stage for allignment
|
g_in_dat_w => c_dat_w,
|
g_in_dat_w => c_dat_w,
|
g_out_dat_w => c_dat_w
|
g_out_dat_w => c_dat_w
|
)
|
)
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
in_dat => sep_out_dat_arr(2*I),
|
in_dat => sep_out_dat_arr(2*I),
|
out_dat => out_dat_arr(2*I)
|
out_dat => out_dat_arr(2*I)
|
);
|
);
|
|
|
u_output_pipeline : entity common_components_lib.common_pipeline
|
u_output_pipeline : entity common_components_lib.common_pipeline
|
generic map (
|
generic map (
|
g_pipeline => c_pipeline_output, -- Only pipeline stage
|
g_pipeline => c_pipeline_output, -- Only pipeline stage
|
g_in_dat_w => c_dat_w,
|
g_in_dat_w => c_dat_w,
|
g_out_dat_w => c_dat_w
|
g_out_dat_w => c_dat_w
|
)
|
)
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
in_dat => sep_out_dat_arr(2*I+1),
|
in_dat => sep_out_dat_arr(2*I+1),
|
out_dat => out_dat_arr(2*I+1)
|
out_dat => out_dat_arr(2*I+1)
|
);
|
);
|
end generate;
|
end generate;
|
|
|
u_out_val_pipeline : entity common_components_lib.common_pipeline_sl
|
u_out_val_pipeline : entity common_components_lib.common_pipeline_sl
|
generic map (
|
generic map (
|
g_pipeline => c_pipeline_output
|
g_pipeline => c_pipeline_output
|
)
|
)
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
in_dat => sep_out_val_vec(1),
|
in_dat => sep_out_val_vec(1),
|
out_dat => out_val
|
out_dat => out_val
|
);
|
);
|
|
|
-- Split the concatenated array into a real and imaginary array for the output
|
-- Split the concatenated array into a real and imaginary array for the output
|
gen_output_arrays : for I in g_fft.wb_factor-1 downto 0 generate
|
gen_output_arrays : for I in g_fft.wb_factor-1 downto 0 generate
|
out_re_arr(I) <= resize_fft_svec(out_dat_arr(I)( g_fft.stage_dat_w-1 downto 0));
|
out_re_arr(I) <= resize_fft_svec(out_dat_arr(I)( g_fft.stage_dat_w-1 downto 0));
|
out_im_arr(I) <= resize_fft_svec(out_dat_arr(I)(c_nof_complex*g_fft.stage_dat_w-1 downto g_fft.stage_dat_w));
|
out_im_arr(I) <= resize_fft_svec(out_dat_arr(I)(c_nof_complex*g_fft.stage_dat_w-1 downto g_fft.stage_dat_w));
|
end generate;
|
end generate;
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|
|
|
