/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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Buffered Clos switch for SDM-Clos routers
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Buffered Clos switch for SDM-Clos routers
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*** SystemVerilog is used ***
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*** SystemVerilog is used ***
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History:
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History:
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09/07/2011 Initial version. <wsong83@gmail.com>
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09/07/2011 Initial version. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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module clos (/*AUTOARG*/
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module clos (/*AUTOARG*/
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// Outputs
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// Outputs
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so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
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so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
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eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
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eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
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wia, nia, eia, lia,
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wia, nia, eia, lia,
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// Inputs
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// Inputs
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si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
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si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
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ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
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ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
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woa, noa, eoa, loa, soa4, woa4, noa4, eoa4, loa4, sdec, ndec, ldec,
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woa, noa, eoa, loa, soa4, woa4, noa4, eoa4, loa4, sdec, ndec, ldec,
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wdec, edec
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wdec, edec, rst_n
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);
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);
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parameter MN = 2; // number of CMs
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parameter MN = 2; // number of CMs
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parameter NN = 2; // number of ports in an IM or OM, equ. to number of virtual circuits
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parameter NN = 2; // number of ports in an IM or OM, equ. to number of virtual circuits
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parameter DW = 8; // datawidth of a single virtual circuit/port
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parameter DW = 8; // datawidth of a single virtual circuit/port
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parameter SCN = DW/2; // number of 1-of-4 sub-channels in one port
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parameter SCN = DW/2; // number of 1-of-4 sub-channels in one port
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input [NN-1:0][SCN-1:0] si0, si1, si2, si3; // south input [0], X+1
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input [NN-1:0][SCN-1:0] si0, si1, si2, si3; // south input [0], X+1
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input [NN-1:0][SCN-1:0] wi0, wi1, wi2, wi3; // west input [1], Y-1
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input [NN-1:0][SCN-1:0] wi0, wi1, wi2, wi3; // west input [1], Y-1
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input [NN-1:0][SCN-1:0] ni0, ni1, ni2, ni3; // north input [2], X-1
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input [NN-1:0][SCN-1:0] ni0, ni1, ni2, ni3; // north input [2], X-1
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input [NN-1:0][SCN-1:0] ei0, ei1, ei2, ei3; // east input [3], Y+1
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input [NN-1:0][SCN-1:0] ei0, ei1, ei2, ei3; // east input [3], Y+1
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input [NN-1:0][SCN-1:0] li0, li1, li2, li3; // local input
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input [NN-1:0][SCN-1:0] li0, li1, li2, li3; // local input
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output [NN-1:0][SCN-1:0] so0, so1, so2, so3; // south output
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output [NN-1:0][SCN-1:0] so0, so1, so2, so3; // south output
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output [NN-1:0][SCN-1:0] wo0, wo1, wo2, wo3; // west output
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output [NN-1:0][SCN-1:0] wo0, wo1, wo2, wo3; // west output
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output [NN-1:0][SCN-1:0] no0, no1, no2, no3; // north output
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output [NN-1:0][SCN-1:0] no0, no1, no2, no3; // north output
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output [NN-1:0][SCN-1:0] eo0, eo1, eo2, eo3; // east output
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output [NN-1:0][SCN-1:0] eo0, eo1, eo2, eo3; // east output
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output [NN-1:0][SCN-1:0] lo0, lo1, lo2, lo3; // local output
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output [NN-1:0][SCN-1:0] lo0, lo1, lo2, lo3; // local output
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// eof bits and ack lines
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// eof bits and ack lines
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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input [NN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4;
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input [NN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4;
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output [NN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;
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output [NN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;
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output [NN-1:0][SCN-1:0] sia, wia, nia, eia, lia;
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output [NN-1:0][SCN-1:0] sia, wia, nia, eia, lia;
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input [NN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;
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input [NN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;
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// `ifdef ENABLE_BUFFERED_CLOS
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// `ifdef ENABLE_BUFFERED_CLOS
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input [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
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input [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
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// `endif
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// `endif
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`else
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`else
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input [NN-1:0] si4, wi4, ni4, ei4, li4;
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input [NN-1:0] si4, wi4, ni4, ei4, li4;
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output [NN-1:0] so4, wo4, no4, eo4, lo4;
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output [NN-1:0] so4, wo4, no4, eo4, lo4;
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output [NN-1:0] sia, wia, nia, eia, lia;
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output [NN-1:0] sia, wia, nia, eia, lia;
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input [NN-1:0] soa, woa, noa, eoa, loa;
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input [NN-1:0] soa, woa, noa, eoa, loa;
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// `ifdef ENABLE_BUFFERED_CLOS
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// `ifdef ENABLE_BUFFERED_CLOS
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input [NN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
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input [NN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
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// `endif
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// `endif
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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input [NN-1:0][3:0] sdec, ndec, ldec; // the routing requests
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input [NN-1:0][3:0] sdec, ndec, ldec; // the routing requests
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input [NN-1:0][1:0] wdec, edec; // the routing requests
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input [NN-1:0][1:0] wdec, edec; // the routing requests
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input rst_n; // global active low reset
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genvar i,j;
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genvar i,j;
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// the IMs
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// the IMs
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im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))
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im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))
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SIM (
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SIM (
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.do0 ( sim0 ),
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.do0 ( sim0 ),
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.do1 ( sim1 ),
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.do1 ( sim1 ),
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.do2 ( sim2 ),
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.do2 ( sim2 ),
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.do3 ( sim3 ),
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.do3 ( sim3 ),
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.deco ( simdec ),
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.deco ( simdec ),
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.dia ( sia ),
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.dia ( sia ),
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.do4 ( sim4 ),
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.do4 ( sim4 ),
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.di0 ( si0 ),
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.di0 ( si0 ),
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.di1 ( si1 ),
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.di1 ( si1 ),
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.di2 ( si2 ),
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.di2 ( si2 ),
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.di3 ( si3 ),
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.di3 ( si3 ),
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.deci ( sdec ),
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.deci ( sdec ),
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.di4 ( si4 ),
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.di4 ( si4 ),
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.doa ( sima ),
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.doa ( sima ),
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`ifndef ENABLE_CRRD
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`ifndef ENABLE_CRRD
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.cms ( sims ),
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.cms ( sims ),
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`endif
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`endif
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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im #(.MN(MN), .NN(NN), .DW(DW), .SN(2))
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im #(.MN(MN), .NN(NN), .DW(DW), .SN(2))
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WIM (
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WIM (
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.do0 ( wim0 ),
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.do0 ( wim0 ),
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.do1 ( wim1 ),
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.do1 ( wim1 ),
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.do2 ( wim2 ),
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.do2 ( wim2 ),
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.do3 ( wim3 ),
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.do3 ( wim3 ),
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.deco ( wimdec ),
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.deco ( wimdec ),
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.dia ( wia ),
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.dia ( wia ),
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.do4 ( wim4 ),
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.do4 ( wim4 ),
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.di0 ( wi0 ),
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.di0 ( wi0 ),
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.di1 ( wi1 ),
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.di1 ( wi1 ),
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.di2 ( wi2 ),
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.di2 ( wi2 ),
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.di3 ( wi3 ),
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.di3 ( wi3 ),
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.deci ( wdec ),
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.deci ( wdec ),
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.di4 ( wi4 ),
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.di4 ( wi4 ),
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.doa ( wima ),
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.doa ( wima ),
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`ifndef ENABLE_CRRD
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`ifndef ENABLE_CRRD
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.cms ( wims ),
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.cms ( wims ),
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`endif
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`endif
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))
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im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))
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NIM (
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NIM (
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.do0 ( nim0 ),
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.do0 ( nim0 ),
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.do1 ( nim1 ),
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.do1 ( nim1 ),
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.do2 ( nim2 ),
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.do2 ( nim2 ),
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.do3 ( nim3 ),
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.do3 ( nim3 ),
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.deco ( nimdec ),
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.deco ( nimdec ),
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.dia ( nia ),
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.dia ( nia ),
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.do4 ( nim4 ),
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.do4 ( nim4 ),
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.di0 ( ni0 ),
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.di0 ( ni0 ),
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.di1 ( ni1 ),
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.di1 ( ni1 ),
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.di2 ( ni2 ),
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.di2 ( ni2 ),
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.di3 ( ni3 ),
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.di3 ( ni3 ),
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.deci ( ndec ),
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.deci ( ndec ),
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.di4 ( ni4 ),
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.di4 ( ni4 ),
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.doa ( nima ),
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.doa ( nima ),
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`ifndef ENABLE_CRRD
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`ifndef ENABLE_CRRD
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.cms ( nims ),
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.cms ( nims ),
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`endif
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`endif
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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im #(.MN(MN), .NN(NN), .DW(DW), .SN(2))
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im #(.MN(MN), .NN(NN), .DW(DW), .SN(2))
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EIM (
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EIM (
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.do0 ( eim0 ),
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.do0 ( eim0 ),
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.do1 ( eim1 ),
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.do1 ( eim1 ),
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.do2 ( eim2 ),
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.do2 ( eim2 ),
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.do3 ( eim3 ),
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.do3 ( eim3 ),
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.deco ( eimdec ),
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.deco ( eimdec ),
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.dia ( eia ),
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.dia ( eia ),
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.do4 ( eim4 ),
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.do4 ( eim4 ),
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.di0 ( ei0 ),
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.di0 ( ei0 ),
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.di1 ( ei1 ),
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.di1 ( ei1 ),
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.di2 ( ei2 ),
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.di2 ( ei2 ),
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.di3 ( ei3 ),
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.di3 ( ei3 ),
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.deci ( edec ),
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.deci ( edec ),
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.di4 ( ei4 ),
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.di4 ( ei4 ),
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.doa ( eima ),
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.doa ( eima ),
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`ifndef ENABLE_CRRD
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`ifndef ENABLE_CRRD
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.cms ( eims ),
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.cms ( eims ),
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`endif
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`endif
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))
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im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))
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LIM (
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LIM (
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.do0 ( lim0 ),
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.do0 ( lim0 ),
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.do1 ( lim1 ),
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.do1 ( lim1 ),
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.do2 ( lim2 ),
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.do2 ( lim2 ),
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.do3 ( lim3 ),
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.do3 ( lim3 ),
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.deco ( limdec ),
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.deco ( limdec ),
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.dia ( lia ),
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.dia ( lia ),
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.do4 ( lim4 ),
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.do4 ( lim4 ),
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.di0 ( li0 ),
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.di0 ( li0 ),
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.di1 ( li1 ),
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.di1 ( li1 ),
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.di2 ( li2 ),
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.di2 ( li2 ),
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.di3 ( li3 ),
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.di3 ( li3 ),
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.deci ( ldec ),
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.deci ( ldec ),
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.di4 ( li4 ),
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.di4 ( li4 ),
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.doa ( lima ),
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.doa ( lima ),
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`ifndef ENABLE_CRRD
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`ifndef ENABLE_CRRD
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.cms ( lims ),
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.cms ( lims ),
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`endif
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`endif
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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// data wire shuffle
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// data wire shuffle
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// the CMs
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// the CMs
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generate
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generate
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for(i=0; i<MN; i++) begin:CMSH
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for(i=0; i<MN; i++) begin:CMSH
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assign cmi0[i][0] = sim0[i];
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assign cmi0[i][0] = sim0[i];
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assign cmi1[i][0] = sim1[i];
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assign cmi1[i][0] = sim1[i];
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assign cmi2[i][0] = sim2[i];
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assign cmi2[i][0] = sim2[i];
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assign cmi3[i][0] = sim3[i];
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assign cmi3[i][0] = sim3[i];
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assign sima[i] = cmia[i][0];
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assign sima[i] = cmia[i][0];
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assign sima4[i] = cmia[i][0];
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assign sima4[i] = cmia[i][0];
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assign cmi0[i][1] = wim0[i];
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assign cmi0[i][1] = wim0[i];
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assign cmi1[i][1] = wim1[i];
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assign cmi1[i][1] = wim1[i];
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assign cmi2[i][1] = wim2[i];
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assign cmi2[i][1] = wim2[i];
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assign cmi3[i][1] = wim3[i];
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assign cmi3[i][1] = wim3[i];
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assign wima[i] = cmia[i][1];
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assign wima[i] = cmia[i][1];
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assign wima4[i] = cmia[i][1];
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assign wima4[i] = cmia[i][1];
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assign cmi0[i][2] = nim0[i];
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assign cmi0[i][2] = nim0[i];
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assign cmi1[i][2] = nim1[i];
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assign cmi1[i][2] = nim1[i];
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assign cmi2[i][2] = nim2[i];
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assign cmi2[i][2] = nim2[i];
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assign cmi3[i][2] = nim3[i];
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assign cmi3[i][2] = nim3[i];
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assign nima[i] = cmia[i][2];
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assign nima[i] = cmia[i][2];
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assign nima4[i] = cmia[i][2];
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assign nima4[i] = cmia[i][2];
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assign cmi0[i][3] = eim0[i];
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assign cmi0[i][3] = eim0[i];
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assign cmi1[i][3] = eim1[i];
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assign cmi1[i][3] = eim1[i];
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assign cmi2[i][3] = eim2[i];
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assign cmi2[i][3] = eim2[i];
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assign cmi3[i][3] = eim3[i];
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assign cmi3[i][3] = eim3[i];
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assign eima[i] = cmia[i][3];
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assign eima[i] = cmia[i][3];
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assign eima4[i] = cmia[i][3];
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assign eima4[i] = cmia[i][3];
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assign cmi0[i][4] = lim0[i];
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assign cmi0[i][4] = lim0[i];
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assign cmi1[i][4] = lim1[i];
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assign cmi1[i][4] = lim1[i];
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assign cmi2[i][4] = lim2[i];
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assign cmi2[i][4] = lim2[i];
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assign cmi3[i][4] = lim3[i];
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assign cmi3[i][4] = lim3[i];
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assign lima[i] = cmia[i][4];
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assign lima[i] = cmia[i][4];
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assign lima4[i] = cmia[i][4];
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assign lima4[i] = cmia[i][4];
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cm #(.KN(5), .DW(DW))
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cm #(.KN(5), .DW(DW))
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CMSW (
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CMSW (
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.do0 ( cmo0[i] ),
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.do0 ( cmo0[i] ),
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.do1 ( cmo1[i] ),
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.do1 ( cmo1[i] ),
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.do2 ( cmo2[i] ),
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.do2 ( cmo2[i] ),
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.do3 ( cmo3[i] ),
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.do3 ( cmo3[i] ),
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.dia ( cmia[i] ),
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.dia ( cmia[i] ),
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.do4 ( cmo4[i] ),
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.do4 ( cmo4[i] ),
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.di0 ( cmi0[i] ),
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.di0 ( cmi0[i] ),
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.di1 ( cmi1[i] ),
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.di1 ( cmi1[i] ),
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.di2 ( cmi2[i] ),
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.di2 ( cmi2[i] ),
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.di3 ( cmi3[i] ),
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.di3 ( cmi3[i] ),
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.sdec ( sdec[i] ),
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.sdec ( sdec[i] ),
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.ndec ( ndec[i] ),
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.ndec ( ndec[i] ),
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.ldec ( ldec[i] ),
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.ldec ( ldec[i] ),
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.wdec ( wdec[i] ),
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.wdec ( wdec[i] ),
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.edec ( edec[i] ),
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.edec ( edec[i] ),
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.di4 ( cmi4[i] ),
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.di4 ( cmi4[i] ),
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.doa ( cmoa[i] ),
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.doa ( cmoa[i] ),
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.doa4 ( cmoa4[i] ),
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.doa4 ( cmoa4[i] ),
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`ifndef ENABLE_CRRD
|
`ifndef ENABLE_CRRD
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.cms ( cms[i] ),
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.cms ( cms[i] ),
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`endif
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`endif
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
|
|
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assign so0[i] = cmo0[i][0];
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assign so0[i] = cmo0[i][0];
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assign so1[i] = cmo1[i][0];
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assign so1[i] = cmo1[i][0];
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assign so2[i] = cmo2[i][0];
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assign so2[i] = cmo2[i][0];
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assign so3[i] = cmo3[i][0];
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assign so3[i] = cmo3[i][0];
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assign cmoa[i][0] = soa[i];
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assign cmoa[i][0] = soa[i];
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assign cmoa[i][0] = soa4[i];
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assign cmoa[i][0] = soa4[i];
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|
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assign wo0[i] = cmo0[i][1];
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assign wo0[i] = cmo0[i][1];
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assign wo1[i] = cmo1[i][1];
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assign wo1[i] = cmo1[i][1];
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assign wo2[i] = cmo2[i][1];
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assign wo2[i] = cmo2[i][1];
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assign wo3[i] = cmo3[i][1];
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assign wo3[i] = cmo3[i][1];
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assign cmoa[i][1] = woa[i];
|
assign cmoa[i][1] = woa[i];
|
assign cmoa[i][1] = woa4[i];
|
assign cmoa[i][1] = woa4[i];
|
|
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assign no0[i] = cmo0[i][2];
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assign no0[i] = cmo0[i][2];
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assign no1[i] = cmo1[i][2];
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assign no1[i] = cmo1[i][2];
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assign no2[i] = cmo2[i][2];
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assign no2[i] = cmo2[i][2];
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assign no3[i] = cmo3[i][2];
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assign no3[i] = cmo3[i][2];
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assign cmoa[i][2] = noa[i];
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assign cmoa[i][2] = noa[i];
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assign cmoa[i][2] = noa4[i];
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assign cmoa[i][2] = noa4[i];
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assign eo0[i] = cmo0[i][3];
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assign eo0[i] = cmo0[i][3];
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assign eo1[i] = cmo1[i][3];
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assign eo1[i] = cmo1[i][3];
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assign eo2[i] = cmo2[i][3];
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assign eo2[i] = cmo2[i][3];
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assign eo3[i] = cmo3[i][3];
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assign eo3[i] = cmo3[i][3];
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assign cmoa[i][3] = eoa[i];
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assign cmoa[i][3] = eoa[i];
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assign cmoa[i][3] = eoa4[i];
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assign cmoa[i][3] = eoa4[i];
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assign lo0[i] = cmo0[i][4];
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assign lo0[i] = cmo0[i][4];
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assign lo1[i] = cmo1[i][4];
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assign lo1[i] = cmo1[i][4];
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assign lo2[i] = cmo2[i][4];
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assign lo2[i] = cmo2[i][4];
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assign lo3[i] = cmo3[i][4];
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assign lo3[i] = cmo3[i][4];
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assign cmoa[i][4] = loa[i];
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assign cmoa[i][4] = loa[i];
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assign cmoa[i][4] = loa4[i];
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assign cmoa[i][4] = loa4[i];
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end
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end
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endgenerate
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endgenerate
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endmodule // clos
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endmodule // clos
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