/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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Input buffer for Wormhole/SDM routers.
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Input buffer for Wormhole/SDM routers.
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*** SystemVerilog is used ***
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*** SystemVerilog is used ***
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References
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References
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* Lookahead pipelines
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* Lookahead pipelines
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Montek Singh and Steven M. Nowick, The design of high-performance dynamic asynchronous pipelines: lookahead style, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007(15), 1256-1269. doi:10.1109/TVLSI.2007.902205
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Montek Singh and Steven M. Nowick, The design of high-performance dynamic asynchronous pipelines: lookahead style, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007(15), 1256-1269. doi:10.1109/TVLSI.2007.902205
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* Channel slicing
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* Channel slicing
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Wei Song and Doug Edwards, A low latency wormhole router for asynchronous on-chip networks, Asia and South Pacific Design Automation Conference, 2010, 437-443.
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Wei Song and Doug Edwards, A low latency wormhole router for asynchronous on-chip networks, Asia and South Pacific Design Automation Conference, 2010, 437-443.
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* SDM
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* SDM
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Wei Song and Doug Edwards, Asynchronous spatial division multiplexing router, Microprocessors and Microsystems, 2011(35), 85-97.
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Wei Song and Doug Edwards, Asynchronous spatial division multiplexing router, Microprocessors and Microsystems, 2011(35), 85-97.
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History:
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History:
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05/05/2009 Initial version. <wsong83@gmail.com>
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05/05/2009 Initial version. <wsong83@gmail.com>
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20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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24/05/2011 Clean up for opensource. <wsong83@gmail.com>
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24/05/2011 Clean up for opensource. <wsong83@gmail.com>
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01/06/2011 Use the comp4 common comparator rather than the chain_comparator defined in this module. <wsong83@gmail.com>
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01/06/2011 Use the comp4 common comparator rather than the chain_comparator defined in this module. <wsong83@gmail.com>
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21/06/2011 Move the eof logic in every pipeline stage outside the pipe4 module. <wsong83@gmail.com>
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21/06/2011 Move the eof logic in every pipeline stage outside the pipe4 module. <wsong83@gmail.com>
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12/07/2011 Preparation for the buffered Clos switch. <wsong83@gmail.com>
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12/07/2011 Preparation for the buffered Clos switch. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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module inp_buf (/*AUTOARG*/
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module inp_buf (/*AUTOARG*/
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// Outputs
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// Outputs
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o0, o1, o2, o3, o4, ia, deco,
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o0, o1, o2, o3, o4, ia, deco,
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// Inputs
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// Inputs
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rst_n, i0, i1, i2, i3, i4, oa, addrx, addry
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rst_n, i0, i1, i2, i3, i4, oa, addrx, addry
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);
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);
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//-------------------------- parameters ---------------------------------------//
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//-------------------------- parameters ---------------------------------------//
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parameter DIR = 0; // the port direction: south, west, north, east, and local
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parameter DIR = 0; // the port direction: south, west, north, east, and local
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parameter RN = 4; // the number of request outputs, must match the direction
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parameter RN = 4; // the number of request outputs, must match the direction
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parameter DW = 16; // the data-width of the data-path
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parameter DW = 16; // the data-width of the data-path
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parameter PD = 2; // the depth of the input buffer
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parameter PD = 2; // the depth of the input buffer
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parameter SCN = DW/2;
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parameter SCN = DW/2;
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//-------------------------- I/O ports ---------------------------------------//
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//-------------------------- I/O ports ---------------------------------------//
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input rst_n; // global reset, active low
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input rst_n; // global reset, active low
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input [SCN-1:0] i0, i1, i2, i3; // data input
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input [SCN-1:0] i0, i1, i2, i3; // data input
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output [SCN-1:0] o0, o1, o2, o3; // data output
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output [SCN-1:0] o0, o1, o2, o3; // data output
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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input [SCN-1:0] i4, oa;
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input [SCN-1:0] i4, oa;
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output [SCN-1:0] o4, ia;
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output [SCN-1:0] o4, ia;
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`else
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`else
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input i4, oa;
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input i4, oa;
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output o4, ia;
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output o4, ia;
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`endif
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`endif
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input [7:0] addrx, addry; // local addresses in 1-of-4 encoding
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input [7:0] addrx, addry; // local addresses in 1-of-4 encoding
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output [RN-1:0] deco; // the decoded routing requests
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output [RN-1:0] deco; // the decoded routing requests
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//-------------------------- control signals ---------------------------------------//
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//-------------------------- control signals ---------------------------------------//
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wire rta; // the ack of the dec reg pipeline stage
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wire rta; // the ack of the dec reg pipeline stage
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wire frame_end; // identify the end of a frame
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wire frame_end; // identify the end of a frame
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wire [7:0] pipe_xd, pipe_yd; // the target address from the incoming frame
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wire [7:0] pipe_xd, pipe_yd; // the target address from the incoming frame
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wire [PD:0][SCN-1:0] pd0, pd1, pd2, pd3; // data wires for the internal pipeline satges
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wire [PD:0][SCN-1:0] pd0, pd1, pd2, pd3; // data wires for the internal pipeline satges
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wire [5:0] raw_dec; // the routing decision from the comparator
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wire [5:0] raw_dec; // the routing decision from the comparator
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wire [5:0] xy_dec; // the routing decision of the XY routing algorithm
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wire [4:0] xy_dec; // the routing decision of the XY routing algorithm
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wire [4:0] dec_reg; // the routing decision kept by C-gates
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wire [4:0] dec_reg; // the routing decision kept by C-gates
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wire x_equal; // addr x = target x
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wire x_equal; // addr x = target x
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wire rt_err; // route decoder error
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wire rt_err; // route decoder error
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [SCN-1:0] deca; // the ack for routing requests
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wire [SCN-1:0] deca; // the ack for routing requests
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wire [SCN-1:0] pda1; // the ack for the 1st pipeline stage
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wire [SCN-1:0] pda1; // the ack for the 1st pipeline stage
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wire [SCN-1:0] acko; // the ack from CB
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wire [SCN-1:0] acko; // the ack from CB
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wire [PD:0][SCN-1:0] pd4, pda, pdan, pd4an; // data wires for the internal pipeline stages
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wire [PD:0][SCN-1:0] pd4, pda, pdan, pd4an; // data wires for the internal pipeline stages
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`else
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`else
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wire deca; // the ack for routing requests
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wire deca; // the ack for routing requests
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wire pda1; // the ack for the 1st pipeline stage
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wire pda1; // the ack for the 1st pipeline stage
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wire acko; // the ack from CB
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wire acko; // the ack from CB
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wire [PD:0] pd4, pda, pdan, pd4an; // data wires for the internal pipeline satges
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wire [PD:0] pd4, pda, pdan, pda4n; // data wires for the internal pipeline satges
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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wire decan;
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wire decan;
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genvar i, j;
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genvar i, j;
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//------------------------- pipelines ------------------------------------- //
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//------------------------- pipelines ------------------------------------- //
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generate for(i=0; i<PD; i++) begin: DP
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generate for(i=0; i<PD; i++) begin: DP
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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for(j=0; j<SCN; j++) begin: SC
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for(j=0; j<SCN; j++) begin: SC
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pipe4 #(.DW(2))
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pipe4 #(.DW(2))
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P (
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P (
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.o0 ( pd0[i][j] ),
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.o0 ( pd0[i][j] ),
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.o1 ( pd1[i][j] ),
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.o1 ( pd1[i][j] ),
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.o2 ( pd2[i][j] ),
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.o2 ( pd2[i][j] ),
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.o3 ( pd3[i][j] ),
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.o3 ( pd3[i][j] ),
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.ia ( pda[i+1][j] ),
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.ia ( pda[i+1][j] ),
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.i0 ( pd0[i+1][j] ),
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.i0 ( pd0[i+1][j] ),
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.i1 ( pd1[i+1][j] ),
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.i1 ( pd1[i+1][j] ),
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.i2 ( pd2[i+1][j] ),
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.i2 ( pd2[i+1][j] ),
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.i3 ( pd3[i+1][j] ),
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.i3 ( pd3[i+1][j] ),
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.oa ( pdan[i][j] )
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.oa ( pdan[i][j] )
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);
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);
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pipen #(.DW(1))
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pipen #(.DW(1))
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PEoF (
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PEoF (
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.d_in_a ( ),
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.d_in_a ( ),
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.d_out ( pd4[i][j] ),
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.d_out ( pd4[i][j] ),
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.d_in ( pd4[i+1][j] ),
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.d_in ( pd4[i+1][j] ),
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.d_out_a ( pd4an[i][j] )
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.d_out_a ( pda4n[i][j] )
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);
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);
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end // block: SC
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end // block: SC
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`else // !`ifdef ENABLE_CHANNEL_SLICING
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`else // !`ifdef ENABLE_CHANNEL_SLICING
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pipe4 #(.DW(DW))
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pipe4 #(.DW(DW))
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P (
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P (
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.o0 ( pd0[i] ),
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.o0 ( pd0[i] ),
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.o1 ( pd1[i] ),
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.o1 ( pd1[i] ),
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.o2 ( pd2[i] ),
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.o2 ( pd2[i] ),
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.o3 ( pd3[i] ),
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.o3 ( pd3[i] ),
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.ia ( pda[i+1] ),
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.ia ( pda[i+1] ),
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.i0 ( pd0[i+1] ),
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.i0 ( pd0[i+1] ),
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.i1 ( pd1[i+1] ),
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.i1 ( pd1[i+1] ),
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.i2 ( pd2[i+1] ),
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.i2 ( pd2[i+1] ),
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.i3 ( pd3[i+1] ),
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.i3 ( pd3[i+1] ),
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.oa ( pdan[i] )
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.oa ( pdan[i] )
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);
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);
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pipen #(.DW(1))
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pipen #(.DW(1))
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PEoF (
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PEoF (
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.d_in_a ( ),
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.d_in_a ( ),
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.d_out ( pd4[i] ),
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.d_out ( pd4[i] ),
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.d_in ( pd4[i+1] ),
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.d_in ( pd4[i+1] ),
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.d_out_a ( pd4an[i] )
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.d_out_a ( pda4n[i] )
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);
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);
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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end // block: DP
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end // block: DP
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endgenerate
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endgenerate
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generate
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generate
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for(i=2; i<PD; i++) begin: DPA
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for(i=2; i<PD; i++) begin: DPA
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assign pdan[i] = rst_n ? ~(pda[i]|pd4[i-1]) : 0;
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assign pdan[i] = rst_n ? ~(pda[i]|pd4[i-1]) : 0;
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assign pd4an[i] = pdan[i];
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assign pda4n[i] = pdan[i];
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end
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end
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// in case only one pipeline stage is configured
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// in case only one pipeline stage is configured
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if(PD>1)
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if(PD>1)
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assign ia = pda[PD]|pd4[PD-1];
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assign ia = pda[PD]|pd4[PD-1];
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else
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else
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assign ia = pda1;
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assign ia = pda1;
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endgenerate
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endgenerate
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//assign ia = pda[PD]|pd4[PD-1];
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//assign ia = pda[PD]|pd4[PD-1];
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assign pd0[PD] = i0;
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assign pd0[PD] = i0;
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assign pd1[PD] = i1;
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assign pd1[PD] = i1;
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assign pd2[PD] = i2;
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assign pd2[PD] = i2;
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assign pd3[PD] = i3;
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assign pd3[PD] = i3;
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assign pd4[PD] = i4;
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assign pd4[PD] = i4;
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assign o0 = pd0[0];
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assign o0 = pd0[0];
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assign o1 = pd1[0];
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assign o1 = pd1[0];
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assign o2 = pd2[0];
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assign o2 = pd2[0];
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assign o3 = pd3[0];
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assign o3 = pd3[0];
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assign o4 = pd4[0];
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assign o4 = pd4[0];
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//---------------------------- route decoder related -------------------------- //
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//---------------------------- route decoder related -------------------------- //
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// fetch the x and y target
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// fetch the x and y target
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and Px_0 (pipe_xd[0], ~rta, pd0[1][0]);
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and Px_0 (pipe_xd[0], ~rta, pd0[1][0]);
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and Px_1 (pipe_xd[1], ~rta, pd1[1][0]);
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and Px_1 (pipe_xd[1], ~rta, pd1[1][0]);
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and Px_2 (pipe_xd[2], ~rta, pd2[1][0]);
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and Px_2 (pipe_xd[2], ~rta, pd2[1][0]);
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and Px_3 (pipe_xd[3], ~rta, pd3[1][0]);
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and Px_3 (pipe_xd[3], ~rta, pd3[1][0]);
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and Px_4 (pipe_xd[4], ~rta, pd0[1][1]);
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and Px_4 (pipe_xd[4], ~rta, pd0[1][1]);
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and Px_5 (pipe_xd[5], ~rta, pd1[1][1]);
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and Px_5 (pipe_xd[5], ~rta, pd1[1][1]);
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and Px_6 (pipe_xd[6], ~rta, pd2[1][1]);
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and Px_6 (pipe_xd[6], ~rta, pd2[1][1]);
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and Px_7 (pipe_xd[7], ~rta, pd3[1][1]);
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and Px_7 (pipe_xd[7], ~rta, pd3[1][1]);
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and Py_0 (pipe_yd[0], ~rta, pd0[1][2]);
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and Py_0 (pipe_yd[0], ~rta, pd0[1][2]);
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and Py_1 (pipe_yd[1], ~rta, pd1[1][2]);
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and Py_1 (pipe_yd[1], ~rta, pd1[1][2]);
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and Py_2 (pipe_yd[2], ~rta, pd2[1][2]);
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and Py_2 (pipe_yd[2], ~rta, pd2[1][2]);
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and Py_3 (pipe_yd[3], ~rta, pd3[1][2]);
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and Py_3 (pipe_yd[3], ~rta, pd3[1][2]);
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and Py_4 (pipe_yd[4], ~rta, pd0[1][3]);
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and Py_4 (pipe_yd[4], ~rta, pd0[1][3]);
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and Py_5 (pipe_yd[5], ~rta, pd1[1][3]);
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and Py_5 (pipe_yd[5], ~rta, pd1[1][3]);
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and Py_6 (pipe_yd[6], ~rta, pd2[1][3]);
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and Py_6 (pipe_yd[6], ~rta, pd2[1][3]);
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and Py_7 (pipe_yd[7], ~rta, pd3[1][3]);
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and Py_7 (pipe_yd[7], ~rta, pd3[1][3]);
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routing_decision // the comparator
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routing_decision // the comparator
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RTD(
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RTD(
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.addrx ( addrx ),
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.addrx ( addrx ),
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.addry ( addry ),
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.addry ( addry ),
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.pipe_xd ( pipe_xd ),
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.pipe_xd ( pipe_xd ),
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.pipe_yd ( pipe_yd ),
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.pipe_yd ( pipe_yd ),
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.decision ( raw_dec )
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.decision ( raw_dec )
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);
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);
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// translate it into the XY dec; not QDI here as the circuit can be slow
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// translate it into the XY dec; not QDI here as the circuit can be slow
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assign xy_dec[1:0] = raw_dec[1:0];
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assign xy_dec[1:0] = raw_dec[1:0];
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assign xy_dec[4:2] = raw_dec[2] ? raw_dec[5:3] : 0;
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assign xy_dec[4:2] = raw_dec[2] ? raw_dec[5:3] : 0;
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// the decoded routing requests
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// the decoded routing requests
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pipen #(.DW(RN))
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pipen #(.DW(5))
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PDEC (
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PDEC (
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.d_in_a ( rta ),
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.d_in_a ( rta ),
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.d_out ( dec_reg ),
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.d_out ( dec_reg ),
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.d_in ( xy_dec ),
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.d_in ( xy_dec ),
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.d_out_a ( decan )
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.d_out_a ( decan )
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);
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);
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assign decan = ~(&deca);
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assign decan = ~(&deca);
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// generate the arbiter request signals
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// generate the arbiter request signals
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assign deco =
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assign deco =
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DIR == 0 ? {dec_reg[4],dec_reg[2],dec_reg[1],dec_reg[3]} : // south port
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DIR == 0 ? {dec_reg[4],dec_reg[2],dec_reg[1],dec_reg[3]} : // south port
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DIR == 1 ? {dec_reg[4],dec_reg[2]} : // west port
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DIR == 1 ? {dec_reg[4],dec_reg[2]} : // west port
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DIR == 2 ? {dec_reg[4],dec_reg[2],dec_reg[3],dec_reg[0]} : // north port
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DIR == 2 ? {dec_reg[4],dec_reg[2],dec_reg[3],dec_reg[0]} : // north port
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DIR == 3 ? {dec_reg[4],dec_reg[3]} : // east port
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DIR == 3 ? {dec_reg[4],dec_reg[3]} : // east port
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{dec_reg[2],dec_reg[1],dec_reg[3],dec_reg[0]} ; // local port
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{dec_reg[2],dec_reg[1],dec_reg[3],dec_reg[0]} ; // local port
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assign rt_err =
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assign rt_err =
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DIR == 0 ? |{dec_reg[0]} : // south port
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DIR == 0 ? |{dec_reg[0]} : // south port
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DIR == 1 ? |{dec_reg[0],dec_reg[1],dec_reg[3]} : // west port
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DIR == 1 ? |{dec_reg[0],dec_reg[1],dec_reg[3]} : // west port
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DIR == 2 ? |{dec_reg[1]} : // north port
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DIR == 2 ? |{dec_reg[1]} : // north port
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DIR == 3 ? |{dec_reg[0],dec_reg[1],dec_reg[2]} : // east port
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DIR == 3 ? |{dec_reg[0],dec_reg[1],dec_reg[2]} : // east port
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|{dec_reg[4]} ; // local port
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|{dec_reg[4]} ; // local port
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// ------------------------ pipeline control ------------------------------ //
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// ------------------------ pipeline control ------------------------------ //
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|
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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for(j=0; j<SCN; j++) begin: SC
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for(j=0; j<SCN; j++) begin: SC
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// the sub-channel controller
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// the sub-channel controller
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ppc SCH_C (
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ppc SCH_C (
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.deca ( deca[j] ),
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.deca ( deca[j] ),
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.dia ( pda1[j] ),
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.dia ( pda1[j] ),
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.eof ( pd4[0][j] ),
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.eof ( pd4[0][j] ),
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.doa ( acko[j]|(pda[0][j]&rt_err) ), // to handle faulty frames
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.doa ( acko[j]|(pda[0][j]&rt_err) ), // to handle faulty frames
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.dec ( rta )
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.dec ( rta )
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);
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);
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// the lookahead pipeline
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// the lookahead pipeline
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`ifdef ENABLE_LOOKAHEAD
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`ifdef ENABLE_LOOKAHEAD
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c2n CD (.q(acko[j]), .a(oa[j]), .b(pda[0][j])); // the C2N gate to avoid early withdrawal
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c2n CD (.q(acko[j]), .a(oa[j]), .b(pda[0][j])); // the C2N gate to avoid early withdrawal
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`else
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`else
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assign acko[j] = oa[j];
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assign acko[j] = oa[j];
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`endif
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`endif
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// the ack lines for the last two pipeline stages
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// the ack lines for the last two pipeline stages
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assign pdan[0][j] = (~oa[j])&rst_n;
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assign pdan[0][j] = (~oa[j])&rst_n;
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assign pda4n[0][j] = (~deca[j])&rst_n;
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assign pda4n[0][j] = (~deca[j])&rst_n;
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assign pdan[1][j] = (~pda1[j])&rst_n;
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assign pdan[1][j] = (~pda1[j])&rst_n;
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assign pda4n[1][j] = pdan[1][j];
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assign pda4n[1][j] = pdan[1][j];
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|
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end // block: SC
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end // block: SC
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`else // !`ifdef ENABLE_CHANNEL_SLICING
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`else // !`ifdef ENABLE_CHANNEL_SLICING
|
ppc SCH_C (
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ppc SCH_C (
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.deca ( deca ),
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.deca ( deca ),
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.dia ( pda1 ),
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.dia ( pda1 ),
|
.eof ( pd4[0] ),
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.eof ( pd4[0] ),
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.doa ( acko|(pda[0]&rt_err) ), // to handle faulty frames
|
.doa ( acko|(pda[0]&rt_err) ), // to handle faulty frames
|
.dec ( rta )
|
.dec ( rta )
|
);
|
);
|
|
|
// the lookahead pipeline
|
// the lookahead pipeline
|
`ifdef ENABLE_LOOKAHEAD
|
`ifdef ENABLE_LOOKAHEAD
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c2n CD (.q(acko), .a(oa), .b(pda[0])); // the C2N gate to avoid early withdrawal
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c2n CD (.q(acko), .a(oa), .b(pda[0])); // the C2N gate to avoid early withdrawal
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`else
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`else
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assign acko = oa;
|
assign acko = oa;
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`endif
|
`endif
|
|
|
// the ack lines for the last two pipeline stages
|
// the ack lines for the last two pipeline stages
|
assign pdan[0] = (~oa)&rst_n;
|
assign pdan[0] = (~oa)&rst_n;
|
assign pda4n[0] = (~deca)&rst_n;
|
assign pda4n[0] = (~deca)&rst_n;
|
assign pdan[1] = (~pda1)&rst_n;
|
assign pdan[1] = (~pda1)&rst_n;
|
assign pda4n[1] = pdan[1];
|
assign pda4n[1] = pdan[1];
|
|
|
`endif // !`ifdef ENABLE_CHANNEL_SLICING
|
`endif // !`ifdef ENABLE_CHANNEL_SLICING
|
|
|
|
|
endmodule // inp_buf
|
endmodule // inp_buf
|
|
|
|
|
// the routing decision making procedure, comparitors
|
// the routing decision making procedure, comparitors
|
module routing_decision (
|
module routing_decision (
|
addrx
|
addrx
|
,addry
|
,addry
|
,pipe_xd
|
,pipe_xd
|
,pipe_yd
|
,pipe_yd
|
,decision
|
,decision
|
);
|
);
|
|
|
// compare with (2,3)
|
// compare with (2,3)
|
input [7:0] addrx;
|
input [7:0] addrx;
|
input [7:0] addry;
|
input [7:0] addry;
|
|
|
input [7:0] pipe_xd;
|
input [7:0] pipe_xd;
|
input [7:0] pipe_yd;
|
input [7:0] pipe_yd;
|
output [5:0] decision;
|
output [5:0] decision;
|
|
|
wire [2:0] x_cmp [1:0];
|
wire [2:0] x_cmp [1:0];
|
wire [2:0] y_cmp [1:0];
|
wire [2:0] y_cmp [1:0];
|
|
|
comp4 X0 ( .a(pipe_xd[3:0]), .b(addrx[3:0]), .q(x_cmp[0]));
|
comp4 X0 ( .a(pipe_xd[3:0]), .b(addrx[3:0]), .q(x_cmp[0]));
|
comp4 X1 ( .a(pipe_xd[7:4]), .b(addrx[7:4]), .q(x_cmp[1]));
|
comp4 X1 ( .a(pipe_xd[7:4]), .b(addrx[7:4]), .q(x_cmp[1]));
|
comp4 Y0 ( .a(pipe_yd[3:0]), .b(addry[3:0]), .q(y_cmp[0]));
|
comp4 Y0 ( .a(pipe_yd[3:0]), .b(addry[3:0]), .q(y_cmp[0]));
|
comp4 Y1 ( .a(pipe_yd[7:4]), .b(addry[7:4]), .q(y_cmp[1]));
|
comp4 Y1 ( .a(pipe_yd[7:4]), .b(addry[7:4]), .q(y_cmp[1]));
|
|
|
assign decision[0] = x_cmp[1][0] | (x_cmp[1][2]&x_cmp[0][0]); // frame x > addr x
|
assign decision[0] = x_cmp[1][0] | (x_cmp[1][2]&x_cmp[0][0]); // frame x > addr x
|
assign decision[1] = x_cmp[1][1] | (x_cmp[1][2]&x_cmp[0][1]); // frame x < addr x
|
assign decision[1] = x_cmp[1][1] | (x_cmp[1][2]&x_cmp[0][1]); // frame x < addr x
|
assign decision[2] = x_cmp[1][2] & x_cmp[0][2]; // frame x = addr x
|
assign decision[2] = x_cmp[1][2] & x_cmp[0][2]; // frame x = addr x
|
assign decision[3] = y_cmp[1][0] | (y_cmp[1][2]&y_cmp[0][0]); // frame y > addr y
|
assign decision[3] = y_cmp[1][0] | (y_cmp[1][2]&y_cmp[0][0]); // frame y > addr y
|
assign decision[4] = y_cmp[1][1] | (y_cmp[1][2]&y_cmp[0][1]); // frame y < addr y
|
assign decision[4] = y_cmp[1][1] | (y_cmp[1][2]&y_cmp[0][1]); // frame y < addr y
|
assign decision[5] = y_cmp[1][2] & y_cmp[0][2]; // frame y = addr y
|
assign decision[5] = y_cmp[1][2] & y_cmp[0][2]; // frame y = addr y
|
|
|
endmodule // routing_decision
|
endmodule // routing_decision
|
|
|
