# Asynchronous SDM NoC
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# Asynchronous SDM NoC
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# (C)2011 Wei Song
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# (C)2011 Wei Song
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# Advanced Processor Technologies Group
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# Advanced Processor Technologies Group
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# Computer Science, the Univ. of Manchester, UK
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# Computer Science, the Univ. of Manchester, UK
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#
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#
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# Authors:
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# Authors:
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# Wei Song wsong83@gmail.com
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# Wei Song wsong83@gmail.com
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#
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#
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# License: LGPL 3.0 or later
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# License: LGPL 3.0 or later
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#
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#
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# Synthesis script
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# Synthesis script
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# currently using the Nangate 45nm cell lib.
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# currently using the Nangate 45nm cell lib.
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#
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#
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# History:
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# History:
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# 31/05/2009 Initial version. <wsong83@gmail.com>
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# 31/05/2009 Initial version. <wsong83@gmail.com>
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set rm_top router
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set rm_top router
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set rm_para "VCN=>1, DW=>8, IPD=>1, OPD=>1"
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set rm_para "VCN=>2, DW=>8, IPD=>1, OPD=>1"
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# working directory
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# working directory
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if {[file exists work ] && [file isdirectory work ]} {
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if {[file exists work ] && [file isdirectory work ]} {
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file delete -force work
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file delete -force work
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}
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}
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file mkdir work
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file mkdir work
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define_design_lib work -path work
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define_design_lib work -path work
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if {![file exists file ]} {
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if {![file exists file ]} {
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file mkdir file
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file mkdir file
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}
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}
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# set the technology libraries
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# set the technology libraries
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source ../../common/script/tech.tcl
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source ../../common/script/tech.tcl
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# read in source codes
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# read in source codes
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source script/source.tcl
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source script/source.tcl
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# elaborate the design
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# elaborate the design
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elaborate ${rm_top} -parameters ${rm_para}
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elaborate ${rm_top} -parameters ${rm_para}
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rename_design ${current_design} router
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rename_design ${current_design} router
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link
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link
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check_design
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check_design
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# read in constraints
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# read in constraints
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echo "It will be many errors in this step. Normally they are fine. For further info. please read the comments in the constraint scripts."
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echo "It will be many errors in this step. Normally they are fine. For further info. please read the comments in the constraint scripts."
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source script/constraint.tcl
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source script/constraint.tcl
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link
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link
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#report loops
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#report loops
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report_timing -loops -max_paths 2
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report_timing -loops -max_paths 2
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compile -boundary_optimization
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compile -boundary_optimization
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define_name_rules verilog -allowed "A-Za-z0-9_" -first_restricted "\\"
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define_name_rules verilog -allowed "A-Za-z0-9_" -first_restricted "\\"
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change_name -rules verilog -hierarchy
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change_name -rules verilog -hierarchy
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write -format verilog -hierarchy -out file/${current_design}_syn.v $current_design
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write -format verilog -hierarchy -out file/${current_design}_syn.v $current_design
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write_sdf -significant_digits 5 file/${current_design}.sdf
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write_sdf -significant_digits 5 file/${current_design}.sdf
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report_constraints -verbose
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report_constraints -verbose
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report_constraints
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report_constraints
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report_area
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report_area
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