/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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Data Clos network.
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Data Clos network.
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*** SystemVerilog is used ***
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*** SystemVerilog is used ***
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History:
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History:
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17/07/2010 Initial version. <wsong83@gmail.com>
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17/07/2010 Initial version. <wsong83@gmail.com>
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20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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23/05/2011 Clean up for opensource. <wsong83@gmail.com>
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23/05/2011 Clean up for opensource. <wsong83@gmail.com>
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21/06/2011 Prepare to support buffered Clos. <wsong83@gmail.com>
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21/06/2011 Prepare to support buffered Clos. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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module dclos (
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module dclos (
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// Outputs
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// Outputs
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so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
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so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
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eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
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eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
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wia, nia, eia, lia,
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wia, nia, eia, lia,
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// Inputs
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// Inputs
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si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
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si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
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ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
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ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
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woa, noa, eoa, loa, imcfg, scfg, ncfg, wcfg, ecfg, lcfg
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woa, noa, eoa, loa, imcfg, scfg, ncfg, wcfg, ecfg, lcfg
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`ifdef ENABLE_BUFFERED_CLOS
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`ifdef ENABLE_BUFFERED_CLOS
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, soa4, woa4, noa4, eoa4, loa4
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, soa4, woa4, noa4, eoa4, loa4
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`endif
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`endif
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, rst_n
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);
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);
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parameter MN = 2; // number of CMs
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parameter MN = 2; // number of CMs
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parameter NN = 2; // number of ports in an IM or OM, equ. to number of virtual circuits
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parameter NN = 2; // number of ports in an IM or OM, equ. to number of virtual circuits
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parameter DW = 8; // datawidth of a single virtual circuit/port
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parameter DW = 8; // datawidth of a single virtual circuit/port
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parameter SCN = DW/2; // number of 1-of-4 sub-channels in one port
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parameter SCN = DW/2; // number of 1-of-4 sub-channels in one port
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input [NN-1:0][SCN-1:0] si0, si1, si2, si3; // south input [0], X+1
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input [NN-1:0][SCN-1:0] si0, si1, si2, si3; // south input [0], X+1
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input [NN-1:0][SCN-1:0] wi0, wi1, wi2, wi3; // west input [1], Y-1
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input [NN-1:0][SCN-1:0] wi0, wi1, wi2, wi3; // west input [1], Y-1
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input [NN-1:0][SCN-1:0] ni0, ni1, ni2, ni3; // north input [2], X-1
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input [NN-1:0][SCN-1:0] ni0, ni1, ni2, ni3; // north input [2], X-1
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input [NN-1:0][SCN-1:0] ei0, ei1, ei2, ei3; // east input [3], Y+1
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input [NN-1:0][SCN-1:0] ei0, ei1, ei2, ei3; // east input [3], Y+1
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input [NN-1:0][SCN-1:0] li0, li1, li2, li3; // local input
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input [NN-1:0][SCN-1:0] li0, li1, li2, li3; // local input
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output [NN-1:0][SCN-1:0] so0, so1, so2, so3; // south output
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output [NN-1:0][SCN-1:0] so0, so1, so2, so3; // south output
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output [NN-1:0][SCN-1:0] wo0, wo1, wo2, wo3; // west output
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output [NN-1:0][SCN-1:0] wo0, wo1, wo2, wo3; // west output
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output [NN-1:0][SCN-1:0] no0, no1, no2, no3; // north output
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output [NN-1:0][SCN-1:0] no0, no1, no2, no3; // north output
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output [NN-1:0][SCN-1:0] eo0, eo1, eo2, eo3; // east output
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output [NN-1:0][SCN-1:0] eo0, eo1, eo2, eo3; // east output
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output [NN-1:0][SCN-1:0] lo0, lo1, lo2, lo3; // local output
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output [NN-1:0][SCN-1:0] lo0, lo1, lo2, lo3; // local output
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// eof bits and ack lines
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// eof bits and ack lines
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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input [NN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4;
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input [NN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4;
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output [NN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;
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output [NN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;
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output [NN-1:0][SCN-1:0] sia, wia, nia, eia, lia;
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output [NN-1:0][SCN-1:0] sia, wia, nia, eia, lia;
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input [NN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;
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input [NN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;
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`ifdef ENABLE_BUFFERED_CLOS
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`ifdef ENABLE_BUFFERED_CLOS
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input [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
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input [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
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`endif
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`endif
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`else
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`else
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input [NN-1:0] si4, wi4, ni4, ei4, li4;
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input [NN-1:0] si4, wi4, ni4, ei4, li4;
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output [NN-1:0] so4, wo4, no4, eo4, lo4;
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output [NN-1:0] so4, wo4, no4, eo4, lo4;
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output [NN-1:0] sia, wia, nia, eia, lia;
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output [NN-1:0] sia, wia, nia, eia, lia;
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input [NN-1:0] soa, woa, noa, eoa, loa;
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input [NN-1:0] soa, woa, noa, eoa, loa;
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`ifdef ENABLE_BUFFERED_CLOS
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`ifdef ENABLE_BUFFERED_CLOS
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input [NN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
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input [NN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
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`endif
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`endif
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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input [4:0][MN-1:0][NN-1:0] imcfg; // configuration for IMs
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input [4:0][MN-1:0][NN-1:0] imcfg; // configuration for IMs
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// configuration for CMs
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// configuration for CMs
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input [MN-1:0][1:0] scfg, ncfg;
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input [MN-1:0][1:0] scfg, ncfg;
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input [MN-1:0][3:0] wcfg, ecfg, lcfg;
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input [MN-1:0][3:0] wcfg, ecfg, lcfg;
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// no OMs
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// no OMs
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input rst_n; // globale active low reset
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// output of IMs
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// output of IMs
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wire [MN-1:0][SCN-1:0] imos0, imos1, imos2, imos3;
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wire [MN-1:0][SCN-1:0] imos0, imos1, imos2, imos3;
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wire [MN-1:0][SCN-1:0] imow0, imow1, imow2, imow3;
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wire [MN-1:0][SCN-1:0] imow0, imow1, imow2, imow3;
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wire [MN-1:0][SCN-1:0] imon0, imon1, imon2, imon3;
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wire [MN-1:0][SCN-1:0] imon0, imon1, imon2, imon3;
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wire [MN-1:0][SCN-1:0] imoe0, imoe1, imoe2, imoe3;
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wire [MN-1:0][SCN-1:0] imoe0, imoe1, imoe2, imoe3;
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wire [MN-1:0][SCN-1:0] imol0, imol1, imol2, imol3;
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wire [MN-1:0][SCN-1:0] imol0, imol1, imol2, imol3;
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [MN-1:0][SCN-1:0] imos4, imow4, imon4, imoe4, imol4;
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wire [MN-1:0][SCN-1:0] imos4, imow4, imon4, imoe4, imol4;
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wire [MN-1:0][SCN-1:0] imosa, imowa, imona, imoea, imola;
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wire [MN-1:0][SCN-1:0] imosa, imowa, imona, imoea, imola;
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`ifdef ENABLE_BUFFERED_CLOS
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`ifdef ENABLE_BUFFERED_CLOS
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wire [MN-1:0][SCN-1:0] imosa4, imowa4, imona4, imoea4, imola4;
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wire [MN-1:0][SCN-1:0] imosa4, imowa4, imona4, imoea4, imola4;
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wire [MN-1:0][SCN-1:0] imosdeca, imowdeca, imondeca, imoedeca, imoldeca;
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wire [MN-1:0][SCN-1:0] imoseofan, imoweofan, imoneofan, imoeeofan, imoleofan;
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`endif
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`endif
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`else
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`else
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wire [MN-1:0] imos4, imow4, imon4, imoe4, imol4;
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wire [MN-1:0] imos4, imow4, imon4, imoe4, imol4;
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wire [MN-1:0] imosa, imowa, imona, imoea, imola;
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wire [MN-1:0] imosa, imowa, imona, imoea, imola;
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`ifdef ENABLE_BUFFERED_CLOS
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`ifdef ENABLE_BUFFERED_CLOS
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wire [MN-1:0] imosdeca, imowdeca, imondeca, imoedeca, imoldeca;
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wire [MN-1:0] imosa4, imowa4, imona4, imoea4, imola4;
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wire [MN-1:0] imosa4, imowa4, imona4, imoea4, imola4;
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wire [MN-1:0] imoseofan, imoweofan, imoneofan, imoeeofan, imoleofan;
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`endif
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`endif
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`endif
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`endif
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// input of CMs
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// input of CMs
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wire [MN-1:0][4:0][SCN-1:0] cmi0, cmi1, cmi2, cmi3;
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wire [MN-1:0][4:0][SCN-1:0] cmi0, cmi1, cmi2, cmi3;
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [MN-1:0][4:0][SCN-1:0] cmi4, cmia;
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wire [MN-1:0][4:0][SCN-1:0] cmi4, cmia;
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`ifdef ENABLE_BUFFERED_CLOS
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wire [MN-1:0][4:0][SCN-1:0] cmian;
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`endif
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`else
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`else
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wire [MN-1:0][4:0] cmi4, cmia;
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wire [MN-1:0][4:0] cmi4, cmia;
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`ifdef ENABLE_BUFFERED_CLOS
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wire [MN-1:0][4:0] cmian;
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`endif
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`endif
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`endif
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// output of CMs
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// output of CMs
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wire [MN-1:0][4:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3;
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wire [MN-1:0][4:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3;
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [MN-1:0][4:0][SCN-1:0] cmo4, cmoa;
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wire [MN-1:0][4:0][SCN-1:0] cmo4, cmoa;
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`ifdef ENABLE_BUFFERED_CLOS
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`ifdef ENABLE_BUFFERED_CLOS
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wire [MN-1:0][4:0][SCN-1:0] cmoa4;
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wire [MN-1:0][4:0][SCN-1:0] cmoa4;
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`endif
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`endif
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`else
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`else
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wire [MN-1:0][4:0] cmo4, cmoa;
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wire [MN-1:0][4:0] cmo4, cmoa;
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`ifdef ENABLE_BUFFERED_CLOS
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`ifdef ENABLE_BUFFERED_CLOS
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wire [MN-1:0][4:0] cmoa4;
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wire [MN-1:0][4:0] cmoa4;
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`endif
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`endif
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`endif
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`endif
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genvar i,j,k;
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genvar i,j,k;
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dcb #(.NN(NN), .MN(MN), .DW(DW))
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dcb #(.NN(NN), .MN(MN), .DW(DW))
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SIM (
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SIM (
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.o0 ( imos0 ),
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.o0 ( imos0 ),
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.o1 ( imos1 ),
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.o1 ( imos1 ),
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.o2 ( imos2 ),
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.o2 ( imos2 ),
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.o3 ( imos3 ),
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.o3 ( imos3 ),
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.o4 ( imos4 ),
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.o4 ( imos4 ),
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.ia ( sia ),
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.ia ( sia ),
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.i0 ( si0 ),
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.i0 ( si0 ),
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.i1 ( si1 ),
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.i1 ( si1 ),
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.i2 ( si2 ),
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.i2 ( si2 ),
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.i3 ( si3 ),
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.i3 ( si3 ),
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.i4 ( si4 ),
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.i4 ( si4 ),
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.oa ( imosa ),
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.oa ( imosa ),
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`ifdef ENABLE_BUFFERED_CLOS
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`ifdef ENABLE_BUFFERED_CLOS
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.oa4 ( imosa4 ),
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.oa4 ( imosa4 ),
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`endif
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`endif
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.cfg ( imcfg[0] )
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.cfg ( imcfg[0] )
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);
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);
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dcb #(.NN(NN), .MN(MN), .DW(DW))
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dcb #(.NN(NN), .MN(MN), .DW(DW))
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WIM (
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WIM (
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.o0 ( imow0 ),
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.o0 ( imow0 ),
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.o1 ( imow1 ),
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.o1 ( imow1 ),
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.o2 ( imow2 ),
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.o2 ( imow2 ),
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.o3 ( imow3 ),
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.o3 ( imow3 ),
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.o4 ( imow4 ),
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.o4 ( imow4 ),
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.ia ( wia ),
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.ia ( wia ),
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.i0 ( wi0 ),
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.i0 ( wi0 ),
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.i1 ( wi1 ),
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.i1 ( wi1 ),
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.i2 ( wi2 ),
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.i2 ( wi2 ),
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.i3 ( wi3 ),
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.i3 ( wi3 ),
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.i4 ( wi4 ),
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.i4 ( wi4 ),
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.oa ( imowa ),
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.oa ( imowa ),
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`ifdef ENABLE_BUFFERED_CLOS
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`ifdef ENABLE_BUFFERED_CLOS
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.oa4 ( imowa4 ),
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.oa4 ( imowa4 ),
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`endif
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`endif
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.cfg ( imcfg[1] )
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.cfg ( imcfg[1] )
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);
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);
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dcb #(.NN(NN), .MN(MN), .DW(DW))
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dcb #(.NN(NN), .MN(MN), .DW(DW))
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NIM (
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NIM (
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.o0 ( imon0 ),
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.o0 ( imon0 ),
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.o1 ( imon1 ),
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.o1 ( imon1 ),
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.o2 ( imon2 ),
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.o2 ( imon2 ),
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.o3 ( imon3 ),
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.o3 ( imon3 ),
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.o4 ( imon4 ),
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.o4 ( imon4 ),
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.ia ( nia ),
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.ia ( nia ),
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.i0 ( ni0 ),
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.i0 ( ni0 ),
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.i1 ( ni1 ),
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.i1 ( ni1 ),
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.i2 ( ni2 ),
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.i2 ( ni2 ),
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.i3 ( ni3 ),
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.i3 ( ni3 ),
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.i4 ( ni4 ),
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.i4 ( ni4 ),
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.oa ( imona ),
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.oa ( imona ),
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`ifdef ENABLE_BUFFERED_CLOS
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`ifdef ENABLE_BUFFERED_CLOS
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.oa4 ( imona4 ),
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.oa4 ( imona4 ),
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`endif
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`endif
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.cfg ( imcfg[2] )
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.cfg ( imcfg[2] )
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);
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);
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dcb #(.NN(NN), .MN(MN), .DW(DW))
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dcb #(.NN(NN), .MN(MN), .DW(DW))
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EIM (
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EIM (
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.o0 ( imoe0 ),
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.o0 ( imoe0 ),
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.o1 ( imoe1 ),
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.o1 ( imoe1 ),
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.o2 ( imoe2 ),
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.o2 ( imoe2 ),
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.o3 ( imoe3 ),
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.o3 ( imoe3 ),
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.o4 ( imoe4 ),
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.o4 ( imoe4 ),
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.ia ( eia ),
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.ia ( eia ),
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.i0 ( ei0 ),
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.i0 ( ei0 ),
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.i1 ( ei1 ),
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.i1 ( ei1 ),
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.i2 ( ei2 ),
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.i2 ( ei2 ),
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.i3 ( ei3 ),
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.i3 ( ei3 ),
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.i4 ( ei4 ),
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.i4 ( ei4 ),
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.oa ( imoea ),
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.oa ( imoea ),
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`ifdef ENABLE_BUFFERED_CLOS
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`ifdef ENABLE_BUFFERED_CLOS
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.oa4 ( imoea4 ),
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.oa4 ( imoea4 ),
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`endif
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`endif
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.cfg ( imcfg[3] )
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.cfg ( imcfg[3] )
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);
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);
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dcb #(.NN(NN), .MN(MN), .DW(DW))
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dcb #(.NN(NN), .MN(MN), .DW(DW))
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LIM (
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LIM (
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.o0 ( imol0 ),
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.o0 ( imol0 ),
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.o1 ( imol1 ),
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.o1 ( imol1 ),
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.o2 ( imol2 ),
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.o2 ( imol2 ),
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.o3 ( imol3 ),
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.o3 ( imol3 ),
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.o4 ( imol4 ),
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.o4 ( imol4 ),
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.ia ( lia ),
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.ia ( lia ),
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.i0 ( li0 ),
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.i0 ( li0 ),
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.i1 ( li1 ),
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.i1 ( li1 ),
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.i2 ( li2 ),
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.i2 ( li2 ),
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.i3 ( li3 ),
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.i3 ( li3 ),
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.i4 ( li4 ),
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.i4 ( li4 ),
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.oa ( imola ),
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.oa ( imola ),
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`ifdef ENABLE_BUFFERED_CLOS
|
`ifdef ENABLE_BUFFERED_CLOS
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.oa4 ( imola4 ),
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.oa4 ( imola4 ),
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`endif
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`endif
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.cfg ( imcfg[4] )
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.cfg ( imcfg[4] )
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);
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);
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|
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generate for(i=0; i<MN; i++) begin: IMSHF
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generate for(i=0; i<MN; i++) begin: IMSHF
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`ifdef ENABLE_BUFFERED_CLOS
|
`ifdef ENABLE_BUFFERED_CLOS
|
// the buffer stage between IM and CM
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// the buffer stage between IM and CM
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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for(j=0; j<SCN; j++) begin:SC
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for(j=0; j<SCN; j++) begin:SC_S
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pipe4 #(.DW(2))
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pipe4 #(.DW(2))
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P (
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P (
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.o0 ( cmi0[i][0] ),
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.o0 ( cmi0[i][0] ),
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.o1 ( cmi1[i][0] ),
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.o1 ( cmi1[i][0] ),
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.o2 ( cmi2[i][0] ),
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.o2 ( cmi2[i][0] ),
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.o3 ( cmi3[i][0] ),
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.o3 ( cmi3[i][0] ),
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.ia ( imosa[i] ),
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.ia ( imosa[i] ),
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.i0 ( imos0[i] ),
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.i0 ( imos0[i] ),
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.i1 ( imos1[i] ),
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.i1 ( imos1[i] ),
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.i2 ( imos3[i] ),
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.i2 ( imos3[i] ),
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.i3 ( imos4[i] ),
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.i3 ( imos4[i] ),
|
.oa ( cmian[i][0] )
|
.oa ( cmian[i][0] )
|
);
|
);
|
|
|
pipen #(.DW(1))
|
pipen #(.DW(1))
|
PEoF (
|
PEoF (
|
.d_in_a ( imosa4[i] ),
|
.d_in_a ( ), // imosa4[i] ),
|
.d_out ( cmi4[i][0] ),
|
.d_out ( cmi4[i][0] ),
|
.d_in ( imos4[i] ),
|
.d_in ( imos4[i] ),
|
.d_out_a ( cmian[i][0] ),
|
.d_out_a ( imoseofan[i] ),
|
);
|
);
|
|
|
|
ppc PCTL (
|
|
.deca ( imosdeca[i] ),
|
|
.dia ( imosa4[i] ),
|
|
.eof ( cmi4[i][0] ),
|
|
.doa ( cmia[i][0] ),
|
|
.dec (
|
|
);
|
|
|
|
assign cmian[i][0] = (~cmia[i][0])&rst_n;
|
|
assign imoseofan[i] = (imosdeca[i])&rst_n;
|
|
end // block: SC
|
|
|
|
pipen #(.DW(4))
|
|
S_PDIR (
|
|
.d_in_a (
|
|
|
|
|
|
|
|
|
`else
|
`else
|
// shuffle the interconnects between IMs and CMs
|
// shuffle the interconnects between IMs and CMs
|
assign cmi0[i][0] = imos0[i];
|
assign cmi0[i][0] = imos0[i];
|
assign cmi1[i][0] = imos1[i];
|
assign cmi1[i][0] = imos1[i];
|
assign cmi2[i][0] = imos2[i];
|
assign cmi2[i][0] = imos2[i];
|
assign cmi3[i][0] = imos3[i];
|
assign cmi3[i][0] = imos3[i];
|
assign cmi4[i][0] = imos4[i];
|
assign cmi4[i][0] = imos4[i];
|
assign imosa[i] = cmia[i][0];
|
assign imosa[i] = cmia[i][0];
|
|
|
assign cmi0[i][1] = imow0[i];
|
assign cmi0[i][1] = imow0[i];
|
assign cmi1[i][1] = imow1[i];
|
assign cmi1[i][1] = imow1[i];
|
assign cmi2[i][1] = imow2[i];
|
assign cmi2[i][1] = imow2[i];
|
assign cmi3[i][1] = imow3[i];
|
assign cmi3[i][1] = imow3[i];
|
assign cmi4[i][1] = imow4[i];
|
assign cmi4[i][1] = imow4[i];
|
assign imowa[i] = cmia[i][1];
|
assign imowa[i] = cmia[i][1];
|
|
|
assign cmi0[i][2] = imon0[i];
|
assign cmi0[i][2] = imon0[i];
|
assign cmi1[i][2] = imon1[i];
|
assign cmi1[i][2] = imon1[i];
|
assign cmi2[i][2] = imon2[i];
|
assign cmi2[i][2] = imon2[i];
|
assign cmi3[i][2] = imon3[i];
|
assign cmi3[i][2] = imon3[i];
|
assign cmi4[i][2] = imon4[i];
|
assign cmi4[i][2] = imon4[i];
|
assign imona[i] = cmia[i][2];
|
assign imona[i] = cmia[i][2];
|
|
|
assign cmi0[i][3] = imoe0[i];
|
assign cmi0[i][3] = imoe0[i];
|
assign cmi1[i][3] = imoe1[i];
|
assign cmi1[i][3] = imoe1[i];
|
assign cmi2[i][3] = imoe2[i];
|
assign cmi2[i][3] = imoe2[i];
|
assign cmi3[i][3] = imoe3[i];
|
assign cmi3[i][3] = imoe3[i];
|
assign cmi4[i][3] = imoe4[i];
|
assign cmi4[i][3] = imoe4[i];
|
assign imoea[i] = cmia[i][3];
|
assign imoea[i] = cmia[i][3];
|
|
|
assign cmi0[i][4] = imol0[i];
|
assign cmi0[i][4] = imol0[i];
|
assign cmi1[i][4] = imol1[i];
|
assign cmi1[i][4] = imol1[i];
|
assign cmi2[i][4] = imol2[i];
|
assign cmi2[i][4] = imol2[i];
|
assign cmi3[i][4] = imol3[i];
|
assign cmi3[i][4] = imol3[i];
|
assign cmi4[i][4] = imol4[i];
|
assign cmi4[i][4] = imol4[i];
|
assign imola[i] = cmia[i][4];
|
assign imola[i] = cmia[i][4];
|
`endif // !`ifdef ENABLE_BUFFERED_CLOS
|
`endif // !`ifdef ENABLE_BUFFERED_CLOS
|
|
|
// CM modules
|
// CM modules
|
dcb_xy #(.VCN(1), .VCW(DW))
|
dcb_xy #(.VCN(1), .VCW(DW))
|
CM (
|
CM (
|
.sia ( cmia[i][0] ),
|
.sia ( cmia[i][0] ),
|
.wia ( cmia[i][1] ),
|
.wia ( cmia[i][1] ),
|
.nia ( cmia[i][2] ),
|
.nia ( cmia[i][2] ),
|
.eia ( cmia[i][3] ),
|
.eia ( cmia[i][3] ),
|
.lia ( cmia[i][4] ),
|
.lia ( cmia[i][4] ),
|
.so0 ( cmo0[i][0] ),
|
.so0 ( cmo0[i][0] ),
|
.so1 ( cmo1[i][0] ),
|
.so1 ( cmo1[i][0] ),
|
.so2 ( cmo2[i][0] ),
|
.so2 ( cmo2[i][0] ),
|
.so3 ( cmo3[i][0] ),
|
.so3 ( cmo3[i][0] ),
|
.so4 ( cmo4[i][0] ),
|
.so4 ( cmo4[i][0] ),
|
.wo0 ( cmo0[i][1] ),
|
.wo0 ( cmo0[i][1] ),
|
.wo1 ( cmo1[i][1] ),
|
.wo1 ( cmo1[i][1] ),
|
.wo2 ( cmo2[i][1] ),
|
.wo2 ( cmo2[i][1] ),
|
.wo3 ( cmo3[i][1] ),
|
.wo3 ( cmo3[i][1] ),
|
.wo4 ( cmo4[i][1] ) ,
|
.wo4 ( cmo4[i][1] ) ,
|
.no0 ( cmo0[i][2] ),
|
.no0 ( cmo0[i][2] ),
|
.no1 ( cmo1[i][2] ),
|
.no1 ( cmo1[i][2] ),
|
.no2 ( cmo2[i][2] ),
|
.no2 ( cmo2[i][2] ),
|
.no3 ( cmo3[i][2] ),
|
.no3 ( cmo3[i][2] ),
|
.no4 ( cmo4[i][2] ),
|
.no4 ( cmo4[i][2] ),
|
.eo0 ( cmo0[i][3] ),
|
.eo0 ( cmo0[i][3] ),
|
.eo1 ( cmo1[i][3] ),
|
.eo1 ( cmo1[i][3] ),
|
.eo2 ( cmo2[i][3] ),
|
.eo2 ( cmo2[i][3] ),
|
.eo3 ( cmo3[i][3] ),
|
.eo3 ( cmo3[i][3] ),
|
.eo4 ( cmo4[i][3] ),
|
.eo4 ( cmo4[i][3] ),
|
.lo0 ( cmo0[i][4] ),
|
.lo0 ( cmo0[i][4] ),
|
.lo1 ( cmo1[i][4] ),
|
.lo1 ( cmo1[i][4] ),
|
.lo2 ( cmo2[i][4] ),
|
.lo2 ( cmo2[i][4] ),
|
.lo3 ( cmo3[i][4] ),
|
.lo3 ( cmo3[i][4] ),
|
.lo4 ( cmo4[i][4] ),
|
.lo4 ( cmo4[i][4] ),
|
.si0 ( cmi0[i][0] ),
|
.si0 ( cmi0[i][0] ),
|
.si1 ( cmi1[i][0] ),
|
.si1 ( cmi1[i][0] ),
|
.si2 ( cmi2[i][0] ),
|
.si2 ( cmi2[i][0] ),
|
.si3 ( cmi3[i][0] ),
|
.si3 ( cmi3[i][0] ),
|
.si4 ( cmi4[i][0] ),
|
.si4 ( cmi4[i][0] ),
|
.wi0 ( cmi0[i][1] ),
|
.wi0 ( cmi0[i][1] ),
|
.wi1 ( cmi1[i][1] ),
|
.wi1 ( cmi1[i][1] ),
|
.wi2 ( cmi2[i][1] ),
|
.wi2 ( cmi2[i][1] ),
|
.wi3 ( cmi3[i][1] ),
|
.wi3 ( cmi3[i][1] ),
|
.wi4 ( cmi4[i][1] ),
|
.wi4 ( cmi4[i][1] ),
|
.ni0 ( cmi0[i][2] ),
|
.ni0 ( cmi0[i][2] ),
|
.ni1 ( cmi1[i][2] ),
|
.ni1 ( cmi1[i][2] ),
|
.ni2 ( cmi2[i][2] ),
|
.ni2 ( cmi2[i][2] ),
|
.ni3 ( cmi3[i][2] ),
|
.ni3 ( cmi3[i][2] ),
|
.ni4 ( cmi4[i][2] ),
|
.ni4 ( cmi4[i][2] ),
|
.ei0 ( cmi0[i][3] ),
|
.ei0 ( cmi0[i][3] ),
|
.ei1 ( cmi1[i][3] ),
|
.ei1 ( cmi1[i][3] ),
|
.ei2 ( cmi2[i][3] ),
|
.ei2 ( cmi2[i][3] ),
|
.ei3 ( cmi3[i][3] ),
|
.ei3 ( cmi3[i][3] ),
|
.ei4 ( cmi4[i][3] ),
|
.ei4 ( cmi4[i][3] ),
|
.li0 ( cmi0[i][4] ),
|
.li0 ( cmi0[i][4] ),
|
.li1 ( cmi1[i][4] ),
|
.li1 ( cmi1[i][4] ),
|
.li2 ( cmi2[i][4] ),
|
.li2 ( cmi2[i][4] ),
|
.li3 ( cmi3[i][4] ),
|
.li3 ( cmi3[i][4] ),
|
.li4 ( cmi4[i][4] ),
|
.li4 ( cmi4[i][4] ),
|
.soa ( cmoa[i][0] ),
|
.soa ( cmoa[i][0] ),
|
.woa ( cmoa[i][1] ),
|
.woa ( cmoa[i][1] ),
|
.noa ( cmoa[i][2] ),
|
.noa ( cmoa[i][2] ),
|
.eoa ( cmoa[i][3] ),
|
.eoa ( cmoa[i][3] ),
|
.loa ( cmoa[i][4] ),
|
.loa ( cmoa[i][4] ),
|
`ifdef ENABLE_BUFFERED_CLOS
|
`ifdef ENABLE_BUFFERED_CLOS
|
.soa4 ( cmoa4[i][0] ),
|
.soa4 ( cmoa4[i][0] ),
|
.woa4 ( cmoa4[i][1] ),
|
.woa4 ( cmoa4[i][1] ),
|
.noa4 ( cmoa4[i][2] ),
|
.noa4 ( cmoa4[i][2] ),
|
.eoa4 ( cmoa4[i][3] ),
|
.eoa4 ( cmoa4[i][3] ),
|
.loa4 ( cmoa4[i][4] ),
|
.loa4 ( cmoa4[i][4] ),
|
`endif
|
`endif
|
.wcfg ( wcfg[i] ),
|
.wcfg ( wcfg[i] ),
|
.ecfg ( ecfg[i] ),
|
.ecfg ( ecfg[i] ),
|
.lcfg ( lcfg[i] ),
|
.lcfg ( lcfg[i] ),
|
.scfg ( scfg[i] ),
|
.scfg ( scfg[i] ),
|
.ncfg ( ncfg[i] )
|
.ncfg ( ncfg[i] )
|
);
|
);
|
|
|
// shuffle between CMs and OMs(OPs)
|
// shuffle between CMs and OMs(OPs)
|
assign so0[i] = cmo0[i][0];
|
assign so0[i] = cmo0[i][0];
|
assign so1[i] = cmo1[i][0];
|
assign so1[i] = cmo1[i][0];
|
assign so2[i] = cmo2[i][0];
|
assign so2[i] = cmo2[i][0];
|
assign so3[i] = cmo3[i][0];
|
assign so3[i] = cmo3[i][0];
|
assign so4[i] = cmo4[i][0];
|
assign so4[i] = cmo4[i][0];
|
assign cmoa[i][0] = soa[i];
|
assign cmoa[i][0] = soa[i];
|
|
|
assign wo0[i] = cmo0[i][1];
|
assign wo0[i] = cmo0[i][1];
|
assign wo1[i] = cmo1[i][1];
|
assign wo1[i] = cmo1[i][1];
|
assign wo2[i] = cmo2[i][1];
|
assign wo2[i] = cmo2[i][1];
|
assign wo3[i] = cmo3[i][1];
|
assign wo3[i] = cmo3[i][1];
|
assign wo4[i] = cmo4[i][1];
|
assign wo4[i] = cmo4[i][1];
|
assign cmoa[i][1] = woa[i];
|
assign cmoa[i][1] = woa[i];
|
|
|
assign no0[i] = cmo0[i][2];
|
assign no0[i] = cmo0[i][2];
|
assign no1[i] = cmo1[i][2];
|
assign no1[i] = cmo1[i][2];
|
assign no2[i] = cmo2[i][2];
|
assign no2[i] = cmo2[i][2];
|
assign no3[i] = cmo3[i][2];
|
assign no3[i] = cmo3[i][2];
|
assign no4[i] = cmo4[i][2];
|
assign no4[i] = cmo4[i][2];
|
assign cmoa[i][2] = noa[i];
|
assign cmoa[i][2] = noa[i];
|
|
|
assign eo0[i] = cmo0[i][3];
|
assign eo0[i] = cmo0[i][3];
|
assign eo1[i] = cmo1[i][3];
|
assign eo1[i] = cmo1[i][3];
|
assign eo2[i] = cmo2[i][3];
|
assign eo2[i] = cmo2[i][3];
|
assign eo3[i] = cmo3[i][3];
|
assign eo3[i] = cmo3[i][3];
|
assign eo4[i] = cmo4[i][3];
|
assign eo4[i] = cmo4[i][3];
|
assign cmoa[i][3] = eoa[i];
|
assign cmoa[i][3] = eoa[i];
|
|
|
assign lo0[i] = cmo0[i][4];
|
assign lo0[i] = cmo0[i][4];
|
assign lo1[i] = cmo1[i][4];
|
assign lo1[i] = cmo1[i][4];
|
assign lo2[i] = cmo2[i][4];
|
assign lo2[i] = cmo2[i][4];
|
assign lo3[i] = cmo3[i][4];
|
assign lo3[i] = cmo3[i][4];
|
assign lo4[i] = cmo4[i][4];
|
assign lo4[i] = cmo4[i][4];
|
assign cmoa[i][4] = loa[i];
|
assign cmoa[i][4] = loa[i];
|
|
|
`ifdef ENABLE_BUFFERED_CLOS
|
`ifdef ENABLE_BUFFERED_CLOS
|
assign cmoa4[i][0] = soa4[i];
|
assign cmoa4[i][0] = soa4[i];
|
assign cmoa4[i][1] = woa4[i];
|
assign cmoa4[i][1] = woa4[i];
|
assign cmoa4[i][2] = noa4[i];
|
assign cmoa4[i][2] = noa4[i];
|
assign cmoa4[i][3] = eoa4[i];
|
assign cmoa4[i][3] = eoa4[i];
|
assign cmoa4[i][4] = loa4[i];
|
assign cmoa4[i][4] = loa4[i];
|
`endif
|
`endif
|
end // block: IMSHF
|
end // block: IMSHF
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
endmodule // dclos
|
endmodule // dclos
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|