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/*

/*

 Asynchronous SDM NoC

 Asynchronous SDM NoC

 (C)2011 Wei Song

 (C)2011 Wei Song

 Advanced Processor Technologies Group

 Advanced Processor Technologies Group

 Computer Science, the Univ. of Manchester, UK

 Computer Science, the Univ. of Manchester, UK

 Authors:

 Authors:

 Wei Song     wsong83@gmail.com

 Wei Song     wsong83@gmail.com

 License: LGPL 3.0 or later

 License: LGPL 3.0 or later

 A single 4-phase 1-of-n pipeline stage.

 A single 4-phase 1-of-n pipeline stage.

 History:

 History:

 05/05/2009  Initial version. <wsong83@gmail.com>

 05/05/2009  Initial version. <wsong83@gmail.com>

 01/06/2011  Clean up for opensource. <wsong83@gmail.com>

 01/06/2011  Clean up for opensource. <wsong83@gmail.com>

*/

*/

module pipen(/*AUTOARG*/

module pipen(/*AUTOARG*/

   // Outputs

   // Outputs

   d_in_a, d_out,

   d_in_a, d_out,

   // Inputs

   // Inputs

   d_in, d_out_a

   d_in, d_out_a

   );

   );

   parameter DW = 4;            // the wire count, the "n" of the 1-of-n code

   parameter DW = 4;            // the wire count, the "n" of the 1-of-n code

   input [DW-1:0]   d_in;

   input [DW-1:0]   d_in;

   output           d_in_a;

   output           d_in_a;

   output [DW-1:0]  d_out;

   output [DW-1:0]  d_out;

   input            d_out_a;

   input            d_out_a;

   genvar           i;

   genvar           i;

   // the data pipe stage

   // the data pipe stage

   generate for (i=0; i<DW; i=i+1) begin:DD

   generate for (i=0; i<DW; i=i+1) begin:DD

       dc2 DC  (.d(d_in[i]),       .a(d_out_a),   .q(d_out[i]));

       dc2 DC  (.d(d_in[i]),       .a(d_out_a),   .q(d_out[i]));

   end endgenerate

   end endgenerate

   assign d_in_a = |d_out;

   assign d_in_a = |d_out;

endmodule // pipen

endmodule // pipen