/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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Asynchronous VC router.
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Asynchronous VC router.
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History:
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History:
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05/04/2010 Initial version. <wsong83@gmail.com>
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05/04/2010 Initial version. <wsong83@gmail.com>
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02/06/2011 Clean up for opensource. <wsong83@gmail.com>
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02/06/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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module router (/*AUTOARG*/
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module router (/*AUTOARG*/
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// Outputs
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// Outputs
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sia, wia, nia, eia, lia, sic, wic, nic, eic, lic, so0, so1, so2,
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sia, wia, nia, eia, lia, sic, wic, nic, eic, lic, so0, so1, so2,
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so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0, eo1, eo2, eo3,
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so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0, eo1, eo2, eo3,
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lo0, lo1, lo2, lo3, soft, woft, noft, eoft, loft, sovc, wovc, novc,
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lo0, lo1, lo2, lo3, soft, woft, noft, eoft, loft, sovc, wovc, novc,
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eovc, lovc, soca, woca, noca, eoca, loca,
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eovc, lovc, soca, woca, noca, eoca, loca,
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// Inputs
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// Inputs
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si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
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si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
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ei1, ei2, ei3, li0, li1, li2, li3, sift, wift, nift, eift, lift,
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ei1, ei2, ei3, li0, li1, li2, li3, sift, wift, nift, eift, lift,
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sivc, wivc, nivc, eivc, livc, sica, wica, nica, eica, lica, soa,
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sivc, wivc, nivc, eivc, livc, sica, wica, nica, eica, lica, soa,
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woa, noa, eoa, loa, soc, woc, noc, eoc, loc, addrx, addry, rst_n
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woa, noa, eoa, loa, soc, woc, noc, eoc, loc, addrx, addry, rst_n
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);
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);
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parameter VCN = 2; // number of VCs per direction
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parameter VCN = 2; // number of VCs per direction
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parameter DW = 32; // data width of an input port
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parameter DW = 32; // data width of an input port
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parameter PD = 1; // the depth of a input VC buffer
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parameter PD = 1; // the depth of a input VC buffer
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parameter FT = 3; // the number of flit types, currently 3 (HD, DATA, TAIL)
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parameter FT = 3; // the number of flit types, currently 3 (HD, DATA, TAIL)
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|
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parameter FCPD = PD;
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parameter FCPD = PD;
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parameter SCN = DW/2;
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parameter SCN = DW/2;
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// input ports
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// input ports
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input [SCN-1:0] si0, si1, si2, si3;
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input [SCN-1:0] si0, si1, si2, si3;
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input [SCN-1:0] wi0, wi1, wi2, wi3;
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input [SCN-1:0] wi0, wi1, wi2, wi3;
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input [SCN-1:0] ni0, ni1, ni2, ni3;
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input [SCN-1:0] ni0, ni1, ni2, ni3;
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input [SCN-1:0] ei0, ei1, ei2, ei3;
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input [SCN-1:0] ei0, ei1, ei2, ei3;
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input [SCN-1:0] li0, li1, li2, li3;
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input [SCN-1:0] li0, li1, li2, li3;
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input [FT-1:0] sift, wift, nift, eift, lift;
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input [FT-1:0] sift, wift, nift, eift, lift;
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input [VCN-1:0] sivc, wivc, nivc, eivc, livc;
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input [VCN-1:0] sivc, wivc, nivc, eivc, livc;
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output sia, wia, nia, eia, lia;
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output sia, wia, nia, eia, lia;
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output [VCN-1:0] sic, wic, nic, eic, lic;
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output [VCN-1:0] sic, wic, nic, eic, lic;
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input [VCN-1:0] sica, wica, nica, eica, lica;
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input [VCN-1:0] sica, wica, nica, eica, lica;
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// output ports
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// output ports
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output [SCN-1:0] so0, so1, so2, so3;
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output [SCN-1:0] so0, so1, so2, so3;
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output [SCN-1:0] wo0, wo1, wo2, wo3;
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output [SCN-1:0] wo0, wo1, wo2, wo3;
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output [SCN-1:0] no0, no1, no2, no3;
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output [SCN-1:0] no0, no1, no2, no3;
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output [SCN-1:0] eo0, eo1, eo2, eo3;
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output [SCN-1:0] eo0, eo1, eo2, eo3;
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output [SCN-1:0] lo0, lo1, lo2, lo3;
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output [SCN-1:0] lo0, lo1, lo2, lo3;
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output [FT-1:0] soft, woft, noft, eoft, loft;
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output [FT-1:0] soft, woft, noft, eoft, loft;
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output [VCN-1:0] sovc, wovc, novc, eovc, lovc;
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output [VCN-1:0] sovc, wovc, novc, eovc, lovc;
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input soa, woa, noa, eoa, loa;
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input soa, woa, noa, eoa, loa;
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input [VCN-1:0] soc, woc, noc, eoc, loc;
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input [VCN-1:0] soc, woc, noc, eoc, loc;
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output [VCN-1:0] soca, woca, noca, eoca, loca;
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output [VCN-1:0] soca, woca, noca, eoca, loca;
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// local address, in 1-of-4 format
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// local address, in 1-of-4 format
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input [7:0] addrx, addry;
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input [7:0] addrx, addry;
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// active-low reset
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// active-low reset
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input rst_n;
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input rst_n;
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//----------------------------------
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//----------------------------------
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// input to crossbar
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// input to crossbar
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wire [VCN-1:0][SCN-1:0] s2cb0, s2cb1, s2cb2, s2cb3;
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wire [VCN-1:0][SCN-1:0] s2cb0, s2cb1, s2cb2, s2cb3;
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wire [VCN-1:0][SCN-1:0] w2cb0, w2cb1, w2cb2, w2cb3;
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wire [VCN-1:0][SCN-1:0] w2cb0, w2cb1, w2cb2, w2cb3;
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wire [VCN-1:0][SCN-1:0] n2cb0, n2cb1, n2cb2, n2cb3;
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wire [VCN-1:0][SCN-1:0] n2cb0, n2cb1, n2cb2, n2cb3;
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wire [VCN-1:0][SCN-1:0] e2cb0, e2cb1, e2cb2, e2cb3;
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wire [VCN-1:0][SCN-1:0] e2cb0, e2cb1, e2cb2, e2cb3;
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wire [VCN-1:0][SCN-1:0] l2cb0, l2cb1, l2cb2, l2cb3;
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wire [VCN-1:0][SCN-1:0] l2cb0, l2cb1, l2cb2, l2cb3;
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wire [VCN-1:0][FT-1:0] s2cbt, w2cbt, n2cbt, e2cbt, l2cbt;
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wire [VCN-1:0][FT-1:0] s2cbt, w2cbt, n2cbt, e2cbt, l2cbt;
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wire [VCN-1:0][3:0] s2cbrtg, n2cbrtg, l2cbrtg;
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wire [VCN-1:0][3:0] s2cbrtg, n2cbrtg, l2cbrtg;
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wire [VCN-1:0][1:0] w2cbrtg, e2cbrtg;
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wire [VCN-1:0][1:0] w2cbrtg, e2cbrtg;
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wire [VCN-1:0] s2cba, w2cba, n2cba, e2cba, l2cba;
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wire [VCN-1:0] s2cba, w2cba, n2cba, e2cba, l2cba;
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// VC requests
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// VC requests
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wire [VCN-1:0][3:0] svcr, nvcr, lvcr;
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wire [VCN-1:0][3:0] svcr, nvcr, lvcr;
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wire [VCN-1:0] svcra, nvcra, lvcra;
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wire [VCN-1:0] svcra, nvcra, lvcra;
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wire [VCN-1:0][1:0] wvcr, evcr;
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wire [VCN-1:0][1:0] wvcr, evcr;
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wire [VCN-1:0] wvcra, evcra;
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wire [VCN-1:0] wvcra, evcra;
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// SW requests
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// SW requests
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wire [VCN-1:0][1:0] siswr, wiswr, niswr, eiswr, liswr;
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wire [VCN-1:0][1:0] siswr, wiswr, niswr, eiswr, liswr;
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wire [VCN-1:0][3:0] siswrt, niswrt, liswrt;
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wire [VCN-1:0][3:0] siswrt, niswrt, liswrt;
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wire [VCN-1:0][1:0] wiswrt, eiswrt;
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wire [VCN-1:0][1:0] wiswrt, eiswrt;
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// crossbar to output
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// crossbar to output
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wire [SCN-1:0] cb2s0, cb2s1, cb2s2, cb2s3;
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wire [SCN-1:0] cb2s0, cb2s1, cb2s2, cb2s3;
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wire [SCN-1:0] cb2w0, cb2w1, cb2w2, cb2w3;
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wire [SCN-1:0] cb2w0, cb2w1, cb2w2, cb2w3;
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wire [SCN-1:0] cb2n0, cb2n1, cb2n2, cb2n3;
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wire [SCN-1:0] cb2n0, cb2n1, cb2n2, cb2n3;
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wire [SCN-1:0] cb2e0, cb2e1, cb2e2, cb2e3;
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wire [SCN-1:0] cb2e0, cb2e1, cb2e2, cb2e3;
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wire [SCN-1:0] cb2l0, cb2l1, cb2l2, cb2l3;
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wire [SCN-1:0] cb2l0, cb2l1, cb2l2, cb2l3;
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wire [FT-1:0] cb2st, cb2wt, cb2nt, cb2et, cb2lt;
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wire [FT-1:0] cb2st, cb2wt, cb2nt, cb2et, cb2lt;
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wire cb2sa, cb2wa, cb2na, cb2ea, cb2la;
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wire cb2sa, cb2wa, cb2na, cb2ea, cb2la;
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// SW requests to VC arbiters in output buffers
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// SW requests to VC arbiters in output buffers
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wire [VCN-1:0] soswr, woswr, noswr, eoswr, loswr;
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wire [VCN-1:0] soswr, woswr, noswr, eoswr, loswr;
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wire [VCN-1:0] soswa, woswa, noswa, eoswa, loswa;
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wire [VCN-1:0] soswa, woswa, noswa, eoswa, loswa;
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//-------------------------------------
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//-------------------------------------
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// south input buffer
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// south input buffer
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inpbuf #(.DW(DW), .VCN(VCN), .DIR(0), .SN(4), .PD(PD), .FT(FT))
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inpbuf #(.DW(DW), .VCN(VCN), .DIR(0), .SN(4), .PD(PD), .FT(FT))
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SIB (
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SIB (
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.dia ( sia ),
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.dia ( sia ),
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.cor ( sic ),
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.cor ( sic ),
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.do0 ( s2cb0 ),
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.do0 ( s2cb0 ),
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.do1 ( s2cb1 ),
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.do1 ( s2cb1 ),
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.do2 ( s2cb2 ),
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.do2 ( s2cb2 ),
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.do3 ( s2cb3 ),
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.do3 ( s2cb3 ),
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.dot ( s2cbt ),
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.dot ( s2cbt ),
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.dortg ( s2cbrtg ),
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.dortg ( s2cbrtg ),
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.vcr ( svcr ),
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.vcr ( svcr ),
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.swr ( siswr ),
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.swr ( siswr ),
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.di0 ( si0 ),
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.di0 ( si0 ),
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.di1 ( si1 ),
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.di1 ( si1 ),
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.di2 ( si2 ),
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.di2 ( si2 ),
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.di3 ( si3 ),
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.di3 ( si3 ),
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.dit ( sift ),
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.dit ( sift ),
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.divc ( sivc ),
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.divc ( sivc ),
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.coa ( sica ),
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.coa ( sica ),
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.doa ( s2cba ),
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.doa ( s2cba ),
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.vcra ( svcra ),
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.vcra ( svcra ),
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.swrt ( siswrt ),
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.swrt ( siswrt ),
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.addrx ( addrx ),
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.addrx ( addrx ),
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.addry ( addry ),
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.addry ( addry ),
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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// west input buffer
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// west input buffer
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inpbuf #(.DW(DW), .VCN(VCN), .DIR(1), .SN(2), .PD(PD), .FT(FT))
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inpbuf #(.DW(DW), .VCN(VCN), .DIR(1), .SN(2), .PD(PD), .FT(FT))
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WIB (
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WIB (
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.dia ( wia ),
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.dia ( wia ),
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.cor ( wic ),
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.cor ( wic ),
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.do0 ( w2cb0 ),
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.do0 ( w2cb0 ),
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.do1 ( w2cb1 ),
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.do1 ( w2cb1 ),
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.do2 ( w2cb2 ),
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.do2 ( w2cb2 ),
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.do3 ( w2cb3 ),
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.do3 ( w2cb3 ),
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.dot ( w2cbt ),
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.dot ( w2cbt ),
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.dortg ( w2cbrtg ),
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.dortg ( w2cbrtg ),
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.vcr ( wvcr ),
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.vcr ( wvcr ),
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.swr ( wiswr ),
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.swr ( wiswr ),
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.di0 ( wi0 ),
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.di0 ( wi0 ),
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.di1 ( wi1 ),
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.di1 ( wi1 ),
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.di2 ( wi2 ),
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.di2 ( wi2 ),
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.di3 ( wi3 ),
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.di3 ( wi3 ),
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.dit ( wift ),
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.dit ( wift ),
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.divc ( wivc ),
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.divc ( wivc ),
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.coa ( wica ),
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.coa ( wica ),
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.doa ( w2cba ),
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.doa ( w2cba ),
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.vcra ( wvcra ),
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.vcra ( wvcra ),
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.swrt ( wiswrt ),
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.swrt ( wiswrt ),
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.addrx ( addrx ),
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.addrx ( addrx ),
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.addry ( addry ),
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.addry ( addry ),
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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|
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// north input buffer
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// north input buffer
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inpbuf #(.DW(DW), .VCN(VCN), .DIR(2), .SN(4), .PD(PD), .FT(FT))
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inpbuf #(.DW(DW), .VCN(VCN), .DIR(2), .SN(4), .PD(PD), .FT(FT))
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NIB (
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NIB (
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.dia ( nia ),
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.dia ( nia ),
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.cor ( nic ),
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.cor ( nic ),
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.do0 ( n2cb0 ),
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.do0 ( n2cb0 ),
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.do1 ( n2cb1 ),
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.do1 ( n2cb1 ),
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.do2 ( n2cb2 ),
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.do2 ( n2cb2 ),
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.do3 ( n2cb3 ),
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.do3 ( n2cb3 ),
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.dot ( n2cbt ),
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.dot ( n2cbt ),
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.dortg ( n2cbrtg ),
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.dortg ( n2cbrtg ),
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.vcr ( nvcr ),
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.vcr ( nvcr ),
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.swr ( niswr ),
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.swr ( niswr ),
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.di0 ( ni0 ),
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.di0 ( ni0 ),
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.di1 ( ni1 ),
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.di1 ( ni1 ),
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.di2 ( ni2 ),
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.di2 ( ni2 ),
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.di3 ( ni3 ),
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.di3 ( ni3 ),
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.dit ( nift ),
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.dit ( nift ),
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.divc ( nivc ),
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.divc ( nivc ),
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.coa ( nica ),
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.coa ( nica ),
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.doa ( n2cba ),
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.doa ( n2cba ),
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.vcra ( nvcra ),
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.vcra ( nvcra ),
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.swrt ( niswrt ),
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.swrt ( niswrt ),
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.addrx ( addrx ),
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.addrx ( addrx ),
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.addry ( addry ),
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.addry ( addry ),
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.rst_n ( rst_n )
|
.rst_n ( rst_n )
|
);
|
);
|
|
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// east input buffer
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// east input buffer
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inpbuf #(.DW(DW), .VCN(VCN), .DIR(3), .SN(2), .PD(PD), .FT(FT))
|
inpbuf #(.DW(DW), .VCN(VCN), .DIR(3), .SN(2), .PD(PD), .FT(FT))
|
EIB (
|
EIB (
|
.dia ( eia ),
|
.dia ( eia ),
|
.cor ( eic ),
|
.cor ( eic ),
|
.do0 ( e2cb0 ),
|
.do0 ( e2cb0 ),
|
.do1 ( e2cb1 ),
|
.do1 ( e2cb1 ),
|
.do2 ( e2cb2 ),
|
.do2 ( e2cb2 ),
|
.do3 ( e2cb3 ),
|
.do3 ( e2cb3 ),
|
.dot ( e2cbt ),
|
.dot ( e2cbt ),
|
.dortg ( e2cbrtg ),
|
.dortg ( e2cbrtg ),
|
.vcr ( evcr ),
|
.vcr ( evcr ),
|
.swr ( eiswr ),
|
.swr ( eiswr ),
|
.di0 ( ei0 ),
|
.di0 ( ei0 ),
|
.di1 ( ei1 ),
|
.di1 ( ei1 ),
|
.di2 ( ei2 ),
|
.di2 ( ei2 ),
|
.di3 ( ei3 ),
|
.di3 ( ei3 ),
|
.dit ( eift ),
|
.dit ( eift ),
|
.divc ( eivc ),
|
.divc ( eivc ),
|
.coa ( eica ),
|
.coa ( eica ),
|
.doa ( e2cba ),
|
.doa ( e2cba ),
|
.vcra ( evcra ),
|
.vcra ( evcra ),
|
.swrt ( eiswrt ),
|
.swrt ( eiswrt ),
|
.addrx ( addrx ),
|
.addrx ( addrx ),
|
.addry ( addry ),
|
.addry ( addry ),
|
.rst_n ( rst_n )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
// local input buffer
|
// local input buffer
|
inpbuf #(.DW(DW), .VCN(VCN), .DIR(4), .SN(4), .PD(PD), .FT(FT))
|
inpbuf #(.DW(DW), .VCN(VCN), .DIR(4), .SN(4), .PD(PD), .FT(FT))
|
LIB (
|
LIB (
|
.dia ( lia ),
|
.dia ( lia ),
|
.cor ( lic ),
|
.cor ( lic ),
|
.do0 ( l2cb0 ),
|
.do0 ( l2cb0 ),
|
.do1 ( l2cb1 ),
|
.do1 ( l2cb1 ),
|
.do2 ( l2cb2 ),
|
.do2 ( l2cb2 ),
|
.do3 ( l2cb3 ),
|
.do3 ( l2cb3 ),
|
.dot ( l2cbt ),
|
.dot ( l2cbt ),
|
.dortg ( l2cbrtg ),
|
.dortg ( l2cbrtg ),
|
.vcr ( lvcr ),
|
.vcr ( lvcr ),
|
.swr ( liswr ),
|
.swr ( liswr ),
|
.di0 ( li0 ),
|
.di0 ( li0 ),
|
.di1 ( li1 ),
|
.di1 ( li1 ),
|
.di2 ( li2 ),
|
.di2 ( li2 ),
|
.di3 ( li3 ),
|
.di3 ( li3 ),
|
.dit ( lift ),
|
.dit ( lift ),
|
.divc ( livc ),
|
.divc ( livc ),
|
.coa ( lica ),
|
.coa ( lica ),
|
.doa ( l2cba ),
|
.doa ( l2cba ),
|
.vcra ( lvcra ),
|
.vcra ( lvcra ),
|
.swrt ( liswrt ),
|
.swrt ( liswrt ),
|
.addrx ( addrx ),
|
.addrx ( addrx ),
|
.addry ( addry ),
|
.addry ( addry ),
|
.rst_n ( rst_n )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
// south output buffer
|
// south output buffer
|
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
|
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
|
SOB (
|
SOB (
|
.dia ( cb2sa ),
|
.dia ( cb2sa ),
|
.do0 ( so0 ),
|
.do0 ( so0 ),
|
.do1 ( so1 ),
|
.do1 ( so1 ),
|
.do2 ( so2 ),
|
.do2 ( so2 ),
|
.do3 ( so3 ),
|
.do3 ( so3 ),
|
.dot ( soft ),
|
.dot ( soft ),
|
.dovc ( sovc ),
|
.dovc ( sovc ),
|
.afc ( soca ),
|
.afc ( soca ),
|
.vca ( soswa ),
|
.vca ( soswa ),
|
.di0 ( cb2s0 ),
|
.di0 ( cb2s0 ),
|
.di1 ( cb2s1 ),
|
.di1 ( cb2s1 ),
|
.di2 ( cb2s2 ),
|
.di2 ( cb2s2 ),
|
.di3 ( cb2s3 ),
|
.di3 ( cb2s3 ),
|
.dit ( cb2st ),
|
.dit ( cb2st ),
|
.doa ( soa ),
|
.doa ( soa ),
|
.credit( soc ),
|
.credit( soc ),
|
.vcr ( soswr ),
|
.vcr ( soswr ),
|
.rst_n ( rst_n )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
// west output buffer
|
// west output buffer
|
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
|
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
|
WOB (
|
WOB (
|
.dia ( cb2wa ),
|
.dia ( cb2wa ),
|
.do0 ( wo0 ),
|
.do0 ( wo0 ),
|
.do1 ( wo1 ),
|
.do1 ( wo1 ),
|
.do2 ( wo2 ),
|
.do2 ( wo2 ),
|
.do3 ( wo3 ),
|
.do3 ( wo3 ),
|
.dot ( woft ),
|
.dot ( woft ),
|
.dovc ( wovc ),
|
.dovc ( wovc ),
|
.afc ( woca ),
|
.afc ( woca ),
|
.vca ( woswa ),
|
.vca ( woswa ),
|
.di0 ( cb2w0 ),
|
.di0 ( cb2w0 ),
|
.di1 ( cb2w1 ),
|
.di1 ( cb2w1 ),
|
.di2 ( cb2w2 ),
|
.di2 ( cb2w2 ),
|
.di3 ( cb2w3 ),
|
.di3 ( cb2w3 ),
|
.dit ( cb2wt ),
|
.dit ( cb2wt ),
|
.doa ( woa ),
|
.doa ( woa ),
|
.credit( woc ),
|
.credit( woc ),
|
.vcr ( woswr ),
|
.vcr ( woswr ),
|
.rst_n ( rst_n )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
// north output buffer
|
// north output buffer
|
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
|
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
|
NOB (
|
NOB (
|
.dia ( cb2na ),
|
.dia ( cb2na ),
|
.do0 ( no0 ),
|
.do0 ( no0 ),
|
.do1 ( no1 ),
|
.do1 ( no1 ),
|
.do2 ( no2 ),
|
.do2 ( no2 ),
|
.do3 ( no3 ),
|
.do3 ( no3 ),
|
.dot ( noft ),
|
.dot ( noft ),
|
.dovc ( novc ),
|
.dovc ( novc ),
|
.afc ( noca ),
|
.afc ( noca ),
|
.vca ( noswa ),
|
.vca ( noswa ),
|
.di0 ( cb2n0 ),
|
.di0 ( cb2n0 ),
|
.di1 ( cb2n1 ),
|
.di1 ( cb2n1 ),
|
.di2 ( cb2n2 ),
|
.di2 ( cb2n2 ),
|
.di3 ( cb2n3 ),
|
.di3 ( cb2n3 ),
|
.dit ( cb2nt ),
|
.dit ( cb2nt ),
|
.doa ( noa ),
|
.doa ( noa ),
|
.credit( noc ),
|
.credit( noc ),
|
.vcr ( noswr ),
|
.vcr ( noswr ),
|
.rst_n ( rst_n )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
// east output buffer
|
// east output buffer
|
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
|
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
|
EOB (
|
EOB (
|
.dia ( cb2ea ),
|
.dia ( cb2ea ),
|
.do0 ( eo0 ),
|
.do0 ( eo0 ),
|
.do1 ( eo1 ),
|
.do1 ( eo1 ),
|
.do2 ( eo2 ),
|
.do2 ( eo2 ),
|
.do3 ( eo3 ),
|
.do3 ( eo3 ),
|
.dot ( eoft ),
|
.dot ( eoft ),
|
.dovc ( eovc ),
|
.dovc ( eovc ),
|
.afc ( eoca ),
|
.afc ( eoca ),
|
.vca ( eoswa ),
|
.vca ( eoswa ),
|
.di0 ( cb2e0 ),
|
.di0 ( cb2e0 ),
|
.di1 ( cb2e1 ),
|
.di1 ( cb2e1 ),
|
.di2 ( cb2e2 ),
|
.di2 ( cb2e2 ),
|
.di3 ( cb2e3 ),
|
.di3 ( cb2e3 ),
|
.dit ( cb2et ),
|
.dit ( cb2et ),
|
.doa ( eoa ),
|
.doa ( eoa ),
|
.credit( eoc ),
|
.credit( eoc ),
|
.vcr ( eoswr ),
|
.vcr ( eoswr ),
|
.rst_n ( rst_n )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
// east output buffer
|
// east output buffer
|
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
|
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
|
LOB (
|
LOB (
|
.dia ( cb2la ),
|
.dia ( cb2la ),
|
.do0 ( lo0 ),
|
.do0 ( lo0 ),
|
.do1 ( lo1 ),
|
.do1 ( lo1 ),
|
.do2 ( lo2 ),
|
.do2 ( lo2 ),
|
.do3 ( lo3 ),
|
.do3 ( lo3 ),
|
.dot ( loft ),
|
.dot ( loft ),
|
.dovc ( lovc ),
|
.dovc ( lovc ),
|
.afc ( loca ),
|
.afc ( loca ),
|
.vca ( loswa ),
|
.vca ( loswa ),
|
.di0 ( cb2l0 ),
|
.di0 ( cb2l0 ),
|
.di1 ( cb2l1 ),
|
.di1 ( cb2l1 ),
|
.di2 ( cb2l2 ),
|
.di2 ( cb2l2 ),
|
.di3 ( cb2l3 ),
|
.di3 ( cb2l3 ),
|
.dit ( cb2lt ),
|
.dit ( cb2lt ),
|
.doa ( loa ),
|
.doa ( loa ),
|
.credit( loc ),
|
.credit( loc ),
|
.vcr ( loswr ),
|
.vcr ( loswr ),
|
.rst_n ( rst_n )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
// VC allocator
|
// VC allocator
|
vcalloc #(.VCN(VCN))
|
vcalloc #(.VCN(VCN))
|
ALLOC (
|
ALLOC (
|
.svcra ( svcra ),
|
.svcra ( svcra ),
|
.wvcra ( wvcra ),
|
.wvcra ( wvcra ),
|
.nvcra ( nvcra ),
|
.nvcra ( nvcra ),
|
.evcra ( evcra ),
|
.evcra ( evcra ),
|
.lvcra ( lvcra ),
|
.lvcra ( lvcra ),
|
.sswa ( siswrt ),
|
.sswa ( siswrt ),
|
.wswa ( wiswrt ),
|
.wswa ( wiswrt ),
|
.nswa ( niswrt ),
|
.nswa ( niswrt ),
|
.eswa ( eiswrt ),
|
.eswa ( eiswrt ),
|
.lswa ( liswrt ),
|
.lswa ( liswrt ),
|
.sosr ( soswr ),
|
.sosr ( soswr ),
|
.wosr ( woswr ),
|
.wosr ( woswr ),
|
.nosr ( noswr ),
|
.nosr ( noswr ),
|
.eosr ( eoswr ),
|
.eosr ( eoswr ),
|
.losr ( loswr ),
|
.losr ( loswr ),
|
.svcr ( svcr ),
|
.svcr ( svcr ),
|
.nvcr ( nvcr ),
|
.nvcr ( nvcr ),
|
.lvcr ( lvcr ),
|
.lvcr ( lvcr ),
|
.wvcr ( wvcr ),
|
.wvcr ( wvcr ),
|
.evcr ( evcr ),
|
.evcr ( evcr ),
|
.sswr ( siswr ),
|
.sswr ( siswr ),
|
.wswr ( wiswr ),
|
.wswr ( wiswr ),
|
.nswr ( niswr ),
|
.nswr ( niswr ),
|
.eswr ( eiswr ),
|
.eswr ( eiswr ),
|
.lswr ( liswr ),
|
.lswr ( liswr ),
|
.sosa ( soswa ),
|
.sosa ( soswa ),
|
.wosa ( woswa ),
|
.wosa ( woswa ),
|
.nosa ( noswa ),
|
.nosa ( noswa ),
|
.eosa ( eoswa ),
|
.eosa ( eoswa ),
|
.losa ( loswa ),
|
.losa ( loswa ),
|
.rst_n ( rst_n )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
// crossbar
|
// crossbar
|
dcb_vc #(.DW(DW), .FT(FT), .VCN(VCN))
|
dcb_vc #(.DW(DW), .FT(FT), .VCN(VCN))
|
CB (
|
CB (
|
.dia ( {l2cba, e2cba, n2cba, w2cba, s2cba} ),
|
.dia ( {l2cba, e2cba, n2cba, w2cba, s2cba} ),
|
.do0 ( {cb2l0, cb2e0, cb2n0, cb2w0, cb2s0} ),
|
.do0 ( {cb2l0, cb2e0, cb2n0, cb2w0, cb2s0} ),
|
.do1 ( {cb2l1, cb2e1, cb2n1, cb2w1, cb2s1} ),
|
.do1 ( {cb2l1, cb2e1, cb2n1, cb2w1, cb2s1} ),
|
.do2 ( {cb2l2, cb2e2, cb2n2, cb2w2, cb2s2} ),
|
.do2 ( {cb2l2, cb2e2, cb2n2, cb2w2, cb2s2} ),
|
.do3 ( {cb2l3, cb2e3, cb2n3, cb2w3, cb2s3} ),
|
.do3 ( {cb2l3, cb2e3, cb2n3, cb2w3, cb2s3} ),
|
.dot ( {cb2lt, cb2et, cb2nt, cb2wt, cb2st} ),
|
.dot ( {cb2lt, cb2et, cb2nt, cb2wt, cb2st} ),
|
.di0 ( {l2cb0, e2cb0, n2cb0, w2cb0, s2cb0} ),
|
.di0 ( {l2cb0, e2cb0, n2cb0, w2cb0, s2cb0} ),
|
.di1 ( {l2cb1, e2cb1, n2cb1, w2cb1, s2cb1} ),
|
.di1 ( {l2cb1, e2cb1, n2cb1, w2cb1, s2cb1} ),
|
.di2 ( {l2cb2, e2cb2, n2cb2, w2cb2, s2cb2} ),
|
.di2 ( {l2cb2, e2cb2, n2cb2, w2cb2, s2cb2} ),
|
.di3 ( {l2cb3, e2cb3, n2cb3, w2cb3, s2cb3} ),
|
.di3 ( {l2cb3, e2cb3, n2cb3, w2cb3, s2cb3} ),
|
.dit ( {l2cbt, e2cbt, n2cbt, w2cbt, s2cbt} ),
|
.dit ( {l2cbt, e2cbt, n2cbt, w2cbt, s2cbt} ),
|
.srtg ( s2cbrtg ),
|
.srtg ( s2cbrtg ),
|
.nrtg ( n2cbrtg ),
|
.nrtg ( n2cbrtg ),
|
.lrtg ( l2cbrtg ),
|
.lrtg ( l2cbrtg ),
|
.wrtg ( w2cbrtg ),
|
.wrtg ( w2cbrtg ),
|
.ertg ( e2cbrtg ),
|
.ertg ( e2cbrtg ),
|
.doa ( {cb2la, cb2ea, cb2na, cb2wa, cb2sa} )
|
.doa ( {cb2la, cb2ea, cb2na, cb2wa, cb2sa} )
|
);
|
);
|
|
|
endmodule // router
|
endmodule // router
|
|
|
|
|
|
|
|
|
|
|
