# Asynchronous SDM NoC
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# Asynchronous SDM NoC
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# (C)2011 Wei Song
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# (C)2011 Wei Song
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# Advanced Processor Technologies Group
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# Advanced Processor Technologies Group
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# Computer Science, the Univ. of Manchester, UK
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# Computer Science, the Univ. of Manchester, UK
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#
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#
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# Authors:
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# Authors:
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# Wei Song wsong83@gmail.com
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# Wei Song wsong83@gmail.com
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#
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#
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# License: LGPL 3.0 or later
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# License: LGPL 3.0 or later
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#
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#
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# Disable the timing loops in asynchronous cells
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# Disable the timing loops in asynchronous cells
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# currently using the Nangate 45nm cell lib.
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# currently using the Nangate 45nm cell lib.
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#
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#
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# History:
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# History:
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# 03/07/2009 Initial version. <wsong83@gmail.com>
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# 03/07/2009 Initial version. <wsong83@gmail.com>
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# 21/05/2011 Change to the Nangate cell library. <wsong83@gmail.com>
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# 27/05/2011 Change to the Nangate cell library. <wsong83@gmail.com>
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set_dont_touch mutex2
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set_dont_touch mutex2
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set_dont_touch delay
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set_dont_touch delay
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# It is not a problem if there is no delay cells in the design.
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# It is not a problem if there is no delay cells in the design.
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uniquify -force
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uniquify -force
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# C-gates on control path
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# C-gates on control path
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foreach_in_collection celln [get_references -hierarchical c2_*] {
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foreach_in_collection celln [get_references -hierarchical c2_*] {
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set_disable_timing [get_object_name $celln]/U2 -from B -to Z
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set_disable_timing [get_object_name $celln]/U2 -from B -to Z
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set_disable_timing [get_object_name $celln]/U3 -from B -to Z
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set_disable_timing [get_object_name $celln]/U3 -from B -to Z
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}
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}
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# C-gates on data path, feedback and data input are disabled from timing analysis
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# C-gates on data path, feedback and data input are disabled from timing analysis
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foreach_in_collection celln [get_references -hierarchical dc2_*] {
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foreach_in_collection celln [get_references -hierarchical dc2_*] {
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set_disable_timing [get_object_name $celln]/U1 -from B -to Z
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set_disable_timing [get_object_name $celln]/U1 -from B -to Z
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set_disable_timing [get_object_name $celln]/U2 -from A -to Z
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set_disable_timing [get_object_name $celln]/U2 -from A -to Z
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set_disable_timing [get_object_name $celln]/U2 -from B -to Z
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set_disable_timing [get_object_name $celln]/U2 -from B -to Z
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set_disable_timing [get_object_name $celln]/U3 -from B -to Z
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set_disable_timing [get_object_name $celln]/U3 -from B -to Z
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}
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}
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# c2n gates
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# c2n gates
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foreach_in_collection celln [get_references -hierarchical c2n_*] {
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foreach_in_collection celln [get_references -hierarchical c2n_*] {
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set_disable_timing [get_object_name $celln]/U1 -from B -to Z
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set_disable_timing [get_object_name $celln]/U1 -from B -to Z
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}
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}
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# It is not a problem if there is no c2n cells in the design.
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# It is not a problem if there is no c2n cells in the design.
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# c2p gates
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# c2p gates
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foreach_in_collection celln [get_references -hierarchical c2p_*] {
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foreach_in_collection celln [get_references -hierarchical c2p_*] {
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set_disable_timing [get_object_name $celln]/U1 -from B -to Z
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set_disable_timing [get_object_name $celln]/U1 -from B -to Z
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}
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}
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# It is not a problem if there is no c2p cells in the design.
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# It is not a problem if there is no c2p cells in the design.
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# mutex gates
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# mutex gates
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foreach_in_collection celln [get_references -hierarchical mutex2_*] {
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foreach_in_collection celln [get_references -hierarchical mutex2_*] {
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set_disable_timing [get_object_name $celln]/U1 -from A2 -to ZN
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set_disable_timing [get_object_name $celln]/U1 -from A2 -to ZN
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set_disable_timing [get_object_name $celln]/U4 -from A2 -to ZN
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set_disable_timing [get_object_name $celln]/U4 -from A2 -to ZN
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set_dont_touch [get_object_name $celln]/U2
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set_dont_touch [get_object_name $celln]/U2
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set_dont_touch [get_object_name $celln]/U3
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set_dont_touch [get_object_name $celln]/U3
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}
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}
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# c2p1 gates
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# c2p1 gates
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foreach_in_collection celln [get_references -hierarchical c2p1_*] {
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foreach_in_collection celln [get_references -hierarchical c2p1_*] {
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set_disable_timing [get_object_name $celln]/U2 -from B -to Z
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set_disable_timing [get_object_name $celln]/U2 -from B -to Z
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set_disable_timing [get_object_name $celln]/U3 -from B -to Z
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set_disable_timing [get_object_name $celln]/U3 -from B -to Z
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}
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}
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# It is not a problem if MRMA is not used in the design.
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# It is not a problem if MRMA is not used in the design.
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# tarb
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# tarb
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foreach_in_collection celln [get_references -hierarchical tarb_*] {
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foreach_in_collection celln [get_references -hierarchical tarb_*] {
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set_disable_timing [get_object_name $celln]/U2 -from A -to Z
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set_disable_timing [get_object_name $celln]/U2 -from A -to Z
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set_disable_timing [get_object_name $celln]/U3 -from A -to Z
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set_disable_timing [get_object_name $celln]/U3 -from A -to Z
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}
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}
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# It is not a problem if tree arbiter is not used in the design.
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# It is not a problem if tree arbiter is not used in the design.
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# cr_blk
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# cr_blk
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foreach_in_collection celln [get_references -hierarchical cr_blk_*] {
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foreach_in_collection celln [get_references -hierarchical cr_blk_*] {
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set_disable_timing [get_object_name $celln]/XG/U1 -from C -to Z
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set_disable_timing [get_object_name $celln]/XG/U1 -from C -to Z
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}
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}
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# It is not a problem if MRMA is not used in the design.
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# It is not a problem if MRMA is not used in the design.
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# mrma multi-resource match arbiter
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foreach_in_collection celln [get_references -hierarchical mrma_*] {
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set_disable_timing [get_object_name $celln]/*.AND_*G* -from B -to Z
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set_disable_timing [get_object_name $celln]/*.AND_RG* -from A -to Z
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}
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# It is not a problem if MRMA is not used in the design.
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# dcb data crossbar
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# dcb data crossbar
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foreach_in_collection celln [get_references -hierarchical dcb_*] {
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foreach_in_collection celln [get_references -hierarchical dcb_*] {
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set_disable_timing [get_object_name $celln]/*.A* -from B -to Z
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set_disable_timing [get_object_name $celln]/*.A* -from B -to Z
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}
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}
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# dcb data crossbar
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# dcb data crossbar
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foreach_in_collection celln [get_references -hierarchical rcb_*] {
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foreach_in_collection celln [get_references -hierarchical rcb_*] {
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set_disable_timing [get_object_name $celln]/*.A* -from B -to Z
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set_disable_timing [get_object_name $celln]/*.A* -from B -to Z
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}
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}
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#It is not a problem if there is no rcb modules in the design.
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#It is not a problem if there is no rcb modules in the design.
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No newline at end of file
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No newline at end of file
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# mnmr m-n match allocator
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foreach_in_collection celln [get_references -hierarchical mnma_*] {
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set_disable_timing [get_object_name $celln]/*.AND_OPRen* -from B -to Z
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}
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#It is not a problem if MNMA is not used in the design.
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No newline at end of file
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No newline at end of file
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