/*
|
/*
|
Asynchronous SDM NoC
|
Asynchronous SDM NoC
|
(C)2011 Wei Song
|
(C)2011 Wei Song
|
Advanced Processor Technologies Group
|
Advanced Processor Technologies Group
|
Computer Science, the Univ. of Manchester, UK
|
Computer Science, the Univ. of Manchester, UK
|
|
|
Authors:
|
Authors:
|
Wei Song wsong83@gmail.com
|
Wei Song wsong83@gmail.com
|
|
|
License: LGPL 3.0 or later
|
License: LGPL 3.0 or later
|
|
|
Multi-resource match arbiter
|
Multi-resource match arbiter
|
*** SystemVerilog is used ***
|
*** SystemVerilog is used ***
|
|
|
References
|
References
|
Stanislavs Golubcovs, Delong Shang, Fei Xia, Andrey Mokhov and Alex Yakovlev, Multi-resource arbiter decomposition, Tech report NCL-EECE-MSD-TR-2009-143, Microelectronic System Design Group, School of EECE, Newcastle University, 2009.
|
Stanislavs Golubcovs, Delong Shang, Fei Xia, Andrey Mokhov and Alex Yakovlev, Multi-resource arbiter decomposition, Tech report NCL-EECE-MSD-TR-2009-143, Microelectronic System Design Group, School of EECE, Newcastle University, 2009.
|
Stanislavs Golubcovs, Delong Shang, Fei Xia, Andrey Mokhov and Alex Yakovlev, Modular approach to multi-resource arbiter design, IEEE Symposium on Asynchronous Circuits and Systems, 2009.
|
Stanislavs Golubcovs, Delong Shang, Fei Xia, Andrey Mokhov and Alex Yakovlev, Modular approach to multi-resource arbiter design, IEEE Symposium on Asynchronous Circuits and Systems, 2009.
|
|
|
History:
|
History:
|
05/09/2009 Initial version. <wsong83@gmail.com>
|
05/09/2009 Initial version. <wsong83@gmail.com>
|
05/11/2009 Speed up the arbiter. <wsong83@gmail.com>
|
05/11/2009 Speed up the arbiter. <wsong83@gmail.com>
|
24/05/2011 Clean up for opensource. <wsong83@gmail.com>
|
27/05/2011 Clean up for opensource. <wsong83@gmail.com>
|
|
|
*/
|
*/
|
|
|
module mrma (/*AUTOARG*/
|
module mrma (/*AUTOARG*/
|
// Outputs
|
// Outputs
|
ca, ra, cfg,
|
ca, ra, cfg,
|
// Inputs
|
// Inputs
|
c, r, rst_n
|
c, r, rst_n
|
);
|
);
|
|
|
// parameters
|
// parameters
|
parameter N = 2; // the number of requests/clients
|
parameter N = 2; // the number of requests/clients
|
parameter M = 2; // the number of resources
|
parameter M = 2; // the number of resources
|
|
|
input [N-1:0] c; // requests/clients
|
input [N-1:0] c; // requests/clients
|
output [N-1:0] ca; // requests ack
|
output [N-1:0] ca; // requests ack
|
|
|
input [M-1:0] r; // resources
|
input [M-1:0] r; // resources
|
output [M-1:0] ra; // resource ack
|
output [M-1:0] ra; // resource ack
|
|
|
output [M-1:0][N-1:0] cfg; // the generated configuration
|
output [M-1:0][N-1:0] cfg; // the generated configuration
|
wire [N-1:0][M-1:0] scfg;
|
wire [N-1:0][M-1:0] scfg;
|
|
|
wire [M-1:0][N-1:0] hs; // match results
|
wire [M-1:0][N-1:0] hs; // match results
|
wire [M-1:0][N-1:0] blk; // blockage
|
wire [M-1:0][N-1:0] blk; // blockage
|
wire [N-1:0][M-1:0] sblk; // shuffled blockage
|
wire [N-1:0][M-1:0] sblk; // shuffled blockage
|
wire [M-1:0] rbi; // resource blockage
|
wire [M-1:0] rbi; // resource blockage
|
wire [N-1:0] cbi; // client blockage
|
wire [N-1:0] cbi; // client blockage
|
wire [N-1:0] cg, cm; // client requests
|
wire [N-1:0] cg, cm; // client requests
|
wire [M-1:0] rg, rm; // resource requests
|
wire [M-1:0] rg, rm; // resource requests
|
|
|
input rst_n; // active low reset
|
input rst_n; // active low reset
|
|
|
// generate variables
|
// generate variables
|
genvar i, j;
|
genvar i, j;
|
|
|
|
|
// input arbiters
|
// input arbiters
|
tree_arb #(N) CIArb (
|
tree_arb #(N) CIArb (
|
.req ( cm ),
|
.req ( cm ),
|
.gnt ( cg )
|
.gnt ( cg )
|
);
|
);
|
|
|
tree_arb #(M) RIArb (
|
tree_arb #(M) RIArb (
|
.req ( rm ),
|
.req ( rm ),
|
.gnt ( rg )
|
.gnt ( rg )
|
);
|
);
|
|
|
generate
|
generate
|
// tile matrix
|
// tile matrix
|
for (i=0; i<M; i++) begin: Row
|
for (i=0; i<M; i++) begin: Row
|
for(j=0; j<N; j++) begin: Clm
|
for(j=0; j<N; j++) begin: Clm
|
cr_blk E (
|
cr_blk E (
|
.bo ( blk[i][j] ),
|
.bo ( blk[i][j] ),
|
.hs ( hs[i][j] ),
|
.hs ( hs[i][j] ),
|
.cbi ( cbi[j] ),
|
.cbi ( cbi[j] ),
|
.rbi ( rbi[i] ),
|
.rbi ( rbi[i] ),
|
.rg ( rg[i] ),
|
.rg ( rg[i] ),
|
.cg ( cg[j] )
|
.cg ( cg[j] )
|
);
|
);
|
|
|
// shuffle the blockage
|
// shuffle the blockage
|
assign sblk[j][i] = blk[i][j];
|
assign sblk[j][i] = blk[i][j];
|
|
|
// shuffle the configuration
|
// shuffle the configuration
|
assign scfg[j][i] = cfg[i][j];
|
assign scfg[j][i] = cfg[i][j];
|
|
|
// store the match results
|
// store the match results
|
c2p C (.q(cfg[i][j]), .a0(c[j]), .a1(hs[i][j]));
|
c2p C (.q(cfg[i][j]), .a(c[j]), .b(hs[i][j]));
|
|
|
end // block: Clm
|
end // block: Clm
|
end // block: Row
|
end // block: Row
|
|
|
// combine the row blockage and generate input requests
|
// combine the row blockage and generate input requests
|
for(i=0; i<M; i++) begin: RB
|
for(i=0; i<M; i++) begin: RB
|
assign rbi[i] = (|blk[i]) & rst_n;
|
assign rbi[i] = (|blk[i]) & rst_n;
|
and AND_RG (rm[i], r[i], ~ra[i], rst_n);
|
and AND_RG (rm[i], r[i], ~ra[i], rst_n);
|
assign ra[i] = |cfg[i];
|
assign ra[i] = |cfg[i];
|
end
|
end
|
|
|
// combine the column blockage and generate input requests
|
// combine the column blockage and generate input requests
|
for(j=0; j<N; j++) begin: CB
|
for(j=0; j<N; j++) begin: CB
|
assign cbi[j] = (|sblk[j]) & rst_n;
|
assign cbi[j] = (|sblk[j]) & rst_n;
|
and AND_CG (cm[j], c[j], ~ca[j], rst_n);
|
and AND_CG (cm[j], c[j], ~ca[j], rst_n);
|
assign ca[j] = |scfg[j];
|
assign ca[j] = |scfg[j];
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
endmodule // mrma
|
endmodule // mrma
|
|
|
|
|
