/*
|
/*
|
Asynchronous SDM NoC
|
Asynchronous SDM NoC
|
(C)2011 Wei Song
|
(C)2011 Wei Song
|
Advanced Processor Technologies Group
|
Advanced Processor Technologies Group
|
Computer Science, the Univ. of Manchester, UK
|
Computer Science, the Univ. of Manchester, UK
|
|
|
Authors:
|
Authors:
|
Wei Song wsong83@gmail.com
|
Wei Song wsong83@gmail.com
|
|
|
License: LGPL 3.0 or later
|
License: LGPL 3.0 or later
|
|
|
Request crossbar for wormhole and SDM routers.
|
Request crossbar for wormhole and SDM routers.
|
*** SystemVerilog is used ***
|
*** SystemVerilog is used ***
|
|
|
History:
|
History:
|
10/12/2009 Initial version. <wsong83@gmail.com>
|
10/12/2009 Initial version. <wsong83@gmail.com>
|
23/05/2011 Use SystemVerilog for wire declaration. <wsong83@gmail.com>
|
23/05/2011 Use SystemVerilog for wire declaration. <wsong83@gmail.com>
|
23/05/2011 Clean up for opensource. <wsong83@gmail.com>
|
27/05/2011 Clean up for opensource. <wsong83@gmail.com>
|
|
|
*/
|
*/
|
|
|
module rcb (/*AUTOARG*/
|
module rcb (/*AUTOARG*/
|
// Outputs
|
// Outputs
|
ira, oreq,
|
ira, oreq,
|
// Inputs
|
// Inputs
|
ireq, ora, cfg
|
ireq, ora, cfg
|
) ;
|
) ;
|
// parameters
|
// parameters
|
parameter NN = 1; // number of input ports
|
parameter NN = 1; // number of input ports
|
parameter MN = 1; // number of output ports
|
parameter MN = 1; // number of output ports
|
parameter DW = 1; // datawidth a port
|
parameter DW = 1; // datawidth a port
|
|
|
input [NN-1:0][DW-1:0] ireq; // input requests
|
input [NN-1:0][DW-1:0] ireq; // input requests
|
output [NN-1:0] ira; // ack for input requests
|
output [NN-1:0] ira; // ack for input requests
|
output [MN-1:0][DW-1:0] oreq; // output requests
|
output [MN-1:0][DW-1:0] oreq; // output requests
|
input [DW-1:0] ora; // ack for output requests
|
input [MN-1:0] ora; // ack for output requests
|
input [MN-1:0][NN-1:0] cfg; // the crossbar configuration
|
input [MN-1:0][NN-1:0] cfg; // the crossbar configuration
|
|
|
wire [MN-1:0][DW-1:0][NN-1-1:0] m; // the internal wires for requests
|
wire [MN-1:0][DW-1:0][NN-1:0] m; // the internal wires for requests
|
wire [NN-1:0][MN-1:0] ma; // the internal wires for acks
|
wire [NN-1:0][MN-1:0] ma; // the internal wires for acks
|
|
|
// generate variable
|
// generate variable
|
genvar i, j, k;
|
genvar i, j, k;
|
|
|
// request matrix
|
// request matrix
|
generate
|
generate
|
for (i=0; i<MN; i++) begin: EN
|
for (i=0; i<MN; i++) begin: EN
|
for (j=0; j<DW; j=j+1) begin: SC
|
for (j=0; j<DW; j++) begin: SC
|
for (k=0; k<NN; k=k+1) begin: IP
|
for (k=0; k<NN; k++) begin: IP
|
and AC (m[i][j][k], ireq[k][j], cfg[i][k]);
|
and AC (m[i][j][k], ireq[k][j], cfg[i][k]);
|
end
|
end
|
|
|
// the OR gates
|
// the OR gates
|
assign oreq[i][j] = |m[i][j];
|
assign oreq[i][j] = |m[i][j];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
// ack matrix
|
// ack matrix
|
generate
|
generate
|
for (k=0; k<NN; k=k+1) begin: ENA
|
for (k=0; k<NN; k++) begin: ENA
|
for (i=0; i<MN; i=i+1) begin: OP
|
for (i=0; i<MN; i++) begin: OP
|
and AC (ma[k][i], ora[i], cfg[i][k]);
|
and AC (ma[k][i], ora[i], cfg[i][k]);
|
end
|
end
|
|
|
// the OR gates
|
// the OR gates
|
assign ira[k] = |ma[k];
|
assign ira[k] = |ma[k];
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
endmodule // rcb
|
endmodule // rcb
|
|
|
|
|
|
|
