/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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The routing calculation unit in every input buffer.
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The routing calculation unit in every input buffer.
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p0 -> L -> p1 -> RTC -> p2 -> L -> p3 -> DEMUX -> p[0] -> L -> p[1] -> L -> p[2] -> L -> p[3] -> L -> p[4]
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p0 -> L -> p1 -> RTC -> p2 -> L -> p3 -> DEMUX -> p[0] -> L -> p[1] -> L -> p[2] -> L -> p[3] -> L -> p[4]
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History:
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History:
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02/04/2010 Initial version. <wsong83@gmail.com>
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02/04/2010 Initial version. <wsong83@gmail.com>
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02/06/2011 Clean up for opensource. <wsong83@gmail.com>
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02/06/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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module rtu (/*AUTOARG*/
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module rtu (/*AUTOARG*/
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// Outputs
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// Outputs
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dia, dort,
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dia, dort,
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// Inputs
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// Inputs
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rstn, di0, di1, di2, di3, dit, divc, addrx, addry, doa
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rstn, di0, di1, di2, di3, dit, divc, addrx, addry, doa
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);
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);
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parameter VCN = 2;
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parameter VCN = 2;
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parameter DIR = 0;
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parameter DIR = 0;
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parameter SN = 4;
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parameter SN = 4;
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parameter PD = 2;
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parameter PD = 2;
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input rstn;
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input rstn;
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input [3:0] di0, di1, di2, di3;
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input [3:0] di0, di1, di2, di3;
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input [2:0] dit;
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input [2:0] dit;
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input [VCN-1:0] divc;
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input [VCN-1:0] divc;
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output dia;
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output dia;
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input [7:0] addrx, addry;
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input [7:0] addrx, addry;
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output [VCN-1:0][SN-1:0] dort;
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output [VCN-1:0][SN-1:0] dort;
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input [VCN-1:0] doa;
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input [VCN-1:0] doa;
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//------------------------------------------
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//------------------------------------------
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wire p0an, p0ap, p0den, p0ad, p0avc;
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wire p0an, p0ap, p0den, p0ad, p0avc;
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wire [3:0] p1d0, p1d1, p1d2, p1d3;
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wire [3:0] p1d0, p1d1, p1d2, p1d3;
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wire [VCN-1:0] p1vc;
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wire [VCN-1:0] p1vc;
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wire p1a, p1ad, p1avc, p1an;
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wire p1a, p1ad, p1avc, p1an;
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wire [SN-1:0] p2d;
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wire [SN-1:0] p2d;
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wire [VCN-1:0] p2vc;
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wire [VCN-1:0] p2vc;
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wire p2a, p2ad, p2avc, p2an;
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wire p2a, p2ad, p2avc, p2an;
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wire [SN-1:0] p3d;
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wire [SN-1:0] p3d;
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wire [VCN-1:0] p3vc;
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wire [VCN-1:0] p3vc;
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wire p3a, p3an;
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wire p3a, p3an;
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wire [PD*2:0][VCN-1:0][SN-1:0] pd;
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wire [PD*2:0][VCN-1:0][SN-1:0] pd;
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wire [PD*2:0][VCN-1:0] pda, pdan;
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wire [PD*2:0][VCN-1:0] pda, pdan;
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wire [2:0] x_cmp [1:0];
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wire [2:0] x_cmp [1:0];
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wire [2:0] y_cmp [1:0];
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wire [2:0] y_cmp [1:0];
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wire [5:0] dec;
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wire [5:0] dec;
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wire ds, dw, dn, de, dl;
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wire ds, dw, dn, de, dl;
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genvar gvc, gbd, i;
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genvar gvc, gbd, i;
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//------------------------------------------
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//------------------------------------------
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// p0 -> L -> p1
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// p0 -> L -> p1
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c2 CP0DE ( .a0(dit[0]), .a1(p1an), .q(p0den));
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c2 CP0DE ( .a0(dit[0]), .a1(p1an), .q(p0den));
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c2 CP0A ( .a0(p0ad), .a1(p0avc), .q(p0ap));
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c2 CP0A ( .a0(p0ad), .a1(p0avc), .q(p0ap));
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assign p0an = |dit[2:1];
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assign p0an = |dit[2:1];
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assign dia = p0an | p0ap;
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assign dia = p0an | p0ap;
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pipe4 #(.DW(8))
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pipe4 #(.DW(8))
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L0D (
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L0D (
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.dia ( p0ad ),
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.ia ( p0ad ),
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.do0 ( p1d0 ),
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.o0 ( p1d0 ),
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.do1 ( p1d1 ),
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.o1 ( p1d1 ),
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.do2 ( p1d2 ),
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.o2 ( p1d2 ),
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.do3 ( p1d3 ),
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.o3 ( p1d3 ),
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.di0 ( di0 ),
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.i0 ( di0 ),
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.di1 ( di1 ),
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.i1 ( di1 ),
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.di2 ( di2 ),
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.i2 ( di2 ),
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.di3 ( di3 ),
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.i3 ( di3 ),
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.doa ( p0den )
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.oa ( p0den )
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);
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);
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pipen #(.DW(VCN))
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pipen #(.DW(VCN))
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L0V (
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L0V (
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.d_in ( divc ),
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.d_in ( divc ),
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.d_in_a ( p0avc ),
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.d_in_a ( p0avc ),
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.d_out ( p1vc ),
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.d_out ( p1vc ),
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.d_out_a ( p0den )
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.d_out_a ( p0den )
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);
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);
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// p1 -> RTC -> p2
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// p1 -> RTC -> p2
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comp4 X0 ( .a({p1d3[0], p1d2[0], p1d1[0], p1d0[0]}), .b(addrx[3:0]), .q(x_cmp[0]));
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comp4 X0 ( .a({p1d3[0], p1d2[0], p1d1[0], p1d0[0]}), .b(addrx[3:0]), .q(x_cmp[0]));
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comp4 X1 ( .a({p1d3[1], p1d2[1], p1d1[1], p1d0[1]}), .b(addrx[7:4]), .q(x_cmp[1]));
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comp4 X1 ( .a({p1d3[1], p1d2[1], p1d1[1], p1d0[1]}), .b(addrx[7:4]), .q(x_cmp[1]));
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comp4 Y0 ( .a({p1d3[2], p1d2[2], p1d1[2], p1d0[2]}), .b(addry[3:0]), .q(y_cmp[0]));
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comp4 Y0 ( .a({p1d3[2], p1d2[2], p1d1[2], p1d0[2]}), .b(addry[3:0]), .q(y_cmp[0]));
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comp4 Y1 ( .a({p1d3[3], p1d2[3], p1d1[3], p1d0[3]}), .b(addry[7:4]), .q(y_cmp[1]));
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comp4 Y1 ( .a({p1d3[3], p1d2[3], p1d1[3], p1d0[3]}), .b(addry[7:4]), .q(y_cmp[1]));
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assign dec[0] = x_cmp[1][0] | (x_cmp[1][2]&x_cmp[0][0]); // frame x > addr x
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assign dec[0] = x_cmp[1][0] | (x_cmp[1][2]&x_cmp[0][0]); // frame x > addr x
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assign dec[1] = x_cmp[1][1] | (x_cmp[1][2]&x_cmp[0][1]); // frame x < addr x
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assign dec[1] = x_cmp[1][1] | (x_cmp[1][2]&x_cmp[0][1]); // frame x < addr x
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assign dec[2] = x_cmp[1][2] & x_cmp[0][2]; // frame x = addr x
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assign dec[2] = x_cmp[1][2] & x_cmp[0][2]; // frame x = addr x
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assign dec[3] = y_cmp[1][0] | (y_cmp[1][2]&y_cmp[0][0]); // frame y > addr y
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assign dec[3] = y_cmp[1][0] | (y_cmp[1][2]&y_cmp[0][0]); // frame y > addr y
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assign dec[4] = y_cmp[1][1] | (y_cmp[1][2]&y_cmp[0][1]); // frame y < addr y
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assign dec[4] = y_cmp[1][1] | (y_cmp[1][2]&y_cmp[0][1]); // frame y < addr y
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assign dec[5] = y_cmp[1][2] & y_cmp[0][2]; // frame y = addr y
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assign dec[5] = y_cmp[1][2] & y_cmp[0][2]; // frame y = addr y
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assign ds = dec[0];
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assign ds = dec[0];
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assign dw = dec[2]&dec[4];
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assign dw = dec[2]&dec[4];
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assign dn = dec[1];
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assign dn = dec[1];
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assign de = dec[2]&dec[3];
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assign de = dec[2]&dec[3];
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assign dl = dec[2]&dec[5];
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assign dl = dec[2]&dec[5];
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assign p2d =
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assign p2d =
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DIR == 0 ? {dl, de, dn, dw} : // south port
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DIR == 0 ? {dl, de, dn, dw} : // south port
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DIR == 1 ? {dl, de} : // west port
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DIR == 1 ? {dl, de} : // west port
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DIR == 2 ? {dl, de, dw, ds} : // north port
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DIR == 2 ? {dl, de, dw, ds} : // north port
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DIR == 3 ? {dl, dw} : // east port
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DIR == 3 ? {dl, dw} : // east port
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{de, dn, dw, ds} ; // local port
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{de, dn, dw, ds} ; // local port
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assign p2vc = p1vc;
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assign p2vc = p1vc;
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assign p1an = p2an;
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assign p1an = p2an;
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// p2 -> L -> p3
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// p2 -> L -> p3
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c2 CP2A ( .a0(p2ad), .a1(p2avc), .q(p2a));
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c2 CP2A ( .a0(p2ad), .a1(p2avc), .q(p2a));
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assign p2an = (~p2a) & rstn;
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assign p2an = (~p2a) & rstn;
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pipen #(.DW(SN))
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pipen #(.DW(SN))
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L2R (
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L2R (
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.d_in ( p2d ),
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.d_in ( p2d ),
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.d_in_a ( p2ad ),
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.d_in_a ( p2ad ),
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.d_out ( p3d ),
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.d_out ( p3d ),
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.d_out_a ( p3an )
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.d_out_a ( p3an )
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);
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);
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pipen #(.DW(VCN))
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pipen #(.DW(VCN))
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L2V (
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L2V (
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.d_in ( p2vc ),
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.d_in ( p2vc ),
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.d_in_a ( p2avc ),
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.d_in_a ( p2avc ),
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.d_out ( p3vc ),
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.d_out ( p3vc ),
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.d_out_a ( p3an )
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.d_out_a ( p3an )
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);
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);
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// p3 -> DEMUX -> pd[0]
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// p3 -> DEMUX -> pd[0]
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ddmux #(.DW(SN), .VCN(VCN))
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ddmux #(.DW(SN), .VCN(VCN))
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RTDM (
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RTDM (
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.d_in_a ( p3a ),
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.d_in_a ( p3a ),
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.d_out ( pd[0] ),
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.d_out ( pd[0] ),
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.d_in ( p3d ),
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.d_in ( p3d ),
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.d_sel ( p3vc ),
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.d_sel ( p3vc ),
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.d_out_a ( pda[0])
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.d_out_a ( pda[0])
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);
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);
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assign p3an = (~p3a) & rstn;
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assign p3an = (~p3a) & rstn;
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// pd pipeline
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// pd pipeline
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generate
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generate
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for(gbd=0; gbd<PD*2; gbd++) begin:RT
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for(gbd=0; gbd<PD*2; gbd++) begin:RT
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for(gvc=0; gvc<VCN; gvc++) begin:V
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for(gvc=0; gvc<VCN; gvc++) begin:V
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pipen #(.DW(SN))
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pipen #(.DW(SN))
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P (
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P (
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.d_in ( pd[gbd][gvc] ),
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.d_in ( pd[gbd][gvc] ),
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.d_in_a ( pda[gbd][gvc] ),
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.d_in_a ( pda[gbd][gvc] ),
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.d_out ( pd[gbd+1][gvc] ),
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.d_out ( pd[gbd+1][gvc] ),
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.d_out_a ( pdan[gbd+1][gvc] )
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.d_out_a ( pdan[gbd+1][gvc] )
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);
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);
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assign pdan[gbd+1][gvc] = (~pda[gbd+1][gvc])&rstn;
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assign pdan[gbd+1][gvc] = (~pda[gbd+1][gvc])&rstn;
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end
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end
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end // block: RT
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end // block: RT
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endgenerate
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endgenerate
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// output
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// output
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generate
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generate
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for(gvc=0; gvc<VCN; gvc++) begin:OV
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for(gvc=0; gvc<VCN; gvc++) begin:OV
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assign dort[gvc] = pd[PD*2][gvc];
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assign dort[gvc] = pd[PD*2][gvc];
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assign pda[PD*2][gvc] = doa[gvc];
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assign pda[PD*2][gvc] = doa[gvc];
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end
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end
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endgenerate
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endgenerate
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endmodule // rtu
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endmodule // rtu
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