/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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Wormhole/SDM router top level module
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Wormhole/SDM router top level module
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*** SystemVerilog is used ***
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*** SystemVerilog is used ***
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History:
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History:
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28/05/2009 Initial version. <wsong83@gmail.com>
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28/05/2009 Initial version. <wsong83@gmail.com>
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23/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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23/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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22/10/2010 Parameterize the number of pipelines in output buffers. <wsong83@gmail.com>
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22/10/2010 Parameterize the number of pipelines in output buffers. <wsong83@gmail.com>
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25/05/2011 Clean up for opensource. <wsong83@gmail.com>
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25/05/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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module router(/*AUTOARG*/
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module router(/*AUTOARG*/
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// Outputs
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// Outputs
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so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
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so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
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eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
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eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
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wia, nia, eia, lia,
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wia, nia, eia, lia,
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// Inputs
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// Inputs
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si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
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si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
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ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
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ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
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woa, noa, eoa, loa, addrx, addry, rst_n
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woa, noa, eoa, loa, addrx, addry, rst_n
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);
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);
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parameter VCN = 1; // number of virtual circuits in each direction. When VCN == 1, it is a wormhole router
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parameter VCN = 1; // number of virtual circuits in each direction. When VCN == 1, it is a wormhole router
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parameter DW = 32; // the datawidth of a single virtual circuit, the total data width of the router is DW*VCN
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parameter DW = 32; // the datawidth of a single virtual circuit, the total data width of the router is DW*VCN
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parameter IPD = 1; // the number of half-buffer stages in input buffers
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parameter IPD = 1; // the number of half-buffer stages in input buffers
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parameter OPD = 2; // the number of half-buffer stages in output buffers
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parameter OPD = 2; // the number of half-buffer stages in output buffers
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parameter SCN = DW/2; // the number of 1-of-4 sub-channel in each virtual circuit
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parameter SCN = DW/2; // the number of 1-of-4 sub-channel in each virtual circuit
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input [VCN-1:0][SCN-1:0] si0, si1, si2, si3; // south input [0], X+1
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input [VCN-1:0][SCN-1:0] si0, si1, si2, si3; // south input [0], X+1
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input [VCN-1:0][SCN-1:0] wi0, wi1, wi2, wi3; // west input [1], Y-1
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input [VCN-1:0][SCN-1:0] wi0, wi1, wi2, wi3; // west input [1], Y-1
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input [VCN-1:0][SCN-1:0] ni0, ni1, ni2, ni3; // north input [2], X-1
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input [VCN-1:0][SCN-1:0] ni0, ni1, ni2, ni3; // north input [2], X-1
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input [VCN-1:0][SCN-1:0] ei0, ei1, ei2, ei3; // east input [3], Y+1
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input [VCN-1:0][SCN-1:0] ei0, ei1, ei2, ei3; // east input [3], Y+1
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input [VCN-1:0][SCN-1:0] li0, li1, li2, li3; // local input
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input [VCN-1:0][SCN-1:0] li0, li1, li2, li3; // local input
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output [VCN-1:0][SCN-1:0] so0, so1, so2, so3; // south output
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output [VCN-1:0][SCN-1:0] so0, so1, so2, so3; // south output
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output [VCN-1:0][SCN-1:0] wo0, wo1, wo2, wo3; // west output
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output [VCN-1:0][SCN-1:0] wo0, wo1, wo2, wo3; // west output
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output [VCN-1:0][SCN-1:0] no0, no1, no2, no3; // north output
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output [VCN-1:0][SCN-1:0] no0, no1, no2, no3; // north output
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output [VCN-1:0][SCN-1:0] eo0, eo1, eo2, eo3; // east output
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output [VCN-1:0][SCN-1:0] eo0, eo1, eo2, eo3; // east output
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output [VCN-1:0][SCN-1:0] lo0, lo1, lo2, lo3; // local output
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output [VCN-1:0][SCN-1:0] lo0, lo1, lo2, lo3; // local output
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// eof bits and ack lines
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// eof bits and ack lines
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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input [VCN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4;
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input [VCN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4;
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output [VCN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;
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output [VCN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;
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output [VCN-1:0][SCN-1:0] sia, wia, nia, eia, lia;
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output [VCN-1:0][SCN-1:0] sia, wia, nia, eia, lia;
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input [VCN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;
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input [VCN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;
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`else
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`else
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input [VCN-1:0] si4, wi4, ni4, ei4, li4;
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input [VCN-1:0] si4, wi4, ni4, ei4, li4;
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output [VCN-1:0] so4, wo4, no4, eo4, lo4;
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output [VCN-1:0] so4, wo4, no4, eo4, lo4;
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output [VCN-1:0] sia, wia, nia, eia, lia;
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output [VCN-1:0] sia, wia, nia, eia, lia;
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input [VCN-1:0] soa, woa, noa, eoa, loa;
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input [VCN-1:0] soa, woa, noa, eoa, loa;
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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input [7:0] addrx, addry; // the local address of the router, coded in 1-of-4 coding
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input [7:0] addrx, addry; // the local address of the router, coded in 1-of-4 coding
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input rst_n; // active low reset signal
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input rst_n; // active low reset signal
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// internal wires, input buffers to switches (crossbar): [dir]2[cb][1-of-4 index]
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// internal wires, input buffers to switches (crossbar): [dir]2[cb][1-of-4 index]
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wire [VCN-1:0][SCN-1:0] s2c0, s2c1, s2c2, s2c3; // south input to switch data
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wire [VCN-1:0][SCN-1:0] s2c0, s2c1, s2c2, s2c3; // south input to switch data
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wire [VCN-1:0][SCN-1:0] w2c0, w2c1, w2c2, w2c3;
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wire [VCN-1:0][SCN-1:0] w2c0, w2c1, w2c2, w2c3;
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wire [VCN-1:0][SCN-1:0] n2c0, n2c1, n2c2, n2c3;
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wire [VCN-1:0][SCN-1:0] n2c0, n2c1, n2c2, n2c3;
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wire [VCN-1:0][SCN-1:0] e2c0, e2c1, e2c2, e2c3;
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wire [VCN-1:0][SCN-1:0] e2c0, e2c1, e2c2, e2c3;
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wire [VCN-1:0][SCN-1:0] l2c0, l2c1, l2c2, l2c3;
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wire [VCN-1:0][SCN-1:0] l2c0, l2c1, l2c2, l2c3;
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// internal wires, switches (crossbar) to output buffers: [cb]2[dir][1-of-4 index]
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// internal wires, switches (crossbar) to output buffers: [cb]2[dir][1-of-4 index]
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wire [VCN-1:0][SCN-1:0] c2s0, c2s1, c2s2, c2s3;
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wire [VCN-1:0][SCN-1:0] c2s0, c2s1, c2s2, c2s3;
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wire [VCN-1:0][SCN-1:0] c2w0, c2w1, c2w2, c2w3;
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wire [VCN-1:0][SCN-1:0] c2w0, c2w1, c2w2, c2w3;
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wire [VCN-1:0][SCN-1:0] c2n0, c2n1, c2n2, c2n3; // switch to north output
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wire [VCN-1:0][SCN-1:0] c2n0, c2n1, c2n2, c2n3; // switch to north output
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wire [VCN-1:0][SCN-1:0] c2e0, c2e1, c2e2, c2e3;
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wire [VCN-1:0][SCN-1:0] c2e0, c2e1, c2e2, c2e3;
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wire [VCN-1:0][SCN-1:0] c2l0, c2l1, c2l2, c2l3;
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wire [VCN-1:0][SCN-1:0] c2l0, c2l1, c2l2, c2l3;
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// internal wires for ack and eof bits
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// internal wires for ack and eof bits
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [VCN-1:0][SCN-1:0] s2c4, w2c4, n2c4, e2c4, l2c4;
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wire [VCN-1:0][SCN-1:0] s2c4, w2c4, n2c4, e2c4, l2c4;
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wire [VCN-1:0][SCN-1:0] c2s4, c2w4, c2n4, c2e4, c2l4;
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wire [VCN-1:0][SCN-1:0] c2s4, c2w4, c2n4, c2e4, c2l4;
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wire [VCN-1:0][SCN-1:0] s2ca, w2ca, n2ca, e2ca, l2ca;
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wire [VCN-1:0][SCN-1:0] s2ca, w2ca, n2ca, e2ca, l2ca;
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wire [VCN-1:0][SCN-1:0] c2sa, c2wa, c2na, c2ea, c2la;
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wire [VCN-1:0][SCN-1:0] c2sa, c2wa, c2na, c2ea, c2la;
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`else
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`else
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wire [VCN-1:0] s2c4, w2c4, n2c4, e2c4, l2c4;
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wire [VCN-1:0] s2c4, w2c4, n2c4, e2c4, l2c4;
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wire [VCN-1:0] c2s4, c2w4, c2n4, c2e4, c2l4;
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wire [VCN-1:0] c2s4, c2w4, c2n4, c2e4, c2l4;
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wire [VCN-1:0] s2ca, w2ca, n2ca, e2ca, l2ca;
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wire [VCN-1:0] s2ca, w2ca, n2ca, e2ca, l2ca;
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wire [VCN-1:0] c2sa, c2wa, c2na, c2ea, c2la;
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wire [VCN-1:0] c2sa, c2wa, c2na, c2ea, c2la;
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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// the requests/acks from/to input buffers to switch allocators
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// the requests/acks from/to input buffers to switch allocators
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wire [VCN-1:0][3:0] sreq, nreq, lreq;
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wire [VCN-1:0][3:0] sreq, nreq, lreq;
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wire [VCN-1:0][1:0] wreq, ereq;
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wire [VCN-1:0][1:0] wreq, ereq;
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wire [VCN-1:0] sack, wack, nack, eack, lack;
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wire [VCN-1:0] sack, wack, nack, eack, lack;
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// configuration bits for the switches
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// configuration bits for the switches
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`ifdef ENABLE_CLOS
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`ifdef ENABLE_CLOS
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wire [4:0][VCN-1:0][VCN-1:0] imcfg;
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wire [4:0][VCN-1:0][VCN-1:0] imcfg;
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wire [VCN-1:0][1:0] scfg, ncfg;
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wire [VCN-1:0][1:0] scfg, ncfg;
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wire [VCN-1:0][3:0] wcfg, ecfg, lcfg;
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wire [VCN-1:0][3:0] wcfg, ecfg, lcfg;
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`else // normal crossbar based SDM
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`else // normal crossbar based SDM
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wire [VCN-1:0][2*VCN-1:0] scfg, ncfg;
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wire [VCN-1:0][2*VCN-1:0] scfg, ncfg;
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wire [VCN-1:0][4*VCN-1:0] wcfg, ecfg, lcfg;
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wire [VCN-1:0][4*VCN-1:0] wcfg, ecfg, lcfg;
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`endif
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`endif
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genvar i;
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genvar i;
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generate
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generate
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for (i=0; i<VCN; i++) begin: SC
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for (i=0; i<VCN; i++) begin: SC
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// --------------- input buffers ------------------- //
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// --------------- input buffers ------------------- //
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inp_buf #(.DIR(0), .RN(4), .DW(DW), .PD(IPD))
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inp_buf #(.DIR(0), .RN(4), .DW(DW), .PD(IPD))
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SIB (
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SIB (
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.o0 ( s2c0[i] ),
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.o0 ( s2c0[i] ),
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.o1 ( s2c1[i] ),
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.o1 ( s2c1[i] ),
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.o2 ( s2c2[i] ),
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.o2 ( s2c2[i] ),
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.o3 ( s2c3[i] ),
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.o3 ( s2c3[i] ),
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.o4 ( s2c4[i] ),
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.o4 ( s2c4[i] ),
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.ia ( sia[i] ),
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.ia ( sia[i] ),
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.arb_r ( sreq[i] ),
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.arb_r ( sreq[i] ),
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.rst_n ( rst_n ),
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.rst_n ( rst_n ),
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.i0 ( si0[i] ),
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.i0 ( si0[i] ),
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.i1 ( si1[i] ),
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.i1 ( si1[i] ),
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.i2 ( si2[i] ),
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.i2 ( si2[i] ),
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.i3 ( si3[i] ),
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.i3 ( si3[i] ),
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.i4 ( si4[i] ),
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.i4 ( si4[i] ),
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.oa ( s2ca[i] ),
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.oa ( s2ca[i] ),
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.addrx ( addrx ),
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.addrx ( addrx ),
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.addry ( addry ),
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.addry ( addry ),
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.arb_ra ( sack[i] )
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.arb_ra ( sack[i] )
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);
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);
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inp_buf #(.DIR(1), .RN(2), .DW(DW), .PD(IPD))
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inp_buf #(.DIR(1), .RN(2), .DW(DW), .PD(IPD))
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WIB (
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WIB (
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.o0 ( w2c0[i] ),
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.o0 ( w2c0[i] ),
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.o1 ( w2c1[i] ),
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.o1 ( w2c1[i] ),
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.o2 ( w2c2[i] ),
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.o2 ( w2c2[i] ),
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.o3 ( w2c3[i] ),
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.o3 ( w2c3[i] ),
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.o4 ( w2c4[i] ),
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.o4 ( w2c4[i] ),
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.ia ( wia[i] ),
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.ia ( wia[i] ),
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.arb_r ( wreq[i] ),
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.arb_r ( wreq[i] ),
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.rst_n ( rst_n ),
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.rst_n ( rst_n ),
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.i0 ( wi0[i] ),
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.i0 ( wi0[i] ),
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.i1 ( wi1[i] ),
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.i1 ( wi1[i] ),
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.i2 ( wi2[i] ),
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.i2 ( wi2[i] ),
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.i3 ( wi3[i] ),
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.i3 ( wi3[i] ),
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.i4 ( wi4[i] ),
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.i4 ( wi4[i] ),
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.oa ( w2ca[i] ),
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.oa ( w2ca[i] ),
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.addrx ( addrx ),
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.addrx ( addrx ),
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.addry ( addry ),
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.addry ( addry ),
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.arb_ra ( wack[i] )
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.arb_ra ( wack[i] )
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);
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);
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inp_buf #(.DIR(2), .RN(4), .DW(DW), .PD(IPD))
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inp_buf #(.DIR(2), .RN(4), .DW(DW), .PD(IPD))
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NIB (
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NIB (
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.o0 ( n2c0[i] ),
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.o0 ( n2c0[i] ),
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.o1 ( n2c1[i] ),
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.o1 ( n2c1[i] ),
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.o2 ( n2c2[i] ),
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.o2 ( n2c2[i] ),
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.o3 ( n2c3[i] ),
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.o3 ( n2c3[i] ),
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.o4 ( n2c4[i] ),
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.o4 ( n2c4[i] ),
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.ia ( nia[i] ),
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.ia ( nia[i] ),
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.arb_r ( nreq[i] ),
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.arb_r ( nreq[i] ),
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.rst_n ( rst_n ),
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.rst_n ( rst_n ),
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.i0 ( ni0[i] ),
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.i0 ( ni0[i] ),
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.i1 ( ni1[i] ),
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.i1 ( ni1[i] ),
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.i2 ( ni2[i] ),
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.i2 ( ni2[i] ),
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.i3 ( ni3[i] ),
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.i3 ( ni3[i] ),
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.i4 ( ni4[i] ),
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.i4 ( ni4[i] ),
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.oa ( n2ca[i] ),
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.oa ( n2ca[i] ),
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.addrx ( addrx ),
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.addrx ( addrx ),
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.addry ( addry ),
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.addry ( addry ),
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.arb_ra ( nack[i] )
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.arb_ra ( nack[i] )
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);
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);
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inp_buf #(.DIR(3), .RN(2), .DW(DW), .PD(IPD))
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inp_buf #(.DIR(3), .RN(2), .DW(DW), .PD(IPD))
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EIB (
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EIB (
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.o0 ( e2c0[i] ),
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.o0 ( e2c0[i] ),
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.o1 ( e2c1[i] ),
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.o1 ( e2c1[i] ),
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.o2 ( e2c2[i] ),
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.o2 ( e2c2[i] ),
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.o3 ( e2c3[i] ),
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.o3 ( e2c3[i] ),
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.o4 ( e2c4[i] ),
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.o4 ( e2c4[i] ),
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.ia ( eia[i] ),
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.ia ( eia[i] ),
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.arb_r ( ereq[i] ),
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.arb_r ( ereq[i] ),
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.rst_n ( rst_n ),
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.rst_n ( rst_n ),
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.i0 ( ei0[i] ),
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.i0 ( ei0[i] ),
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.i1 ( ei1[i] ),
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.i1 ( ei1[i] ),
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.i2 ( ei2[i] ),
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.i2 ( ei2[i] ),
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.i3 ( ei3[i] ),
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.i3 ( ei3[i] ),
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.i4 ( ei4[i] ),
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.i4 ( ei4[i] ),
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.oa ( e2ca[i] ),
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.oa ( e2ca[i] ),
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.addrx ( addrx ),
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.addrx ( addrx ),
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.addry ( addry ),
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.addry ( addry ),
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.arb_ra ( eack[i] )
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.arb_ra ( eack[i] )
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);
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);
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inp_buf #(.DIR(4), .RN(4), .DW(DW), .PD(IPD))
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inp_buf #(.DIR(4), .RN(4), .DW(DW), .PD(IPD))
|
LIB (
|
LIB (
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.o0 ( l2c0[i] ),
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.o0 ( l2c0[i] ),
|
.o1 ( l2c1[i] ),
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.o1 ( l2c1[i] ),
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.o2 ( l2c2[i] ),
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.o2 ( l2c2[i] ),
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.o3 ( l2c3[i] ),
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.o3 ( l2c3[i] ),
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.o4 ( l2c4[i] ),
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.o4 ( l2c4[i] ),
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.ia ( lia[i] ),
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.ia ( lia[i] ),
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.arb_r ( lreq[i] ),
|
.arb_r ( lreq[i] ),
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.rst_n ( rst_n ),
|
.rst_n ( rst_n ),
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.i0 ( li0[i] ),
|
.i0 ( li0[i] ),
|
.i1 ( li1[i] ),
|
.i1 ( li1[i] ),
|
.i2 ( li2[i] ),
|
.i2 ( li2[i] ),
|
.i3 ( li3[i] ),
|
.i3 ( li3[i] ),
|
.i4 ( li4[i] ),
|
.i4 ( li4[i] ),
|
.oa ( l2ca[i] ),
|
.oa ( l2ca[i] ),
|
.addrx ( addrx ),
|
.addrx ( addrx ),
|
.addry ( addry ),
|
.addry ( addry ),
|
.arb_ra ( lack[i] )
|
.arb_ra ( lack[i] )
|
);
|
);
|
|
|
// --------------------- output buffers ---------------- //
|
// --------------------- output buffers ---------------- //
|
outp_buf #(.DW(DW), .PD(OPD))
|
outp_buf #(.DW(DW), .PD(OPD))
|
SOB (
|
SOB (
|
.o0 ( so0[i] ),
|
.o0 ( so0[i] ),
|
.o1 ( so1[i] ),
|
.o1 ( so1[i] ),
|
.o2 ( so2[i] ),
|
.o2 ( so2[i] ),
|
.o3 ( so3[i] ),
|
.o3 ( so3[i] ),
|
.o4 ( so4[i] ),
|
.o4 ( so4[i] ),
|
.oa ( soa[i] ),
|
.oa ( soa[i] ),
|
.i0 ( c2s0[i] ),
|
.i0 ( c2s0[i] ),
|
.i1 ( c2s1[i] ),
|
.i1 ( c2s1[i] ),
|
.i2 ( c2s2[i] ),
|
.i2 ( c2s2[i] ),
|
.i3 ( c2s3[i] ),
|
.i3 ( c2s3[i] ),
|
.i4 ( c2s4[i] ),
|
.i4 ( c2s4[i] ),
|
.ia ( c2sa[i] ),
|
.ia ( c2sa[i] ),
|
.rst_n ( rst_n )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
outp_buf #(.DW(DW), .PD(OPD))
|
outp_buf #(.DW(DW), .PD(OPD))
|
WOB (
|
WOB (
|
.o0 ( wo0[i] ),
|
.o0 ( wo0[i] ),
|
.o1 ( wo1[i] ),
|
.o1 ( wo1[i] ),
|
.o2 ( wo2[i] ),
|
.o2 ( wo2[i] ),
|
.o3 ( wo3[i] ),
|
.o3 ( wo3[i] ),
|
.o4 ( wo4[i] ),
|
.o4 ( wo4[i] ),
|
.oa ( woa[i] ),
|
.oa ( woa[i] ),
|
.i0 ( c2w0[i] ),
|
.i0 ( c2w0[i] ),
|
.i1 ( c2w1[i] ),
|
.i1 ( c2w1[i] ),
|
.i2 ( c2w2[i] ),
|
.i2 ( c2w2[i] ),
|
.i3 ( c2w3[i] ),
|
.i3 ( c2w3[i] ),
|
.i4 ( c2w4[i] ),
|
.i4 ( c2w4[i] ),
|
.ia ( c2wa[i] ),
|
.ia ( c2wa[i] ),
|
.rst_n ( rst_n )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
outp_buf #(.DW(DW), .PD(OPD))
|
outp_buf #(.DW(DW), .PD(OPD))
|
NOB (
|
NOB (
|
.o0 ( no0[i] ),
|
.o0 ( no0[i] ),
|
.o1 ( no1[i] ),
|
.o1 ( no1[i] ),
|
.o2 ( no2[i] ),
|
.o2 ( no2[i] ),
|
.o3 ( no3[i] ),
|
.o3 ( no3[i] ),
|
.o4 ( no4[i] ),
|
.o4 ( no4[i] ),
|
.oa ( noa[i] ),
|
.oa ( noa[i] ),
|
.i0 ( c2n0[i] ),
|
.i0 ( c2n0[i] ),
|
.i1 ( c2n1[i] ),
|
.i1 ( c2n1[i] ),
|
.i2 ( c2n2[i] ),
|
.i2 ( c2n2[i] ),
|
.i3 ( c2n3[i] ),
|
.i3 ( c2n3[i] ),
|
.i4 ( c2n4[i] ),
|
.i4 ( c2n4[i] ),
|
.ia ( c2na[i] ),
|
.ia ( c2na[i] ),
|
.rst_n ( rst_n )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
outp_buf #(.DW(DW), .PD(OPD))
|
outp_buf #(.DW(DW), .PD(OPD))
|
EOB (
|
EOB (
|
.o0 ( eo0[i] ),
|
.o0 ( eo0[i] ),
|
.o1 ( eo1[i] ),
|
.o1 ( eo1[i] ),
|
.o2 ( eo2[i] ),
|
.o2 ( eo2[i] ),
|
.o3 ( eo3[i] ),
|
.o3 ( eo3[i] ),
|
.o4 ( eo4[i] ),
|
.o4 ( eo4[i] ),
|
.oa ( eoa[i] ),
|
.oa ( eoa[i] ),
|
.i0 ( c2e0[i] ),
|
.i0 ( c2e0[i] ),
|
.i1 ( c2e1[i] ),
|
.i1 ( c2e1[i] ),
|
.i2 ( c2e2[i] ),
|
.i2 ( c2e2[i] ),
|
.i3 ( c2e3[i] ),
|
.i3 ( c2e3[i] ),
|
.i4 ( c2e4[i] ),
|
.i4 ( c2e4[i] ),
|
.ia ( c2ea[i] ),
|
.ia ( c2ea[i] ),
|
.rst_n ( rst_n )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
outp_buf #(.DW(DW), .PD(OPD))
|
outp_buf #(.DW(DW), .PD(OPD))
|
LOB (
|
LOB (
|
.o0 ( lo0[i] ),
|
.o0 ( lo0[i] ),
|
.o1 ( lo1[i] ),
|
.o1 ( lo1[i] ),
|
.o2 ( lo2[i] ),
|
.o2 ( lo2[i] ),
|
.o3 ( lo3[i] ),
|
.o3 ( lo3[i] ),
|
.o4 ( lo4[i] ),
|
.o4 ( lo4[i] ),
|
.oa ( loa[i] ),
|
.oa ( loa[i] ),
|
.i0 ( c2l0[i] ),
|
.i0 ( c2l0[i] ),
|
.i1 ( c2l1[i] ),
|
.i1 ( c2l1[i] ),
|
.i2 ( c2l2[i] ),
|
.i2 ( c2l2[i] ),
|
.i3 ( c2l3[i] ),
|
.i3 ( c2l3[i] ),
|
.i4 ( c2l4[i] ),
|
.i4 ( c2l4[i] ),
|
.ia ( c2la[i] ),
|
.ia ( c2la[i] ),
|
.rst_n ( rst_n )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
end // block: SC
|
end // block: SC
|
endgenerate
|
endgenerate
|
|
|
`ifdef ENABLE_CLOS
|
`ifdef ENABLE_CLOS
|
dclos #(.MN(VCN), .NN(VCN), .DW(DW))
|
dclos #(.MN(VCN), .NN(VCN), .DW(DW))
|
CB (
|
CB (
|
.so0 ( c2s0 ),
|
.so0 ( c2s0 ),
|
.so1 ( c2s1 ),
|
.so1 ( c2s1 ),
|
.so2 ( c2s2 ),
|
.so2 ( c2s2 ),
|
.so3 ( c2s3 ),
|
.so3 ( c2s3 ),
|
.so4 ( c2s4 ),
|
.so4 ( c2s4 ),
|
.soa ( c2sa ),
|
.soa ( c2sa ),
|
.wo0 ( c2w0 ),
|
.wo0 ( c2w0 ),
|
.wo1 ( c2w1 ),
|
.wo1 ( c2w1 ),
|
.wo2 ( c2w2 ),
|
.wo2 ( c2w2 ),
|
.wo3 ( c2w3 ),
|
.wo3 ( c2w3 ),
|
.wo4 ( c2w4 ),
|
.wo4 ( c2w4 ),
|
.woa ( c2wa ),
|
.woa ( c2wa ),
|
.no0 ( c2n0 ),
|
.no0 ( c2n0 ),
|
.no1 ( c2n1 ),
|
.no1 ( c2n1 ),
|
.no2 ( c2n2 ),
|
.no2 ( c2n2 ),
|
.no3 ( c2n3 ),
|
.no3 ( c2n3 ),
|
.no4 ( c2n4 ),
|
.no4 ( c2n4 ),
|
.noa ( c2na ),
|
.noa ( c2na ),
|
.eo0 ( c2e0 ),
|
.eo0 ( c2e0 ),
|
.eo1 ( c2e1 ),
|
.eo1 ( c2e1 ),
|
.eo2 ( c2e2 ),
|
.eo2 ( c2e2 ),
|
.eo3 ( c2e3 ),
|
.eo3 ( c2e3 ),
|
.eo4 ( c2e4 ),
|
.eo4 ( c2e4 ),
|
.eoa ( c2ea ),
|
.eoa ( c2ea ),
|
.lo0 ( c2l0 ),
|
.lo0 ( c2l0 ),
|
.lo1 ( c2l1 ),
|
.lo1 ( c2l1 ),
|
.lo2 ( c2l2 ),
|
.lo2 ( c2l2 ),
|
.lo3 ( c2l3 ),
|
.lo3 ( c2l3 ),
|
.lo4 ( c2l4 ),
|
.lo4 ( c2l4 ),
|
.loa ( c2la ),
|
.loa ( c2la ),
|
.si0 ( s2c0 ),
|
.si0 ( s2c0 ),
|
.si1 ( s2c1 ),
|
.si1 ( s2c1 ),
|
.si2 ( s2c2 ),
|
.si2 ( s2c2 ),
|
.si3 ( s2c3 ),
|
.si3 ( s2c3 ),
|
.si4 ( s2c4 ),
|
.si4 ( s2c4 ),
|
.sia ( s2ca ),
|
.sia ( s2ca ),
|
.wi0 ( w2c0 ),
|
.wi0 ( w2c0 ),
|
.wi1 ( w2c1 ),
|
.wi1 ( w2c1 ),
|
.wi2 ( w2c2 ),
|
.wi2 ( w2c2 ),
|
.wi3 ( w2c3 ),
|
.wi3 ( w2c3 ),
|
.wi4 ( w2c4 ),
|
.wi4 ( w2c4 ),
|
.wia ( w2ca ),
|
.wia ( w2ca ),
|
.ni0 ( n2c0 ),
|
.ni0 ( n2c0 ),
|
.ni1 ( n2c1 ),
|
.ni1 ( n2c1 ),
|
.ni2 ( n2c2 ),
|
.ni2 ( n2c2 ),
|
.ni3 ( n2c3 ),
|
.ni3 ( n2c3 ),
|
.ni4 ( n2c4 ),
|
.ni4 ( n2c4 ),
|
.nia ( n2ca ),
|
.nia ( n2ca ),
|
.ei0 ( e2c0 ),
|
.ei0 ( e2c0 ),
|
.ei1 ( e2c1 ),
|
.ei1 ( e2c1 ),
|
.ei2 ( e2c2 ),
|
.ei2 ( e2c2 ),
|
.ei3 ( e2c3 ),
|
.ei3 ( e2c3 ),
|
.ei4 ( e2c4 ),
|
.ei4 ( e2c4 ),
|
.eia ( e2ca ),
|
.eia ( e2ca ),
|
.li0 ( l2c0 ),
|
.li0 ( l2c0 ),
|
.li1 ( l2c1 ),
|
.li1 ( l2c1 ),
|
.li2 ( l2c2 ),
|
.li2 ( l2c2 ),
|
.li3 ( l2c3 ),
|
.li3 ( l2c3 ),
|
.li4 ( l2c4 ),
|
.li4 ( l2c4 ),
|
.lia ( l2ca ),
|
.lia ( l2ca ),
|
.imcfg ( imcfg ),
|
.imcfg ( imcfg ),
|
.wcfg ( wcfg ),
|
.wcfg ( wcfg ),
|
.ecfg ( ecfg ),
|
.ecfg ( ecfg ),
|
.lcfg ( lcfg ),
|
.lcfg ( lcfg ),
|
.scfg ( scfg ),
|
.scfg ( scfg ),
|
.ncfg ( ncfg )
|
.ncfg ( ncfg )
|
) ;
|
) ;
|
|
|
clos_sch #(.M(VCN), .N(VCN))
|
clos_sch #(.M(VCN), .N(VCN))
|
ALLOC (
|
ALLOC (
|
.sack ( sack ),
|
.sack ( sack ),
|
.wack ( wack ),
|
.wack ( wack ),
|
.nack ( nack ),
|
.nack ( nack ),
|
.eack ( eack ),
|
.eack ( eack ),
|
.lack ( lack ),
|
.lack ( lack ),
|
.imc ( imcfg ),
|
.imc ( imcfg ),
|
.scfg ( scfg ),
|
.scfg ( scfg ),
|
.ncfg ( ncfg ),
|
.ncfg ( ncfg ),
|
.wcfg ( wcfg ),
|
.wcfg ( wcfg ),
|
.ecfg ( ecfg ),
|
.ecfg ( ecfg ),
|
.lcfg ( lcfg ),
|
.lcfg ( lcfg ),
|
.sreq ( sreq ),
|
.sreq ( sreq ),
|
.nreq ( nreq ),
|
.nreq ( nreq ),
|
.lreq ( lreq ),
|
.lreq ( lreq ),
|
.wreq ( wreq ),
|
.wreq ( wreq ),
|
.ereq ( ereq ),
|
.ereq ( ereq ),
|
.rst_n ( rst_n )
|
.rst_n ( rst_n )
|
);
|
);
|
`else // Crossbar based SDM
|
`else // Crossbar based SDM
|
|
|
dcb_xy #(.VCN(VCN), .VCW(DW))
|
dcb_xy #(.VCN(VCN), .VCW(DW))
|
CB (
|
CB (
|
.so0 ( c2s0 ),
|
.so0 ( c2s0 ),
|
.so1 ( c2s1 ),
|
.so1 ( c2s1 ),
|
.so2 ( c2s2 ),
|
.so2 ( c2s2 ),
|
.so3 ( c2s3 ),
|
.so3 ( c2s3 ),
|
.so4 ( c2s4 ),
|
.so4 ( c2s4 ),
|
.soa ( c2sa ),
|
.soa ( c2sa ),
|
.wo0 ( c2w0 ),
|
.wo0 ( c2w0 ),
|
.wo1 ( c2w1 ),
|
.wo1 ( c2w1 ),
|
.wo2 ( c2w2 ),
|
.wo2 ( c2w2 ),
|
.wo3 ( c2w3 ),
|
.wo3 ( c2w3 ),
|
.wo4 ( c2w4 ),
|
.wo4 ( c2w4 ),
|
.woa ( c2wa ),
|
.woa ( c2wa ),
|
.no0 ( c2n0 ),
|
.no0 ( c2n0 ),
|
.no1 ( c2n1 ),
|
.no1 ( c2n1 ),
|
.no2 ( c2n2 ),
|
.no2 ( c2n2 ),
|
.no3 ( c2n3 ),
|
.no3 ( c2n3 ),
|
.no4 ( c2n4 ),
|
.no4 ( c2n4 ),
|
.noa ( c2na ),
|
.noa ( c2na ),
|
.eo0 ( c2e0 ),
|
.eo0 ( c2e0 ),
|
.eo1 ( c2e1 ),
|
.eo1 ( c2e1 ),
|
.eo2 ( c2e2 ),
|
.eo2 ( c2e2 ),
|
.eo3 ( c2e3 ),
|
.eo3 ( c2e3 ),
|
.eo4 ( c2e4 ),
|
.eo4 ( c2e4 ),
|
.eoa ( c2ea ),
|
.eoa ( c2ea ),
|
.lo0 ( c2l0 ),
|
.lo0 ( c2l0 ),
|
.lo1 ( c2l1 ),
|
.lo1 ( c2l1 ),
|
.lo2 ( c2l2 ),
|
.lo2 ( c2l2 ),
|
.lo3 ( c2l3 ),
|
.lo3 ( c2l3 ),
|
.lo4 ( c2l4 ),
|
.lo4 ( c2l4 ),
|
.loa ( c2la ),
|
.loa ( c2la ),
|
.si0 ( s2c0 ),
|
.si0 ( s2c0 ),
|
.si1 ( s2c1 ),
|
.si1 ( s2c1 ),
|
.si2 ( s2c2 ),
|
.si2 ( s2c2 ),
|
.si3 ( s2c3 ),
|
.si3 ( s2c3 ),
|
.si4 ( s2c4 ),
|
.si4 ( s2c4 ),
|
.sia ( s2ca ),
|
.sia ( s2ca ),
|
.wi0 ( w2c0 ),
|
.wi0 ( w2c0 ),
|
.wi1 ( w2c1 ),
|
.wi1 ( w2c1 ),
|
.wi2 ( w2c2 ),
|
.wi2 ( w2c2 ),
|
.wi3 ( w2c3 ),
|
.wi3 ( w2c3 ),
|
.wi4 ( w2c4 ),
|
.wi4 ( w2c4 ),
|
.wia ( w2ca ),
|
.wia ( w2ca ),
|
.ni0 ( n2c0 ),
|
.ni0 ( n2c0 ),
|
.ni1 ( n2c1 ),
|
.ni1 ( n2c1 ),
|
.ni2 ( n2c2 ),
|
.ni2 ( n2c2 ),
|
.ni3 ( n2c3 ),
|
.ni3 ( n2c3 ),
|
.ni4 ( n2c4 ),
|
.ni4 ( n2c4 ),
|
.nia ( n2ca ),
|
.nia ( n2ca ),
|
.ei0 ( e2c0 ),
|
.ei0 ( e2c0 ),
|
.ei1 ( e2c1 ),
|
.ei1 ( e2c1 ),
|
.ei2 ( e2c2 ),
|
.ei2 ( e2c2 ),
|
.ei3 ( e2c3 ),
|
.ei3 ( e2c3 ),
|
.ei4 ( e2c4 ),
|
.ei4 ( e2c4 ),
|
.eia ( e2ca ),
|
.eia ( e2ca ),
|
.li0 ( l2c0 ),
|
.li0 ( l2c0 ),
|
.li1 ( l2c1 ),
|
.li1 ( l2c1 ),
|
.li2 ( l2c2 ),
|
.li2 ( l2c2 ),
|
.li3 ( l2c3 ),
|
.li3 ( l2c3 ),
|
.li4 ( l2c4 ),
|
.li4 ( l2c4 ),
|
.lia ( l2ca ),
|
.lia ( l2ca ),
|
.wcfg ( wcfg ),
|
.wcfg ( wcfg ),
|
.ecfg ( ecfg ),
|
.ecfg ( ecfg ),
|
.lcfg ( lcfg ),
|
.lcfg ( lcfg ),
|
.scfg ( scfg ),
|
.scfg ( scfg ),
|
.ncfg ( ncfg )
|
.ncfg ( ncfg )
|
) ;
|
) ;
|
|
|
|
|
sdm_sch #(.VCN(VCN))
|
sdm_sch #(.VCN(VCN))
|
ALLOC (
|
ALLOC (
|
.sack ( sack ),
|
.sack ( sack ),
|
.wack ( wack ),
|
.wack ( wack ),
|
.nack ( nack ),
|
.nack ( nack ),
|
.eack ( eack ),
|
.eack ( eack ),
|
.lack ( lack ),
|
.lack ( lack ),
|
.scfg ( scfg ),
|
.scfg ( scfg ),
|
.ncfg ( ncfg ),
|
.ncfg ( ncfg ),
|
.wcfg ( wcfg ),
|
.wcfg ( wcfg ),
|
.ecfg ( ecfg ),
|
.ecfg ( ecfg ),
|
.lcfg ( lcfg ),
|
.lcfg ( lcfg ),
|
.sreq ( sreq ),
|
.sreq ( sreq ),
|
.nreq ( nreq ),
|
.nreq ( nreq ),
|
.lreq ( lreq ),
|
.lreq ( lreq ),
|
.wreq ( wreq ),
|
.wreq ( wreq ),
|
.ereq ( ereq ),
|
.ereq ( ereq ),
|
.rst_n ( rst_n )
|
.rst_n ( rst_n )
|
);
|
);
|
`endif
|
`endif
|
|
|
endmodule // router
|
endmodule // router
|
|
|