/*
|
/*
|
Asynchronous SDM NoC
|
Asynchronous SDM NoC
|
(C)2011 Wei Song
|
(C)2011 Wei Song
|
Advanced Processor Technologies Group
|
Advanced Processor Technologies Group
|
Computer Science, the Univ. of Manchester, UK
|
Computer Science, the Univ. of Manchester, UK
|
|
|
Authors:
|
Authors:
|
Wei Song wsong83@gmail.com
|
Wei Song wsong83@gmail.com
|
|
|
License: LGPL 3.0 or later
|
License: LGPL 3.0 or later
|
|
|
The full dual-rail pipeline stage for the credit fifo in VC routers.
|
The full dual-rail pipeline stage for the credit fifo in VC routers.
|
It has a reset pin to feed a token into every cpipe stage.
|
It has a reset pin to feed a token into every cpipe stage.
|
|
|
History:
|
History:
|
31/03/2010 Initial version. <wsong83@gmail.com>
|
31/03/2010 Initial version. <wsong83@gmail.com>
|
01/06/2011 Clean up for opensource. <wsong83@gmail.com>
|
01/06/2011 Clean up for opensource. <wsong83@gmail.com>
|
|
|
*/
|
*/
|
|
|
module cpipe (/*AUTOARG*/
|
module cpipe (/*AUTOARG*/
|
// Outputs
|
// Outputs
|
cia, co,
|
cia, co,
|
// Inputs
|
// Inputs
|
rst, ci, coa
|
rst, ci, coa
|
);
|
);
|
|
|
input rst; // active high reset
|
input rst; // active high reset
|
input ci; // credit input
|
input ci; // credit input
|
output cia; // credit input ack
|
output cia; // credit input ack
|
output co; // credit output
|
output co; // credit output
|
input coa; // credit output ack
|
input coa; // credit output ack
|
|
|
wire c0, c1; // internal wires
|
wire c0, c1; // internal wires
|
|
|
dc2 C0 ( .d(ci), .a(~c1), .q(c0));
|
dc2 C0 ( .d(ci), .a(~c1), .q(c0));
|
dc2 C1 ( .d(c0|rst), .a((~coa)|rst), .q(c1));
|
dc2 C1 ( .d(c0|rst), .a((~coa)|rst), .q(c1));
|
|
|
assign co = (~rst)&c1;
|
assign co = (~rst)&c1;
|
assign cia = c0;
|
assign cia = c0;
|
|
|
endmodule // cpipe
|
endmodule // cpipe
|
|
|
