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[/] [async_sdm_noc/] [tags/] [v0.2/] [vc/] [src/] [fcctl.v] - Diff between revs 47 and 56

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/*
/*
 Asynchronous SDM NoC
 Asynchronous SDM NoC
 (C)2011 Wei Song
 (C)2011 Wei Song
 Advanced Processor Technologies Group
 Advanced Processor Technologies Group
 Computer Science, the Univ. of Manchester, UK
 Computer Science, the Univ. of Manchester, UK
 
 
 Authors:
 Authors:
 Wei Song     wsong83@gmail.com
 Wei Song     wsong83@gmail.com
 
 
 License: LGPL 3.0 or later
 License: LGPL 3.0 or later
 
 
 Flow control unit.
 Flow control unit.
 
 
 History:
 History:
 31/03/2010  Initial version. <wsong83@gmail.com>
 31/03/2010  Initial version. <wsong83@gmail.com>
 12/05/2010  Use MPxP crossbar. <wsong83@gmail.com>
 12/05/2010  Use MPxP crossbar. <wsong83@gmail.com>
 02/06/2011  Clean up for opensource. <wsong83@gmail.com>
 02/06/2011  Clean up for opensource. <wsong83@gmail.com>
 
 
*/
*/
 
 
module fcctl ( /*AUTOARG*/
module fcctl ( /*AUTOARG*/
   // Outputs
   // Outputs
   afc, ro,
   afc, ro,
   // Inputs
   // Inputs
   credit, ri, rst
   credit, ri, rst
   );
   );
   parameter VCN = 2;           // number of VCs per direction
   parameter VCN = 2;           // number of VCs per direction
   parameter PD = 3;            // depth of an input VC buffer
   parameter PD = 3;            // depth of an input VC buffer
 
 
   input [VCN-1:0]  credit;      // credit input from the next router
   input [VCN-1:0]  credit;      // credit input from the next router
   output [VCN-1:0] afc; // ack for the credit input
   output [VCN-1:0] afc; // ack for the credit input
   input [VCN-1:0]  ri;          // VC request from VCA
   input [VCN-1:0]  ri;          // VC request from VCA
   output [VCN-1:0] ro;          // credit grant output
   output [VCN-1:0] ro;          // credit grant output
   input            rst;        // active high reset
   input            rst;        // active high reset
 
 
   wire [PD:0][VCN-1:0] cp, cpa;
   wire [PD:0][VCN-1:0] cp, cpa;
 
 
   genvar                 i,j;
   genvar                 i,j;
 
 
   // the credit pipeline
   // the credit pipeline
   generate
   generate
      for(i=0; i<PD; i++) begin: P
      for(i=0; i<PD; i++) begin: P
         for(j=0; j<VCN; j++) begin: V
         for(j=0; j<VCN; j++) begin: V
            cpipe CP (.cia(cpa[i][j]), .co(cp[i+1][j]), .rst(rst), .ci(cp[i][j]), .coa(cpa[i+1][j]));
            cpipe CP (.cia(cpa[i][j]), .co(cp[i+1][j]), .rst(rst), .ci(cp[i][j]), .coa(cpa[i+1][j]));
         end
         end
      end
      end
   endgenerate
   endgenerate
 
 
   // grant a credit to a VC request
   // grant a credit to a VC request
   generate
   generate
      for(i=0; i<VCN; i++) begin:R
      for(i=0; i<VCN; i++) begin:R
         dc2 CR (.a(ri[i]), .d(cp[PD][i]), .q(cpa[PD][i]));
         dc2 CR (.a(ri[i]), .d(cp[PD][i]), .q(cpa[PD][i]));
      end
      end
   endgenerate
   endgenerate
 
 
   assign ro = cpa[PD];
   assign ro = cpa[PD];
   assign cp[0] = credit;
   assign cp[0] = credit;
   assign afc = cpa[0];
   assign afc = cpa[0];
 
 
endmodule // fcctl
endmodule // fcctl
 
 
 
 

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