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Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
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Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
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Version: 0.2
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Version: 0.2
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On-chip networks or networks-on-chip (NoCs) are the on-chip communication fabric for
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On-chip networks or networks-on-chip (NoCs) are the on-chip communication fabric for
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current and future multiprocessor SoCs (MPSoCs) and chip multiprocessors (CMPs).
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current and future multiprocessor SoCs (MPSoCs) and chip multiprocessors (CMPs).
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Compared with synchronous NoCs, asynchronous NoCs have following benefits:
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Compared with synchronous NoCs, asynchronous NoCs have following benefits:
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* Tolerance to all kinds of delay variations caused by process, power and temperature
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* Tolerance to all kinds of delay variations caused by process, power and temperature
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variations.
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variations.
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* Low transmission latency.
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* Low transmission latency.
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* Zero dynamic power when idle.
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* Zero dynamic power when idle.
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* Unified sync/async interface and easy clock domain integration.
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* Unified sync/async interface and easy clock domain integration.
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Most NoCs use the wormhole flow control method. Many complex flow control methods are
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Most NoCs use the wormhole flow control method. Many complex flow control methods are
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built upon the wormhole method, such as virtual channel (VC), TDMA, and SDM. VC is the
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built upon the wormhole method, such as virtual channel (VC), TDMA, and SDM. VC is the
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most utilized flow control in both sync and async NoCs. However, it is found VC
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most utilized flow control in both sync and async NoCs. However, it is found VC
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compromises the throughput performance of asynchronous NoCs. This project provides a new
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compromises the throughput performance of asynchronous NoCs. This project provides a new
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asynchronous router structure which use SDM rather than VC. It has been shown that SDM
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asynchronous router structure which use SDM rather than VC. It has been shown that SDM
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achieve better throughput than VC in the same router configuration.
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achieve better throughput than VC in the same router configuration.
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This project provide a reconfigurable asynchronous SDM router which can be configured
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This project provide a reconfigurable asynchronous SDM router which can be configured
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into a basic wormhole router or an SDM router with multiple virtual circuits in every
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into a basic wormhole router or an SDM router with multiple virtual circuits in every
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direction.
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direction.
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Features:
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Features:
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* 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local)
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* 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local)
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* The dimension order routing (XY routing)
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* The dimension order routing (XY routing)
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* Available flow control methods: wormhole, SDM, VC
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* Available flow control methods: wormhole, SDM, VC
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* Reconfigurable number of virtual circuits, buffer size, data width
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* Reconfigurable number of virtual circuits, buffer size, data width
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* Fully synthesizable router implementation
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* Fully synthesizable router implementation
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* SystemC testbench provided
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* SystemC testbench provided
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Languages:
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Languages:
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* Routers are written in synthesizable SystemVerilog
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* Routers are written in synthesizable SystemVerilog
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* Test benches are provided by SystemC
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* Test benches are provided by SystemC
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Software requirements:
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Software requirements:
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* The open source Nangate 45nm cell library
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* The open source Nangate 45nm cell library
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* Synopsys Design Compiler (Synthesis)
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* Synopsys Design Compiler (Synthesis)
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* Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation)
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* Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation)
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File structure:
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File structure:
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* common files needed for both SDM and VC routers
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* common files needed for both SDM and VC routers
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\- script synthesis scripts for all routers
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\- script synthesis scripts for all routers
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|- src HDL for all routers
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|- src HDL for all routers
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\- tb test bench files for all routers
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\- tb test bench files for all routers
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* doc documents
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* doc documents
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* lib minimal Nangate 45nm cell lib
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* lib minimal Nangate 45nm cell lib
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* sdm SDM/wormhole router design
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* sdm SDM/wormhole router design
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\- define.v HDL configuration file
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\- define.v HDL configuration file
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|- define.h test bench configuration
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|- define.h test bench configuration
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|- sim simulation run dir
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|- sim simulation run dir
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|- src HDL
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|- src HDL
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|- syn synthesis run dir
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|- syn synthesis run dir
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\- script synthesis script
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\- script synthesis script
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\- tb test bench
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\- tb test bench
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* vc VC router deign
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* vc VC router deign
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\- define.v HDL configure file
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\- define.v HDL configure file
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|- define.h test bench configuration
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|- define.h test bench configuration
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|- sim simulation run dir
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|- sim simulation run dir
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|- src HDL
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|- src HDL
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|- syn synthesis run dir
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|- syn synthesis run dir
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\- script synthesis script
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\- script synthesis script
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\- tb test bench
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\- tb test bench
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How to run:
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How to run:
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* to synthesize a router
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* to synthesize a router
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1. set up your design compiler enviornment and your cell library.
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1. set up your design compiler enviornment and your cell library.
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2. modify the "define.v" configuration file for the strcture your want.
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2. modify the "define.v" configuration file for the strcture your want.
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currently including:
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currently including:
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ENABLE_CLOS use the 2-stage Clos switch instead of crossbar
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ENABLE_CLOS use the 2-stage Clos switch instead of crossbar
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ENABLE_CRRD use the CRRD dispatching algorithm for the Clos
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ENABLE_CRRD use the CRRD dispatching algorithm for the Clos
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ENABLE_MRMA use the multi-resource matching arbiter instead of MNMA
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ENABLE_MRMA use the multi-resource matching arbiter instead of MNMA
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ENABLE_CHANNEL_SLICING use channel slicing
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ENABLE_CHANNEL_SLICING use channel slicing
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ENABLE_LOOKAHEAD use the lookahead pipelines
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ENABLE_LOOKAHEAD use the lookahead pipelines
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ENABLE_EOF router use eof bit to indicate end-of-frame
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ENABLE_EOF router use eof bit to indicate end-of-frame
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3. modify the "compile.tcl" scription for the design parameters.
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3. modify the "compile.tcl" scription for the design parameters.
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currently including:
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currently including:
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VCN number of virtual circuits
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VCN number of virtual circuits
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DW the data width of a single virtual circuit
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DW the data width of a single virtual circuit
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IPD the depth of input buffers
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IPD the depth of input buffers
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OPD the depth of putput buffers
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OPD the depth of putput buffers
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4. if another cell lib is used, change "cell_lib.v" in common\src and other related
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4. if another cell lib is used, change "cell_lib.v" in common\src and other related
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files. (very likely you need to email me for further instructions :-) )
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files. (very likely you need to email me for further instructions :-) )
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5. modify the "tech.tcl" in common/script for your cell library.
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5. modify the "tech.tcl" in common/script for your cell library.
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6. run the synthesis at [sdm/vc]/syn
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6. run the synthesis at [sdm/vc]/syn
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dc_shell -f script/compile.tcl
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dc_shell -f script/compile.tcl
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7. the synthesized netlist is inside [sdm/vc]/syn/file/
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7. the synthesized netlist is inside [sdm/vc]/syn/file/
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* to run post-synthesis simulation
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* to run post-synthesis simulation
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1. check the netlists in [sdm/vc]/syn/file/
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1. check the netlists in [sdm/vc]/syn/file/
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2. modify the testbench configuration "define.h" according to your requirements.
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2. modify the testbench configuration "define.h" according to your requirements.
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Especially make sure the following are matched (at least in the SDM routers):
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ChBW = DW/8; SubChN = VCN
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3. make sure your NC-Simulator is installed alright (proper SystemC support).
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3. make sure your NC-Simulator is installed alright (proper SystemC support).
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4. run the compilation at [sdm/vc]/sim
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4. run the compilation at [sdm/vc]/sim
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compile.tcl
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compile.sh
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5. run the simulation at [sdm/vc]/sim
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5. run the simulation at [sdm/vc]/sim
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ncsim -tcl noctb
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ncsim -tcl noctb
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6. the simulation output files are *.ana at [sdm/vc]/sim
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6. the simulation output files are *.ana at [sdm/vc]/sim
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"throughput.ana":
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"throughput.ana":
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{simulation time in ps} TAB {throughput in bytes}
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{simulation time in ps} TAB {throughput in bytes}
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"delay.ana":
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"delay.ana":
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{simulation time in ps} TAB {avg. frame latency} TAB {avg. path setup delay}
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{simulation time in ps} TAB {avg. frame latency} TAB {avg. path setup delay}
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* The process of synthesize and simulate the VC router is similar to the procedure of
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* The process of synthesize and simulate the VC router is similar to the procedure of
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the wormhole/SDM router.
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the wormhole/SDM router.
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For any questions and bug reports,
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For any questions and bug reports,
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please email to Wei Song from wsong83@gmail.com
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please email to Wei Song from wsong83@gmail.com
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Wei Song
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Wei Song
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08/06/2011
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08/06/2011
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