/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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A synthesizable cell library for asynchronous circuis.
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A synthesizable cell library for asynchronous circuis.
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Some cell are directly initialized to one of the Nangate 45nm cell lib.
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Some cell are directly initialized to one of the Nangate 45nm cell lib.
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History:
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History:
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05/05/2009 Initial version. <wsong83@gmail.com>
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05/05/2009 Initial version. <wsong83@gmail.com>
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20/05/2011 Change to general verilog description for opensource.
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20/05/2011 Change to general verilog description for opensource.
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The Nangate cell library is used. <wsong83@gmail.com>
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The Nangate cell library is used. <wsong83@gmail.com>
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*/
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*/
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// General 2-input C-element
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// General 2-input C-element
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module c2 (a0, a1, q);
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module c2 (a0, a1, q);
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input a0, a1; // two inputs
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input a0, a1; // two inputs
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output q; // output
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output q; // output
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wire [2:0] m; // internal wires
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wire [2:0] m; // internal wires
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nand U1 (m[0], a0, a1);
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nand U1 (m[0], a0, a1);
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nand U2 (m[1], a0, q);
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nand U2 (m[1], a0, q);
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nand U3 (m[2], a1, q);
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nand U3 (m[2], a1, q);
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assign q = &m;
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assign q = &m;
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endmodule
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endmodule
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// the 2-input C-element on data paths, different name for easy synthesis scription
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// the 2-input C-element on data paths, different name for easy synthesis scription
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module dc2 (d, a, q);
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module dc2 (d, a, q);
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input d; // data input
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input d; // data input
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input a; // ack input
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input a; // ack input
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output q; // data output
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output q; // data output
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wire [2:0] m; // internal wires
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wire [2:0] m; // internal wires
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nand U1 (m[0], a, d);
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nand U1 (m[0], a, d);
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nand U2 (m[1], d, q);
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nand U2 (m[1], d, q);
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nand U3 (m[2], a, q);
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nand U3 (m[2], a, q);
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assign q = &m;
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assign q = &m;
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endmodule
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endmodule
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// 2-input C-element with a minus input
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// 2-input C-element with a minus input
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module c2n (a, b, q);
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module c2n (a, b, q);
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input a; // the normal input
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input a; // the normal input
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input b; // the minus input
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input b; // the minus input
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output q; // output
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output q; // output
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wire m; // internal wire
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wire m; // internal wire
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and U1 (m, b, q);
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and U1 (m, b, q);
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or U2 (q, m, a);
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or U2 (q, m, a);
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endmodule
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endmodule
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// 2-input C-element with a plus input
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// 2-input C-element with a plus input
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module c2p (a, b, q);
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module c2p (a, b, q);
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input a; // the normal input
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input a; // the normal input
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input b; // the plus input
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input b; // the plus input
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output q; // output
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output q; // output
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wire m; // internal wire
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wire m; // internal wire
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or U1 (m, b, q);
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or U1 (m, b, q);
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and U2 (q, m, a);
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and U2 (q, m, a);
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endmodule
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endmodule
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// 2-input MUTEX cell, Nangate
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// 2-input MUTEX cell, Nangate
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module mutex ( a, b, qa, qb ); // !!! dont touch !!!
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module mutex2 ( a, b, qa, qb ); // !!! dont touch !!!
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input a, b; // request inputs
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input a, b; // request inputs
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output qa, qb; // grant outputs
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output qa, qb; // grant outputs
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wire qan, qbn; // internal wires
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wire qan, qbn; // internal wires
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NAND2_X2 U1 ( .A1(a), .A2(qbn), .ZN(qan) ); // different driving strength for fast convergence
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NAND2_X2 U1 ( .A1(a), .A2(qbn), .ZN(qan) ); // different driving strength for fast convergence
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NOR3_X2 U2 ( .A1(qbn), .A2(qbn), .A3(qbn), .ZN(qb) ); // pulse filter
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NOR3_X2 U2 ( .A1(qbn), .A2(qbn), .A3(qbn), .ZN(qb) ); // pulse filter
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NOR3_X2 U3 ( .A1(qan), .A2(qan), .A3(qan), .ZN(qa) ); // pulse filter
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NOR3_X2 U3 ( .A1(qan), .A2(qan), .A3(qan), .ZN(qa) ); // pulse filter
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NAND2_X1 U4 ( .A1(b), .A2(qan), .ZN(qbn) );
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NAND2_X1 U4 ( .A1(b), .A2(qan), .ZN(qbn) );
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endmodule
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endmodule
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// 3-input C-element with a plus input
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// 3-input C-element with a plus input
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module c2p1 (a0, a1, b, q);
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module c2p1 (a0, a1, b, q);
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input a0, a1; // normal inputs
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input a0, a1; // normal inputs
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input b; // plus input
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input b; // plus input
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output q; // output
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output q; // output
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wire [2:0] m; // internal wires
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wire [2:0] m; // internal wires
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nand U1 (m[0], a0, a1, b);
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nand U1 (m[0], a0, a1, b);
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nand U2 (m[1], a0, q);
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nand U2 (m[1], a0, q);
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nand U3 (m[2], a1, q);
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nand U3 (m[2], a1, q);
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assign q = &m;
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assign q = &m;
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endmodule
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endmodule
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// the basic element of a tree arbiter
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// the basic element of a tree arbiter
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module tarb ( ngnt, ntgnt, req, treq );
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module tarb ( ngnt, ntgnt, req, treq );
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input [1:0] req; // request input
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input [1:0] req; // request input
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output [1:0] ngnt; // the negative grant output
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output [1:0] ngnt; // the negative grant output
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output treq; // combined request output
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output treq; // combined request output
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input ntgnt; // the negative combined grant input
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input ntgnt; // the negative combined grant input
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wire n1, n2; // internal wires
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wire n1, n2; // internal wires
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wire [1:0] mgnt; // outputs of the MUTEX
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wire [1:0] mgnt; // outputs of the MUTEX
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mutex ME ( .a(req[0]), .b(req[1]), .qa(mgnt[0]), .qb(mgnt[1]) );
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mutex2 ME ( .a(req[0]), .b(req[1]), .qa(mgnt[0]), .qb(mgnt[1]) );
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c2n C0 ( .a(ntgnt), .b(n2), .q(ngnt[0]) );
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c2n C0 ( .a(ntgnt), .b(n2), .q(ngnt[0]) );
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c2n C1 ( .a(ntgnt), .b(n1), .q(ngnt[1]) );
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c2n C1 ( .a(ntgnt), .b(n1), .q(ngnt[1]) );
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nand U1 (treq, n1, n2);
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nand U1 (treq, n1, n2);
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nand U2 (n1, ngnt[0], mgnt[1]);
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nand U2 (n1, ngnt[0], mgnt[1]);
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nand U3 (n2, ngnt[1], mgnt[0]);
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nand U3 (n2, ngnt[1], mgnt[0]);
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endmodule
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endmodule
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// the tile in a multi-resource arbiter
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// the tile in a multi-resource arbiter
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module cr_blk ( bo, hs, cbi, rbi, rg, cg );
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module cr_blk ( bo, hs, cbi, rbi, rg, cg );
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input rg, cg; // input requests
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input rg, cg; // input requests
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input cbi, rbi; // input blockage
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input cbi, rbi; // input blockage
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output bo; // output blockage
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output bo; // output blockage
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output hs; // match result
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output hs; // match result
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wire blk; // internal wire
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wire blk; // internal wire
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c2p1 XG ( .a0(rg), .a1(cg), .b(blk), .q(bo) );
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c2p1 XG ( .a0(rg), .a1(cg), .b(blk), .q(bo) );
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c2p1 HG ( .a0(cbi), .a1(rbi), .b(bo), .q(hs) );
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c2p1 HG ( .a0(cbi), .a1(rbi), .b(bo), .q(hs) );
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nor U1 (blk, rbi, cbi);
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nor U1 (blk, rbi, cbi);
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endmodule
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endmodule
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// a data latch template, Nangate
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// a data latch template, Nangate
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module dlatch ( q, qb, d, g);
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module dlatch ( q, qb, d, g);
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output q, qb;
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output q, qb;
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input d, g;
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input d, g;
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DLH_X1 U1 (.Q(q), .D(d), .G(g));
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DLH_X1 U1 (.Q(q), .D(d), .G(g));
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endmodule
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endmodule
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// a delay line, Nangate
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// a delay line, Nangate
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module delay (q, a);
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module delay (q, a);
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input a;
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input a;
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output q;
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output q;
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BUF_X2 U (.Z(q), .A(a));
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BUF_X2 U (.Z(q), .A(a));
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endmodule
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endmodule
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