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/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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A single 4-phase 1-of-n pipeline stage.
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A single 4-phase 1-of-n pipeline stage.
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History:
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History:
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05/05/2009 Initial version. <wsong83@gmail.com>
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05/05/2009 Initial version. <wsong83@gmail.com>
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01/06/2011 Clean up for opensource. <wsong83@gmail.com>
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01/06/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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module pipen(/*AUTOARG*/
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module pipen(/*AUTOARG*/
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// Outputs
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// Outputs
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d_in_a, d_out,
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d_in_a, d_out,
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// Inputs
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// Inputs
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d_in, d_out_a
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d_in, d_out_a
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);
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);
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parameter DW = 4; // the wire count, the "n" of the 1-of-n code
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parameter DW = 4; // the wire count, the "n" of the 1-of-n code
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input [DW-1:0] d_in;
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input [DW-1:0] d_in;
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output d_in_a;
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output d_in_a;
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output [DW-1:0] d_out;
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output [DW-1:0] d_out;
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input d_out_a;
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input d_out_a;
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genvar i;
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genvar i;
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// the data pipe stage
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// the data pipe stage
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generate for (i=0; i<DW; i=i+1) begin:DD
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generate for (i=0; i<DW; i=i+1) begin:DD
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dc2 DC (.d(d_in[i]), .a(d_out_a), .q(d_out[i]));
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dc2 DC (.d(d_in[i]), .a(d_out_a), .q(d_out[i]));
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end endgenerate
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end endgenerate
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assign d_in_a = |d_out;
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assign d_in_a = |d_out;
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endmodule // pipen
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endmodule // pipen
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