URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [trunk/] [common/] [tb/] [anaproc.v] - Diff between revs 32 and 37

Rev 32	Rev 37
`/*`	`/*`
`Asynchronous SDM NoC`	`Asynchronous SDM NoC`
`(C)2011 Wei Song`	`(C)2011 Wei Song`
`Advanced Processor Technologies Group`	`Advanced Processor Technologies Group`
`Computer Science, the Univ. of Manchester, UK`	`Computer Science, the Univ. of Manchester, UK`

`Authors:`	`Authors:`
`Wei Song wsong83@gmail.com`	`Wei Song wsong83@gmail.com`

`License: LGPL 3.0 or later`	`License: LGPL 3.0 or later`

`The SystemC to keep a module of the simulation analysis object.`	`The SystemC to keep a module of the simulation analysis object.`

`History:`	`History:`
`27/02/2011 Initial version. <wsong83@gmail.com>`	`27/02/2011 Initial version. <wsong83@gmail.com>`
`30/05/2011 Clean up for opensource. <wsong83@gmail.com>`	`30/05/2011 Clean up for opensource. <wsong83@gmail.com>`

`*/`	`*/`

`module AnaProc ()`	`module AnaProc ()`
`//`	`//`
`// The foreign attribute string value must be a SystemC value.`	`// The foreign attribute string value must be a SystemC value.`
`//`	`//`
`(* integer foreign = "SystemC";`	`(* integer foreign = "SystemC";`
`*);`	`*);`
`//`	`//`
`// Verilog port names must match port names exactly as they appear in the`	`// Verilog port names must match port names exactly as they appear in the`
`// sc_module class in SystemC; they must also match in order, mode, and type.`	`// sc_module class in SystemC; they must also match in order, mode, and type.`
`//`	`//`

`endmodule`	`endmodule`