/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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CM allocator (the CM dispatcher in the thesis)
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CM allocator (the CM dispatcher in the thesis)
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*** SystemVerilog is used ***
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*** SystemVerilog is used ***
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References
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References
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For the detail structure, please refer to Section 6.3.1 of the thesis:
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For the detail structure, please refer to Section 6.3.1 of the thesis:
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Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.
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Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.
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History:
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History:
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08/09/2009 Initial version. <wsong83@gmail.com>
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08/09/2009 Initial version. <wsong83@gmail.com>
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20/09/2010 Modified for the Clos SDM router <wsong83@cs.man.ac.uk>
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20/09/2010 Modified for the Clos SDM router <wsong83@cs.man.ac.uk>
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25/05/2011 Clean up for opensource. <wsong83@gmail.com>
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25/05/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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module cm_alloc (/*AUTOARG*/
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module cm_alloc (/*AUTOARG*/
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`ifndef ENABLE_CRRD
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`ifndef ENABLE_CRRD
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s,
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s,
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`endif
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`endif
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// Outputs
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// Outputs
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sra, wra, nra, era, lra, scfg, ncfg, wcfg, ecfg, lcfg,
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sra, wra, nra, era, lra, scfg, ncfg, wcfg, ecfg, lcfg,
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// Inputs
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// Inputs
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wr, er, sr, nr, lr
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wr, er, sr, nr, lr
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) ;
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) ;
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//requests from all IMs
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//requests from all IMs
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input [1:0] wr, er;
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input [1:0] wr, er;
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input [3:0] sr, nr, lr;
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input [3:0] sr, nr, lr;
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// ack to IMs
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// ack to IMs
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output sra, wra, nra, era, lra;
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output sra, wra, nra, era, lra;
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// the configuration to the local CM
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// the configuration to the local CM
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output [1:0] scfg, ncfg;
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output [1:0] scfg, ncfg;
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output [3:0] wcfg, ecfg, lcfg;
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output [3:0] wcfg, ecfg, lcfg;
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// when using the asynchronous dispatching algorithm, status is sent back to IMs
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// when using the asynchronous dispatching algorithm, status is sent back to IMs
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`ifndef ENABLE_CRRD
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`ifndef ENABLE_CRRD
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output [4:0] s;
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output [4:0] s;
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`endif
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`endif
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// arbiters
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// arbiters
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mutex_arb #(2)
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mutex_arb #(2)
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SA ( .req ( {lr[0], nr[0]} ),
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SA ( .req ( {lr[0], nr[0]} ),
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.gnt ( scfg )
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.gnt ( scfg )
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);
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);
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mutex_arb #(4)
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mutex_arb #(4)
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WA ( .req ( {lr[1], er[0], nr[1], sr[0]} ),
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WA ( .req ( {lr[1], er[0], nr[1], sr[0]} ),
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.gnt ( wcfg )
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.gnt ( wcfg )
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);
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);
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mutex_arb #(2)
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mutex_arb #(2)
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NA ( .req ( {lr[2], sr[1]} ),
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NA ( .req ( {lr[2], sr[1]} ),
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.gnt ( ncfg )
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.gnt ( ncfg )
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);
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);
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mutex_arb #(4)
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mutex_arb #(4)
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EA ( .req ( {lr[3], nr[2], wr[0], sr[2]} ),
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EA ( .req ( {lr[3], nr[2], wr[0], sr[2]} ),
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.gnt ( ecfg )
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.gnt ( ecfg )
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);
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);
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mutex_arb #(4)
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mutex_arb #(4)
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LA ( .req ( {er[1], nr[3], wr[1], sr[3]} ),
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LA ( .req ( {er[1], nr[3], wr[1], sr[3]} ),
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.gnt ( lcfg )
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.gnt ( lcfg )
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);
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);
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// generating the ack
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// generating the ack
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assign sra = |{wcfg[0], ncfg[0], ecfg[0], lcfg[0]};
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assign sra = |{wcfg[0], ncfg[0], ecfg[0], lcfg[0]};
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assign wra = |{ecfg[1], lcfg[1]};
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assign wra = |{ecfg[1], lcfg[1]};
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assign nra = |{scfg[0], wcfg[1], ecfg[2], lcfg[2]};
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assign nra = |{scfg[0], wcfg[1], ecfg[2], lcfg[2]};
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assign era = |{wcfg[2], lcfg[3]};
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assign era = |{wcfg[2], lcfg[3]};
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assign lra = |{scfg[1], wcfg[3], ncfg[1], ecfg[3]};
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assign lra = |{scfg[1], wcfg[3], ncfg[1], ecfg[3]};
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// generating the status
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// generating the status
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`ifndef ENABLE_CRRD
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`ifndef ENABLE_CRRD
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assign s = {|lcfg, |ecfg, |ncfg, |wcfg, |scfg};
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assign s = {|lcfg, |ecfg, |ncfg, |wcfg, |scfg};
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`endif
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`endif
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endmodule // cm_alloc
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endmodule // cm_alloc
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