/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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IM allocator (the IM dispatcher in the thesis)
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IM allocator (the IM dispatcher in the thesis)
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*** SystemVerilog is used ***
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*** SystemVerilog is used ***
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References
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References
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For the detail structure, please refer to Section 6.3.1 of the thesis:
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For the detail structure, please refer to Section 6.3.1 of the thesis:
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Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.
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Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.
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History:
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History:
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05/09/2009 Initial version. <wsong83@gmail.com>
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05/09/2009 Initial version. <wsong83@gmail.com>
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10/10/2009 Add the reset port. <wsong83@gmail.com>
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10/10/2009 Add the reset port. <wsong83@gmail.com>
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05/11/2009 Speed up the arbiter. <wsong83@gmail.com>
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05/11/2009 Speed up the arbiter. <wsong83@gmail.com>
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10/06/2010 [Major] change to use PIM structure. <wsong83@gmail.com>
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10/06/2010 [Major] change to use PIM structure. <wsong83@gmail.com>
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23/08/2010 Fix the non-QDI request withdraw process. <wsong83@gmail.com>
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23/08/2010 Fix the non-QDI request withdraw process. <wsong83@gmail.com>
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25/05/2011 Clean up for opensource. <wsong83@gmail.com>
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27/05/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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module im_alloc (/*AUTOARG*/
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module im_alloc (/*AUTOARG*/
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`ifndef ENABLE_CRRD
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`ifndef ENABLE_CRRD
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CMs,
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CMs,
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`endif
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`endif
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// Outputs
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// Outputs
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IMa, cfg,
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IMa, cfg,
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// Inputs
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// Inputs
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IMr, rst_n
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IMr, rst_n
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) ;
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) ;
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// parameters
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// parameters
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parameter VCN = 2; // the number of virtual circuits on one port
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parameter VCN = 2; // the number of virtual circuits on one port
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parameter CMN = 2; // the number of central modules
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parameter CMN = 2; // the number of central modules
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parameter SN = 2; // the possible output port choice of a port
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parameter SN = 2; // the possible output port choice of a port
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input [VCN-1:0][SN-1:0] IMr; // the requests from virtual circuits
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input [VCN-1:0][SN-1:0] IMr; // the requests from virtual circuits
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output [VCN-1:0] IMa; // switch ready, ack for the request
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output [VCN-1:0] IMa; // switch ready, ack for the request
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`ifndef ENABLE_CRRD
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`ifndef ENABLE_CRRD
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input [CMN-1:0][SN-1:0] CMs; // the states from CMs
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input [CMN-1:0][SN-1:0] CMs; // the states from CMs
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`endif
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`endif
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input rst_n; // the negtive active reset
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input rst_n; // the negtive active reset
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output [CMN-1:0][VCN-1:0] cfg; // the matrix configuration signals
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output [CMN-1:0][VCN-1:0] cfg; // the matrix configuration signals
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// internal wires
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// internal wires
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`ifdef ENABLE_CRRD
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`ifdef ENABLE_CRRD
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`ifdef ENABLE_MRMA
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`ifdef ENABLE_MRMA
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wire [VCN-1:0] IPr; // request to the MRMA
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wire [VCN-1:0] IPr; // request to the MRMA
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wire [CMN-1:0] OPrdy, OPblk; // OP ready and blocked status
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wire [CMN-1:0] OPrdy, OPblk; // OP ready and blocked status
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wire [CMN:0] OPrst_n; // the buffered resets to avoid metastability
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wire [CMN:0] OPrst_n; // the buffered resets to avoid metastability
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`else
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`else
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wire [VCN-1:0][CMN-1:0] IPr; // request to the MNMA
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wire [VCN-1:0][CMN-1:0] IPr; // request to the MNMA
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`endif
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`endif
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`else
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`else
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// using the feedback from CMs
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// using the feedback from CMs
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wire [VCN-1:0][CMN-1:0][SN-1:0] IPrm; // to generate the practical IPr
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wire [VCN-1:0][CMN-1:0][SN-1:0] IPrm; // to generate the practical IPr
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wire [VCN-1:0][CMN-1:0] IPr;
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wire [VCN-1:0][CMN-1:0] IPr;
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`endif
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`endif
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// generate variables
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// generate variables
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genvar i, j, k;
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genvar i, j, k;
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//----------------------------------------
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//----------------------------------------
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// the PIM crossbar allocator
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// the PIM crossbar allocator
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`ifndef ENABLE_MRMA
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`ifndef ENABLE_MRMA
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mnma #(.N(VCN), .M(CMN))
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mnma #(.N(VCN), .M(CMN))
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PIMA (
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PIMA (
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.cfg ( cfg ),
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.cfg ( cfg ),
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.r ( IPr ),
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.r ( IPr ),
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.ra ( IMa )
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.ra ( IMa )
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);
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);
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generate
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generate
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for(i=0; i<VCN; i++) begin: IPC
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for(i=0; i<VCN; i++) begin: IPC
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for(j=0; j<CMN; j++) begin: OPC
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for(j=0; j<CMN; j++) begin: OPC
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`ifdef ENABLE_CRRD
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`ifdef ENABLE_CRRD
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IPr[i][j] = |IMr[i];
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assign IPr[i][j] = |IMr[i];
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`else
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`else
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IPr[i][j] = |IPrm[i][j];
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assign IPr[i][j] = |IPrm[i][j];
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for(k=0; k<SN; k++) begin: DIRC
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for(k=0; k<SN; k++) begin: DIRC
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c2p IPRen (.q(IPrm[i][j][k]), .a0(IMr[i][k]), .a1(~CMs[j][k]));
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c2p IPRen (.q(IPrm[i][j][k]), .a0(IMr[i][k]), .a1(~CMs[j][k]));
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end
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end
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`endif
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`endif
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end
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end
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end // block: IPC
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end // block: IPC
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endgenerate
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endgenerate
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`else
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`else
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mrma #(.N(VCN), .M(CMN))
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mrma #(.N(VCN), .M(CMN))
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PIMA (
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PIMA (
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.ca ( IMa ),
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.ca ( IMa ),
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.ra ( OPblk ),
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.ra ( OPblk ),
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.cfg ( cfg ),
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.cfg ( cfg ),
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.c ( IPr ),
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.c ( IPr ),
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.r ( OPrdy ),
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.r ( OPrdy ),
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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generate
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generate
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for(i=0; i<CMN; i++) begin: OPC
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for(i=0; i<CMN; i++) begin: OPC
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delay DLY ( .q(OPrst_n[i+1]), .a(OPrst_n[i])); // dont touch
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delay DLY ( .q(OPrst_n[i+1]), .a(OPrst_n[i])); // dont touch
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assign OPrdy[i] = (~OPblk[i])&OPrst_n[i+1];
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assign OPrdy[i] = (~OPblk[i])&OPrst_n[i+1];
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end
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end
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for(i=0; i<VCN; i++) begin: IPC
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for(i=0; i<VCN; i++) begin: IPC
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assign IPr[i] = |IMr[i];
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assign IPr[i] = |IMr[i];
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end
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end
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endgenerate
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endgenerate
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assign OPrst_n[0] = rst_n;
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`endif // !`ifndef ENABLE_MRMA
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`endif // !`ifndef ENABLE_MRMA
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endmodule // im_alloc
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endmodule // im_alloc
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