/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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Input buffer for Wormhole/SDM routers.
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Input buffer for Wormhole/SDM routers.
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*** SystemVerilog is used ***
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*** SystemVerilog is used ***
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References
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References
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* Lookahead pipelines
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* Lookahead pipelines
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Montek Singh and Steven M. Nowick, The design of high-performance dynamic asynchronous pipelines: lookahead style, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007(15), 1256-1269. doi:10.1109/TVLSI.2007.902205
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Montek Singh and Steven M. Nowick, The design of high-performance dynamic asynchronous pipelines: lookahead style, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007(15), 1256-1269. doi:10.1109/TVLSI.2007.902205
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* Channel slicing
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* Channel slicing
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Wei Song and Doug Edwards, A low latency wormhole router for asynchronous on-chip networks, Asia and South Pacific Design Automation Conference, 2010, 437-443.
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Wei Song and Doug Edwards, A low latency wormhole router for asynchronous on-chip networks, Asia and South Pacific Design Automation Conference, 2010, 437-443.
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* SDM
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* SDM
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Wei Song and Doug Edwards, Asynchronous spatial division multiplexing router, Microprocessors and Microsystems, 2011(35), 85-97.
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Wei Song and Doug Edwards, Asynchronous spatial division multiplexing router, Microprocessors and Microsystems, 2011(35), 85-97.
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History:
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History:
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05/05/2009 Initial version. <wsong83@gmail.com>
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05/05/2009 Initial version. <wsong83@gmail.com>
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20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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24/05/2011 Clean up for opensource. <wsong83@gmail.com>
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24/05/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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module inp_buf (/*AUTOARG*/
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module inp_buf (/*AUTOARG*/
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// Outputs
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// Outputs
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o0, o1, o2, o3, o4, ia, arb_r,
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o0, o1, o2, o3, o4, ia, arb_r,
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// Inputs
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// Inputs
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rst_n, i0, i1, i2, i3, i4, oa, addrx, addry, arb_ra
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rst_n, i0, i1, i2, i3, i4, oa, addrx, addry, arb_ra
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);
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);
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//-------------------------- parameters ---------------------------------------//
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//-------------------------- parameters ---------------------------------------//
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parameter DIR = 0; // the port direction: south, west, north, east, and local
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parameter DIR = 0; // the port direction: south, west, north, east, and local
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parameter RN = 4; // the number of request outputs, must match the direction
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parameter RN = 4; // the number of request outputs, must match the direction
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parameter DW = 16; // the data-width of the data-path
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parameter DW = 16; // the data-width of the data-path
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parameter PD = 2; // the depth of the input buffer
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parameter PD = 2; // the depth of the input buffer
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parameter SCN = DW/2;
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parameter SCN = DW/2;
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//-------------------------- I/O ports ---------------------------------------//
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//-------------------------- I/O ports ---------------------------------------//
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input rst_n; // global reset, active low
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input rst_n; // global reset, active low
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input [SCN-1:0] i0, i1, i2, i3; // data input
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input [SCN-1:0] i0, i1, i2, i3; // data input
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output [SCN-1:0] o0, o1, o2, o3; // data output
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output [SCN-1:0] o0, o1, o2, o3; // data output
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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input [SCN-1:0] i4, oa;
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input [SCN-1:0] i4, oa;
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output [SCN-1:0] o4, ia;
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output [SCN-1:0] o4, ia;
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`else
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`else
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input i4, oa;
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input i4, oa;
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output o4, ia;
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output o4, ia;
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`endif
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`endif
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input [7:0] addrx, addry;
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input [7:0] addrx, addry;
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output [RN-1:0] arb_r;
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output [RN-1:0] arb_r;
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input arb_ra;
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input arb_ra;
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//-------------------------- control signals ---------------------------------------//
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//-------------------------- control signals ---------------------------------------//
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wire rten; // routing enable
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wire rten; // routing enable
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wire frame_end; // identify the end of a frame
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wire frame_end; // identify the end of a frame
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wire [7:0] pipe_xd, pipe_yd; // the target address from the incoming frame
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wire [7:0] pipe_xd, pipe_yd; // the target address from the incoming frame
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wire [PD:0][SCN-1:0] pd0, pd1, pd2, pd3; // data wires for the internal pipeline satges
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wire [PD:0][SCN-1:0] pd0, pd1, pd2, pd3; // data wires for the internal pipeline satges
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wire [5:0] raw_dec; // the routing decision from the comparator
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wire [5:0] raw_dec; // the routing decision from the comparator
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wire [4:0] dec_reg; // the routing decision kept by C-gates
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wire [4:0] dec_reg; // the routing decision kept by C-gates
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wire x_equal; // addr x = target x
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wire x_equal; // addr x = target x
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wire rt_err; // route decoder error
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wire rt_err; // route decoder error
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wire rt_ack; // route build ack
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wire rt_ack; // route build ack
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [SCN-1:0] rtrst; // rt decoder reset for each sub-channel
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wire [SCN-1:0] rtrst; // rt decoder reset for each sub-channel
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wire [PD:0][SCN-1:0] pd4, pda, pdan; // data wires for the internal pipeline stages
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wire [PD:0][SCN-1:0] pd4, pda, pdan; // data wires for the internal pipeline stages
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`else
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`else
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wire rtrst; // rt decode reset
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wire rtrst; // rt decode reset
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wire [PD:0] pd4, pda, pdan; // data wires for the internal pipeline satges
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wire [PD:0] pd4, pda, pdan; // data wires for the internal pipeline satges
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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genvar i, j;
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genvar i, j;
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//------------------------- pipelines ------------------------------------- //
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//------------------------- pipelines ------------------------------------- //
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generate for(i=0; i<PD; i++) begin: DP
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generate for(i=0; i<PD; i++) begin: DP
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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for(j=0; j<SCN; j++) begin: SC
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for(j=0; j<SCN; j++) begin: SC
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pipe4 #(.DW(2))
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pipe4 #(.DW(2))
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P (
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P (
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.o0 ( pd0[i][j] ),
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.o0 ( pd0[i][j] ),
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.o1 ( pd1[i][j] ),
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.o1 ( pd1[i][j] ),
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.o2 ( pd2[i][j] ),
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.o2 ( pd2[i][j] ),
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.o3 ( pd3[i][j] ),
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.o3 ( pd3[i][j] ),
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.o4 ( pd4[i][j] ),
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.o4 ( pd4[i][j] ),
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.ia ( pda[i+1][j] ),
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.ia ( pda[i+1][j] ),
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.i0 ( pd0[i+1][j] ),
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.i0 ( pd0[i+1][j] ),
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.i1 ( pd1[i+1][j] ),
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.i1 ( pd1[i+1][j] ),
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.i2 ( pd2[i+1][j] ),
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.i2 ( pd2[i+1][j] ),
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.i3 ( pd3[i+1][j] ),
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.i3 ( pd3[i+1][j] ),
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.i4 ( pd4[i+1][j] ),
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.i4 ( pd4[i+1][j] ),
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.oa ( pdan[i][j] )
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.oa ( pdan[i][j] )
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);
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);
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end // block: SC
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end // block: SC
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`else // !`ifdef ENABLE_CHANNEL_SLICING
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`else // !`ifdef ENABLE_CHANNEL_SLICING
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pipe4 #(.DW(DW))
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pipe4 #(.DW(DW))
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P (
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P (
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.o0 ( pd0[i] ),
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.o0 ( pd0[i] ),
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.o1 ( pd1[i] ),
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.o1 ( pd1[i] ),
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.o2 ( pd2[i] ),
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.o2 ( pd2[i] ),
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.o3 ( pd3[i] ),
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.o3 ( pd3[i] ),
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.o4 ( pd4[i] ),
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.o4 ( pd4[i] ),
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.ia ( pda[i+1] ),
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.ia ( pda[i+1] ),
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.i0 ( pd0[i+1] ),
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.i0 ( pd0[i+1] ),
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.i1 ( pd1[i+1] ),
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.i1 ( pd1[i+1] ),
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.i2 ( pd2[i+1] ),
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.i2 ( pd2[i+1] ),
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.i3 ( pd3[i+1] ),
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.i3 ( pd3[i+1] ),
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.i4 ( pd4[i+1] ),
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.i4 ( pd4[i+1] ),
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.oa ( pdan[i] )
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.oa ( pdan[i] )
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);
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);
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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end // block: DP
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end // block: DP
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endgenerate
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endgenerate
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generate for(i=1; i<PD; i++) begin: DPA
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generate for(i=1; i<PD; i++) begin: DPA
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assign pdan[i] = rst_n ? ~(pda[i]|pd4[i-1]) : 0;
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assign pdan[i] = rst_n ? ~(pda[i]|pd4[i-1]) : 0;
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end
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end
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endgenerate
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endgenerate
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assign ia = pda[PD]|pd4[PD-1];
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assign ia = pda[PD]|pd4[PD-1];
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assign pd0[PD] = i0;
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assign pd0[PD] = i0;
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assign pd1[PD] = i1;
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assign pd1[PD] = i1;
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assign pd2[PD] = i2;
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assign pd2[PD] = i2;
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assign pd3[PD] = i3;
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assign pd3[PD] = i3;
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assign pd4[PD] = i4;
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assign pd4[PD] = i4;
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assign o0 = pd0[0];
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assign o0 = pd0[0];
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assign o1 = pd1[0];
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assign o1 = pd1[0];
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assign o2 = pd2[0];
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assign o2 = pd2[0];
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assign o3 = pd3[0];
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assign o3 = pd3[0];
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assign o4 = pd4[0];
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assign o4 = pd4[0];
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//---------------------------- route decoder related -------------------------- //
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//---------------------------- route decoder related -------------------------- //
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// fetch the x and y target
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// fetch the x and y target
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and Px_0 (pipe_xd[0], rten, pd0[1][0]);
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and Px_0 (pipe_xd[0], rten, pd0[1][0]);
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and Px_1 (pipe_xd[1], rten, pd1[1][0]);
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and Px_1 (pipe_xd[1], rten, pd1[1][0]);
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and Px_2 (pipe_xd[2], rten, pd2[1][0]);
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and Px_2 (pipe_xd[2], rten, pd2[1][0]);
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and Px_3 (pipe_xd[3], rten, pd3[1][0]);
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and Px_3 (pipe_xd[3], rten, pd3[1][0]);
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and Px_4 (pipe_xd[4], rten, pd0[1][1]);
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and Px_4 (pipe_xd[4], rten, pd0[1][1]);
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and Px_5 (pipe_xd[5], rten, pd1[1][1]);
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and Px_5 (pipe_xd[5], rten, pd1[1][1]);
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and Px_6 (pipe_xd[6], rten, pd2[1][1]);
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and Px_6 (pipe_xd[6], rten, pd2[1][1]);
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and Px_7 (pipe_xd[7], rten, pd3[1][1]);
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and Px_7 (pipe_xd[7], rten, pd3[1][1]);
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and Py_0 (pipe_yd[0], rten, pd0[1][2]);
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and Py_0 (pipe_yd[0], rten, pd0[1][2]);
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and Py_1 (pipe_yd[1], rten, pd1[1][2]);
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and Py_1 (pipe_yd[1], rten, pd1[1][2]);
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and Py_2 (pipe_yd[2], rten, pd2[1][2]);
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and Py_2 (pipe_yd[2], rten, pd2[1][2]);
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and Py_3 (pipe_yd[3], rten, pd3[1][2]);
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and Py_3 (pipe_yd[3], rten, pd3[1][2]);
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and Py_4 (pipe_yd[4], rten, pd0[1][3]);
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and Py_4 (pipe_yd[4], rten, pd0[1][3]);
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and Py_5 (pipe_yd[5], rten, pd1[1][3]);
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and Py_5 (pipe_yd[5], rten, pd1[1][3]);
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and Py_6 (pipe_yd[6], rten, pd2[1][3]);
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and Py_6 (pipe_yd[6], rten, pd2[1][3]);
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and Py_7 (pipe_yd[7], rten, pd3[1][3]);
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and Py_7 (pipe_yd[7], rten, pd3[1][3]);
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routing_decision // the comparator
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routing_decision // the comparator
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RTD(
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RTD(
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.addrx ( addrx )
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.addrx ( addrx )
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,.addry ( addry )
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,.addry ( addry )
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,.pipe_xd ( pipe_xd )
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,.pipe_xd ( pipe_xd )
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,.pipe_yd ( pipe_yd )
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,.pipe_yd ( pipe_yd )
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,.decision ( raw_dec )
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,.decision ( raw_dec )
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);
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);
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// keep the routing decision until the tail flit is received by all sub-channels
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// keep the routing decision until the tail flit is received by all sub-channels
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c2p C_RTD0 ( .a1(raw_dec[0]), .a0((~frame_end)&rst_n), .q(dec_reg[0]));
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c2p C_RTD0 ( .b(raw_dec[0]), .a((~frame_end)&rst_n), .q(dec_reg[0]));
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c2p C_RTD1 ( .a1(raw_dec[1]), .a0((~frame_end)&rst_n), .q(dec_reg[1]));
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c2p C_RTD1 ( .b(raw_dec[1]), .a((~frame_end)&rst_n), .q(dec_reg[1]));
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c2p C_RT_XEQ (.a1(raw_dec[2]), .a0((~frame_end)&rst_n), .q(x_equal) );
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c2p C_RT_XEQ (.b(raw_dec[2]), .a((~frame_end)&rst_n), .q(x_equal) );
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c2p C_RTD2 ( .a1(raw_dec[3]), .a0(x_equal), .q(dec_reg[2]));
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c2p C_RTD2 ( .b(raw_dec[3]), .a(x_equal), .q(dec_reg[2]));
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c2p C_RTD3 ( .a1(raw_dec[4]), .a0(x_equal), .q(dec_reg[3]));
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c2p C_RTD3 ( .b(raw_dec[4]), .a(x_equal), .q(dec_reg[3]));
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c2p C_RTD4 ( .a1(raw_dec[5]), .a0(x_equal), .q(dec_reg[4]));
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c2p C_RTD4 ( .b(raw_dec[5]), .a(x_equal), .q(dec_reg[4]));
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// generate the arbiter request signals
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// generate the arbiter request signals
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assign arb_r =
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assign arb_r =
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DIR == 0 ? {dec_reg[4],dec_reg[2],dec_reg[1],dec_reg[3]} : // south port
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DIR == 0 ? {dec_reg[4],dec_reg[2],dec_reg[1],dec_reg[3]} : // south port
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DIR == 1 ? {dec_reg[4],dec_reg[2]} : // west port
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DIR == 1 ? {dec_reg[4],dec_reg[2]} : // west port
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DIR == 2 ? {dec_reg[4],dec_reg[2],dec_reg[3],dec_reg[0]} : // north port
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DIR == 2 ? {dec_reg[4],dec_reg[2],dec_reg[3],dec_reg[0]} : // north port
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DIR == 3 ? {dec_reg[4],dec_reg[3]} : // east port
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DIR == 3 ? {dec_reg[4],dec_reg[3]} : // east port
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{dec_reg[2],dec_reg[1],dec_reg[3],dec_reg[0]} ; // local port
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{dec_reg[2],dec_reg[1],dec_reg[3],dec_reg[0]} ; // local port
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assign rt_err =
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assign rt_err =
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DIR == 0 ? |{dec_reg[0]} : // south port
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DIR == 0 ? |{dec_reg[0]} : // south port
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DIR == 1 ? |{dec_reg[0],dec_reg[1],dec_reg[3]} : // west port
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DIR == 1 ? |{dec_reg[0],dec_reg[1],dec_reg[3]} : // west port
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DIR == 2 ? |{dec_reg[1]} : // north port
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DIR == 2 ? |{dec_reg[1]} : // north port
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DIR == 3 ? |{dec_reg[0],dec_reg[1],dec_reg[2]} : // east port
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DIR == 3 ? |{dec_reg[0],dec_reg[1],dec_reg[2]} : // east port
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|{dec_reg[4]} ; // local port
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|{dec_reg[4]} ; // local port
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or IP_RTACK (rt_ack, rt_err, arb_ra);
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or IP_RTACK (rt_ack, rt_err, arb_ra);
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// ------------------------ pipeline control ------------------------------ //
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// ------------------------ pipeline control ------------------------------ //
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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for(j=0; j<SCN; j++) begin: SC
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for(j=0; j<SCN; j++) begin: SC
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// the sub-channel controller
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// the sub-channel controller
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subc_ctl SCH_C (
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subc_ctl SCH_C (
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.nack ( pdan[0][j] ),
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.nack ( pdan[0][j] ),
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.rt_rst ( rtrst[j] ),
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.rt_rst ( rtrst[j] ),
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.ai2cb ( oa[j] ),
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.ai2cb ( oa[j] ),
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.ack ( pda[1][j] ),
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.ack ( pda[1][j] ),
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.eof ( pd4[0][j] ),
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.eof ( pd4[0][j] ),
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.rt_ra ( rt_ack ),
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.rt_ra ( rt_ack ),
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.rt_err ( rt_err ),
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.rt_err ( rt_err ),
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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end // block: SC
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end // block: SC
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`else // !`ifdef ENABLE_CHANNEL_SLICING
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`else // !`ifdef ENABLE_CHANNEL_SLICING
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subc_ctl SCH_C (
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subc_ctl SCH_C (
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.nack ( pdan[0] ),
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.nack ( pdan[0] ),
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.rt_rst ( rtrst ),
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.rt_rst ( rtrst ),
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.ai2cb ( oa ),
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.ai2cb ( oa ),
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.ack ( pda[1] ),
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.ack ( pda[1] ),
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.eof ( pd4[0] ),
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.eof ( pd4[0] ),
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.rt_ra ( rt_ack ),
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.rt_ra ( rt_ack ),
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.rt_err ( rt_err ),
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.rt_err ( rt_err ),
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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// the router controller part
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// the router controller part
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assign rten = ~rt_ack;
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assign rten = ~rt_ack;
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assign frame_end = &rtrst;
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assign frame_end = &rtrst;
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endmodule // inp_buf
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endmodule // inp_buf
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// the routing decision making procedure, comparitors
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// the routing decision making procedure, comparitors
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module routing_decision (
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module routing_decision (
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addrx
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addrx
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,addry
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,addry
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,pipe_xd
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,pipe_xd
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,pipe_yd
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,pipe_yd
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,decision
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,decision
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);
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);
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// compare with (2,3)
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// compare with (2,3)
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input [7:0] addrx;
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input [7:0] addrx;
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input [7:0] addry;
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input [7:0] addry;
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|
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input [7:0] pipe_xd;
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input [7:0] pipe_xd;
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input [7:0] pipe_yd;
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input [7:0] pipe_yd;
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output [5:0] decision;
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output [5:0] decision;
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|
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wire [2:0] x_cmp [1:0];
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wire [2:0] x_cmp [1:0];
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wire [2:0] y_cmp [1:0];
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wire [2:0] y_cmp [1:0];
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|
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chain_comparator X0 ( .a(pipe_xd[3:0]), .b(addrx[3:0]), .q(x_cmp[0]));
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chain_comparator X0 ( .a(pipe_xd[3:0]), .b(addrx[3:0]), .q(x_cmp[0]));
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chain_comparator X1 ( .a(pipe_xd[7:4]), .b(addrx[7:4]), .q(x_cmp[1]));
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chain_comparator X1 ( .a(pipe_xd[7:4]), .b(addrx[7:4]), .q(x_cmp[1]));
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chain_comparator Y0 ( .a(pipe_yd[3:0]), .b(addry[3:0]), .q(y_cmp[0]));
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chain_comparator Y0 ( .a(pipe_yd[3:0]), .b(addry[3:0]), .q(y_cmp[0]));
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chain_comparator Y1 ( .a(pipe_yd[7:4]), .b(addry[7:4]), .q(y_cmp[1]));
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chain_comparator Y1 ( .a(pipe_yd[7:4]), .b(addry[7:4]), .q(y_cmp[1]));
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assign decision[0] = x_cmp[1][0] | (x_cmp[1][2]&x_cmp[0][0]); // frame x > addr x
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assign decision[0] = x_cmp[1][0] | (x_cmp[1][2]&x_cmp[0][0]); // frame x > addr x
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assign decision[1] = x_cmp[1][1] | (x_cmp[1][2]&x_cmp[0][1]); // frame x < addr x
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assign decision[1] = x_cmp[1][1] | (x_cmp[1][2]&x_cmp[0][1]); // frame x < addr x
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assign decision[2] = x_cmp[1][2] & x_cmp[0][2]; // frame x = addr x
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assign decision[2] = x_cmp[1][2] & x_cmp[0][2]; // frame x = addr x
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assign decision[3] = y_cmp[1][0] | (y_cmp[1][2]&y_cmp[0][0]); // frame y > addr y
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assign decision[3] = y_cmp[1][0] | (y_cmp[1][2]&y_cmp[0][0]); // frame y > addr y
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assign decision[4] = y_cmp[1][1] | (y_cmp[1][2]&y_cmp[0][1]); // frame y < addr y
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assign decision[4] = y_cmp[1][1] | (y_cmp[1][2]&y_cmp[0][1]); // frame y < addr y
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assign decision[5] = y_cmp[1][2] & y_cmp[0][2]; // frame y = addr y
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assign decision[5] = y_cmp[1][2] & y_cmp[0][2]; // frame y = addr y
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|
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endmodule // routing_decision
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endmodule // routing_decision
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// the 1-of-4 comparator
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// the 1-of-4 comparator
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module chain_comparator (
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module chain_comparator (
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a
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a
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,b
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,b
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,q
|
,q
|
);
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);
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|
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input [3:0] a;
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input [3:0] a;
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input [3:0] b;
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input [3:0] b;
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output [2:0] q;
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output [2:0] q;
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|
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// a > b
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// a > b
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assign q[0] = (a[3]&(|b[2:0])) | (a[2]&(|b[1:0])) | (a[1]&(|b[0:0]));
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assign q[0] = (a[3]&(|b[2:0])) | (a[2]&(|b[1:0])) | (a[1]&(|b[0:0]));
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|
|
// a < b
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// a < b
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assign q[1] = (a[2]&(|b[3:3])) | (a[1]&(|b[3:2])) | (a[0]&(|b[3:1]));
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assign q[1] = (a[2]&(|b[3:3])) | (a[1]&(|b[3:2])) | (a[0]&(|b[3:1]));
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|
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// a = b
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// a = b
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assign q[2] = (a[3]&b[3]) | (a[2]&b[2]) | (a[1]&b[1]) | (a[0]&b[0]);
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assign q[2] = (a[3]&b[3]) | (a[2]&b[2]) | (a[1]&b[1]) | (a[0]&b[0]);
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|
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endmodule // chain_comparator
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endmodule // chain_comparator
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