/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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Crossbar based SDM switch allocator
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Crossbar based SDM switch allocator
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*** SystemVerilog is used ***
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*** SystemVerilog is used ***
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References
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References
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For the detail structure, please refer to Section 6.3.1 of the thesis:
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For the detail structure, please refer to Section 6.3.1 of the thesis:
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Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.
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Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.
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History:
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History:
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28/09/2009 Initial version. <wsong83@gmail.com>
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28/09/2009 Initial version. <wsong83@gmail.com>
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25/05/2011 Clean up for opensource. <wsong83@gmail.com>
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27/05/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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module sdm_sch (/*AUTOARG*/
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module sdm_sch (/*AUTOARG*/
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// Outputs
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// Outputs
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sack, wack, nack, eack, lack, scfg, ncfg, wcfg, ecfg, lcfg,
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sack, wack, nack, eack, lack, scfg, ncfg, wcfg, ecfg, lcfg,
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// Inputs
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// Inputs
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sreq, nreq, lreq, wreq, ereq
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sreq, nreq, lreq, wreq, ereq, rst_n
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);
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);
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parameter VCN = 2; // the number of virtual circuits per port
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parameter VCN = 2; // the number of virtual circuits per port
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// income requests
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// income requests
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input [VCN-1:0][3:0] sreq, nreq, lreq;
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input [VCN-1:0][3:0] sreq, nreq, lreq;
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input [VCN-1:0][1:0] wreq, ereq;
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input [VCN-1:0][1:0] wreq, ereq;
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// ack to input buffers
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// ack to input buffers
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output [VCN-1:0] sack, wack, nack, eack, lack;
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output [VCN-1:0] sack, wack, nack, eack, lack;
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// configuration to the crossbar
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// configuration to the crossbar
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output [VCN-1:0][1:0][VCN-1:0] scfg, ncfg;
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output [VCN-1:0][1:0][VCN-1:0] scfg, ncfg;
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output [VCN-1:0][3:0][VCN-1:0] wcfg, ecfg, lcfg;
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output [VCN-1:0][3:0][VCN-1:0] wcfg, ecfg, lcfg;
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input rst_n; // active low global reset
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input rst_n; // active low global reset
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// requests to arbiters
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// requests to arbiters
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`ifndef ENABLE_MRMA
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`ifndef ENABLE_MRMA
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wire [1:0][VCN-1:0][VCN-1:0] r2s, r2n; // shuffle the incoming request signals
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wire [1:0][VCN-1:0][VCN-1:0] r2s, r2n; // shuffle the incoming request signals
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wire [3:0][VCN-1:0][VCN-1:0] r2w, r2e, r2l;
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wire [3:0][VCN-1:0][VCN-1:0] r2w, r2e, r2l;
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`else
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`else
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wire [1:0][VCN-1:0] r2s, r2n; // shuffle the incoming request signals
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wire [1:0][VCN-1:0] r2s, r2n; // shuffle the incoming request signals
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wire [3:0][VCN-1:0] r2w, r2e, r2l;
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wire [3:0][VCN-1:0] r2w, r2e, r2l;
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`endif
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`endif
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// ack from arbiters
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// ack from arbiters
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wire [VCN-1:0][3:0] a2s, a2n, a2l;
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wire [VCN-1:0][3:0] a2s, a2n, a2l;
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wire [VCN-1:0][1:0] a2w, a2e;
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wire [VCN-1:0][1:0] a2w, a2e;
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// ack of the arbiters
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// ack of the arbiters
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wire [1:0][VCN-1:0] r2sa, r2na;
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wire [1:0][VCN-1:0] r2sa, r2na;
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wire [3:0][VCN-1:0] r2wa, r2ea, r2la;
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wire [3:0][VCN-1:0] r2wa, r2ea, r2la;
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`ifdef ENABLE_MRMA
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`ifdef ENABLE_MRMA
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wire [VCN:0] OPrst_n; // the buffered resets to avoid metastability
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wire [VCN:0] OPrst_n; // the buffered resets to avoid metastability
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wire [VCN-1:0] SOPrdy, SOPblk; // OP ready and blocked status
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wire [VCN-1:0] SOPrdy, SOPblk; // OP ready and blocked status
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wire [VCN-1:0] WOPrdy, WOPblk; // OP ready and blocked status
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wire [VCN-1:0] WOPrdy, WOPblk; // OP ready and blocked status
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wire [VCN-1:0] NOPrdy, NOPblk; // OP ready and blocked status
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wire [VCN-1:0] NOPrdy, NOPblk; // OP ready and blocked status
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wire [VCN-1:0] EOPrdy, EOPblk; // OP ready and blocked status
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wire [VCN-1:0] EOPrdy, EOPblk; // OP ready and blocked status
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wire [VCN-1:0] LOPrdy, LOPblk; // OP ready and blocked status
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wire [VCN-1:0] LOPrdy, LOPblk; // OP ready and blocked status
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`endif
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`endif
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genvar i,j;
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genvar i,j;
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// wire shuffle
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// wire shuffle
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generate for(i=0; i<VCN; i++) begin: SHUF
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generate for(i=0; i<VCN; i++) begin: SHUF
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`ifndef ENABLE_MRMA
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`ifndef ENABLE_MRMA
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for(j=0; j<VCN; j++) begin: CO
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for(j=0; j<VCN; j++) begin: CO
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assign r2s[0][i][j] = nreq[i][0];
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assign r2s[0][i][j] = nreq[i][0];
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assign r2s[1][i][j] = lreq[i][0];
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assign r2s[1][i][j] = lreq[i][0];
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assign r2w[0][i][j] = sreq[i][0];
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assign r2w[0][i][j] = sreq[i][0];
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assign r2w[1][i][j] = nreq[i][1];
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assign r2w[1][i][j] = nreq[i][1];
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assign r2w[2][i][j] = ereq[i][0];
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assign r2w[2][i][j] = ereq[i][0];
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assign r2w[3][i][j] = lreq[i][1];
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assign r2w[3][i][j] = lreq[i][1];
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assign r2n[0][i][j] = sreq[i][1];
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assign r2n[0][i][j] = sreq[i][1];
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assign r2n[1][i][j] = lreq[i][2];
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assign r2n[1][i][j] = lreq[i][2];
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assign r2e[0][i][j] = sreq[i][2];
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assign r2e[0][i][j] = sreq[i][2];
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assign r2e[1][i][j] = wreq[i][0];
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assign r2e[1][i][j] = wreq[i][0];
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assign r2e[2][i][j] = nreq[i][2];
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assign r2e[2][i][j] = nreq[i][2];
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assign r2e[3][i][j] = lreq[i][3];
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assign r2e[3][i][j] = lreq[i][3];
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assign r2l[0][i][j] = sreq[i][3];
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assign r2l[0][i][j] = sreq[i][3];
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assign r2l[1][i][j] = wreq[i][1];
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assign r2l[1][i][j] = wreq[i][1];
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assign r2l[2][i][j] = nreq[i][3];
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assign r2l[2][i][j] = nreq[i][3];
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assign r2l[3][i][j] = ereq[i][1];
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assign r2l[3][i][j] = ereq[i][1];
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end // block: CO
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end // block: CO
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`else // !`ifndef ENABLE_MRMA
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`else // !`ifndef ENABLE_MRMA
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assign r2s[0][i] = nreq[i][0];
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assign r2s[0][i] = nreq[i][0];
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assign r2s[1][i] = lreq[i][0];
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assign r2s[1][i] = lreq[i][0];
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assign r2w[0][i] = sreq[i][0];
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assign r2w[0][i] = sreq[i][0];
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assign r2w[1][i] = nreq[i][1];
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assign r2w[1][i] = nreq[i][1];
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assign r2w[2][i] = ereq[i][0];
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assign r2w[2][i] = ereq[i][0];
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assign r2w[3][i] = lreq[i][1];
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assign r2w[3][i] = lreq[i][1];
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assign r2n[0][i] = sreq[i][1];
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assign r2n[0][i] = sreq[i][1];
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assign r2n[1][i] = lreq[i][2];
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assign r2n[1][i] = lreq[i][2];
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assign r2e[0][i] = sreq[i][2];
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assign r2e[0][i] = sreq[i][2];
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assign r2e[1][i] = wreq[i][0];
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assign r2e[1][i] = wreq[i][0];
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assign r2e[2][i] = nreq[i][2];
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assign r2e[2][i] = nreq[i][2];
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assign r2e[3][i] = lreq[i][3];
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assign r2e[3][i] = lreq[i][3];
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assign r2l[0][i] = sreq[i][3];
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assign r2l[0][i] = sreq[i][3];
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assign r2l[1][i] = wreq[i][1];
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assign r2l[1][i] = wreq[i][1];
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assign r2l[2][i] = nreq[i][3];
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assign r2l[2][i] = nreq[i][3];
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assign r2l[3][i] = ereq[i][1];
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assign r2l[3][i] = ereq[i][1];
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`endif // !`ifndef ENABLE_MRMA
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`endif // !`ifndef ENABLE_MRMA
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assign a2s[i][0] = r2wa[0][i];
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assign a2s[i][0] = r2wa[0][i];
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assign a2s[i][1] = r2na[0][i];
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assign a2s[i][1] = r2na[0][i];
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assign a2s[i][2] = r2ea[0][i];
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assign a2s[i][2] = r2ea[0][i];
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assign a2s[i][3] = r2la[0][i];
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assign a2s[i][3] = r2la[0][i];
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assign a2w[i][0] = r2ea[1][i];
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assign a2w[i][0] = r2ea[1][i];
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assign a2w[i][1] = r2la[1][i];
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assign a2w[i][1] = r2la[1][i];
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assign a2n[i][0] = r2sa[0][i];
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assign a2n[i][0] = r2sa[0][i];
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assign a2n[i][1] = r2wa[1][i];
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assign a2n[i][1] = r2wa[1][i];
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assign a2n[i][2] = r2ea[2][i];
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assign a2n[i][2] = r2ea[2][i];
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assign a2n[i][3] = r2la[2][i];
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assign a2n[i][3] = r2la[2][i];
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assign a2e[i][0] = r2wa[2][i];
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assign a2e[i][0] = r2wa[2][i];
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assign a2e[i][1] = r2la[3][i];
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assign a2e[i][1] = r2la[3][i];
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assign a2l[i][0] = r2sa[1][i];
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assign a2l[i][0] = r2sa[1][i];
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assign a2l[i][1] = r2wa[3][i];
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assign a2l[i][1] = r2wa[3][i];
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assign a2l[i][2] = r2na[1][i];
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assign a2l[i][2] = r2na[1][i];
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assign a2l[i][3] = r2ea[3][i];
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assign a2l[i][3] = r2ea[3][i];
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assign sack[i] = |a2s[i];
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assign sack[i] = |a2s[i];
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assign wack[i] = |a2w[i];
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assign wack[i] = |a2w[i];
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assign nack[i] = |a2n[i];
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assign nack[i] = |a2n[i];
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assign eack[i] = |a2e[i];
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assign eack[i] = |a2e[i];
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assign lack[i] = |a2l[i];
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assign lack[i] = |a2l[i];
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end // block: SHUF
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end // block: SHUF
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endgenerate
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endgenerate
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// output port arbiter/allocators
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// output port arbiter/allocators
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`ifndef ENABLE_MRMA
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`ifndef ENABLE_MRMA
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mnma #(.N(2*VCN), .M(VCN))
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mnma #(.N(2*VCN), .M(VCN))
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SCBA (
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SCBA (
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.r ( r2s ),
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.r ( r2s ),
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.ra ( r2sa ),
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.ra ( r2sa ),
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.cfg ( scfg )
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.cfg ( scfg )
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);
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);
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mnma #(.N(4*VCN), .M(VCN))
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mnma #(.N(4*VCN), .M(VCN))
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WCBA (
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WCBA (
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.r ( r2w ),
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.r ( r2w ),
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.ra ( r2wa ),
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.ra ( r2wa ),
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.cfg ( wcfg )
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.cfg ( wcfg )
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);
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);
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mnma #(.N(2*VCN), .M(VCN))
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mnma #(.N(2*VCN), .M(VCN))
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NCBA (
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NCBA (
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.r ( r2n ),
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.r ( r2n ),
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.ra ( r2na ),
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.ra ( r2na ),
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.cfg ( ncfg )
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.cfg ( ncfg )
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);
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);
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mnma #(.N(4*VCN), .M(VCN))
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mnma #(.N(4*VCN), .M(VCN))
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ECBA (
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ECBA (
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.r ( r2e ),
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.r ( r2e ),
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.ra ( r2ea ),
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.ra ( r2ea ),
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.cfg ( ecfg )
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.cfg ( ecfg )
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);
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);
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mnma #(.N(4*VCN), .M(VCN))
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mnma #(.N(4*VCN), .M(VCN))
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LCBA (
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LCBA (
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.r ( r2l ),
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.r ( r2l ),
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.ra ( r2la ),
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.ra ( r2la ),
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.cfg ( lcfg )
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.cfg ( lcfg )
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);
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);
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`else // !`ifndef ENABLE_MRMA
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`else // !`ifndef ENABLE_MRMA
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mrma #(.N(2*VCN), .M(VCN))
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mrma #(.N(2*VCN), .M(VCN))
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SCBA (
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SCBA (
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.ca ( r2sa ),
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.ca ( r2sa ),
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.ra ( SOPblk ),
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.ra ( SOPblk ),
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.cfg ( scfg ),
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.cfg ( scfg ),
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.c ( r2s ),
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.c ( r2s ),
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.r ( SOPrdy ),
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.r ( SOPrdy ),
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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mrma #(.N(4*VCN), .M(VCN))
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mrma #(.N(4*VCN), .M(VCN))
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WCBA (
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WCBA (
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.ca ( r2wa ),
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.ca ( r2wa ),
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.ra ( WOPblk ),
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.ra ( WOPblk ),
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.cfg ( wcfg ),
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.cfg ( wcfg ),
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.c ( r2w ),
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.c ( r2w ),
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.r ( WOPrdy ),
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.r ( WOPrdy ),
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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mrma #(.N(2*VCN), .M(VCN))
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mrma #(.N(2*VCN), .M(VCN))
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NCBA (
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NCBA (
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.ca ( r2na ),
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.ca ( r2na ),
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.ra ( NOPblk ),
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.ra ( NOPblk ),
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.cfg ( ncfg ),
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.cfg ( ncfg ),
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.c ( r2n ),
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.c ( r2n ),
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.r ( NOPrdy ),
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.r ( NOPrdy ),
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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mrma #(.N(4*VCN), .M(VCN))
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mrma #(.N(4*VCN), .M(VCN))
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ECBA (
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ECBA (
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.ca ( r2ea ),
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.ca ( r2ea ),
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.ra ( EOPblk ),
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.ra ( EOPblk ),
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.cfg ( ecfg ),
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.cfg ( ecfg ),
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.c ( r2e ),
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.c ( r2e ),
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.r ( EOPrdy ),
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.r ( EOPrdy ),
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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mrma #(.N(4*VCN), .M(VCN))
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mrma #(.N(4*VCN), .M(VCN))
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LCBA (
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LCBA (
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.ca ( r2la ),
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.ca ( r2la ),
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.ra ( LOPblk ),
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.ra ( LOPblk ),
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.cfg ( lcfg ),
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.cfg ( lcfg ),
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.c ( r2l ),
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.c ( r2l ),
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.r ( LOPrdy ),
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.r ( LOPrdy ),
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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generate
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generate
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for(i=0; i<VCN; i++) begin: OPC
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for(i=0; i<VCN; i++) begin: OPC
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delay DLY ( .q(OPrst_n[i+1]), .a(OPrst_n[i])); // dont touch
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delay DLY ( .q(OPrst_n[i+1]), .a(OPrst_n[i])); // dont touch
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assign SOPrdy[i] = (~SOPblk[i])&SOPrst_n[i+1];
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assign SOPrdy[i] = (~SOPblk[i])&OPrst_n[i+1];
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assign WOPrdy[i] = (~WOPblk[i])&WOPrst_n[i+1];
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assign WOPrdy[i] = (~WOPblk[i])&OPrst_n[i+1];
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assign NOPrdy[i] = (~NOPblk[i])&NOPrst_n[i+1];
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assign NOPrdy[i] = (~NOPblk[i])&OPrst_n[i+1];
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assign EOPrdy[i] = (~EOPblk[i])&EOPrst_n[i+1];
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assign EOPrdy[i] = (~EOPblk[i])&OPrst_n[i+1];
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assign LOPrdy[i] = (~LOPblk[i])&LOPrst_n[i+1];
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assign LOPrdy[i] = (~LOPblk[i])&OPrst_n[i+1];
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end
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end
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endgenerate
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endgenerate
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assign OPrst_n[0] = rst_n;
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`endif // !`ifndef ENABLE_MRMA
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`endif // !`ifndef ENABLE_MRMA
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endmodule // sdm_sch
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endmodule // sdm_sch
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