/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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The SystemC module of network node including the processing element and the network interface.
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The SystemC module of network node including the processing element and the network interface.
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Currently the transmission FIFO is 500 frame deep.
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Currently the transmission FIFO is 500 frame deep.
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History:
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History:
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26/02/2011 Initial version. <wsong83@gmail.com>
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26/02/2011 Initial version. <wsong83@gmail.com>
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30/05/2011 Clean up for opensource. <wsong83@gmail.com>
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30/05/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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#ifndef NETNODE_H_
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#ifndef NETNODE_H_
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#define NETNODE_H_
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#define NETNODE_H_
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#include "define.h"
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#include "define.h"
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#include <systemc.h>
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#include <systemc.h>
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#include "ni.h"
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#include "ni.h"
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#include "procelem.h"
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#include "procelem.h"
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#include "rtdriver.h"
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#include "rtdriver.h"
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class NetNode : public sc_module {
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class NetNode : public sc_module {
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public:
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public:
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RTDriver * LIOD [SubChN]; /* driving and convert I/O to/from router local port */
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RTDriver * LIOD [SubChN]; /* driving and convert I/O to/from router local port */
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Network_Adapter * NI; /* network interface */
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Network_Adapter * NI; /* network interface */
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ProcElem * PE; /* processor element */
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ProcElem * PE; /* processor element */
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#ifdef ENABLE_CHANNEL_CLISING
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#ifdef ENABLE_CHANNEL_CLISING
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sc_signal<sc_lv<ChBW*4> > rtia [SubChN]; /* input ack to router */
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sc_signal<sc_lv<ChBW*4> > rtia [SubChN]; /* input ack to router */
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sc_signal<sc_lv<ChBW*4> > rtod4 [SubChN]; /* output eof to router */
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sc_signal<sc_lv<ChBW*4> > rtod4 [SubChN]; /* output eof to router */
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sc_signal<sc_lv<ChBW*4> > rtoa [SubChN]; /* output ack from router */
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sc_signal<sc_lv<ChBW*4> > rtoa [SubChN]; /* output ack from router */
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sc_signal<sc_lv<ChBW*4> > rtid4 [SubChN]; /* input data from router */
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sc_signal<sc_lv<ChBW*4> > rtid4 [SubChN]; /* input data from router */
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sc_in<sc_lv<SubChN*ChBW*4> > dia; /* input ack, undivided */
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sc_in<sc_lv<SubChN*ChBW*4> > dia; /* input ack, undivided */
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sc_in<sc_lv<SubChN*ChBW*4> > do4; /* output eof, undivided */
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sc_in<sc_lv<SubChN*ChBW*4> > do4; /* output eof, undivided */
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sc_out<sc_lv<SubChN*ChBW*4> > doa; /* output ack, undivided */
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sc_out<sc_lv<SubChN*ChBW*4> > doa; /* output ack, undivided */
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sc_out<sc_lv<SubChN*ChBW*4> > di4; /* input eof, undivided */
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sc_out<sc_lv<SubChN*ChBW*4> > di4; /* input eof, undivided */
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#else
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#else
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sc_signal<sc_logic > rtia [SubChN]; /* input ack to router */
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sc_signal<sc_logic > rtia [SubChN]; /* input ack to router */
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sc_signal<sc_logic > rtod4 [SubChN]; /* output data to router */
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sc_signal<sc_logic > rtod4 [SubChN]; /* output data to router */
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sc_signal<sc_logic > rtoa [SubChN]; /* output ack from router */
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sc_signal<sc_logic > rtoa [SubChN]; /* output ack from router */
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sc_signal<sc_logic > rtid4 [SubChN]; /* input eof from router */
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sc_signal<sc_logic > rtid4 [SubChN]; /* input eof from router */
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sc_in<sc_lv<SubChN> > dia; /* input ack, undivided */
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sc_in<sc_lv<SubChN> > dia; /* input ack, undivided */
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sc_in<sc_lv<SubChN> > do4; /* output eof, undivided */
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sc_in<sc_lv<SubChN> > do4; /* output eof, undivided */
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sc_out<sc_lv<SubChN> > doa; /* output ack, undivided */
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sc_out<sc_lv<SubChN> > doa; /* output ack, undivided */
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sc_out<sc_lv<SubChN> > di4; /* input eof, undivided */
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sc_out<sc_lv<SubChN> > di4; /* input eof, undivided */
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#endif
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#endif
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sc_signal<sc_lv<ChBW*4 > > rtod [SubChN][4]; /* output data to router */
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sc_signal<sc_lv<ChBW*4 > > rtod [SubChN][4]; /* output data to router */
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sc_signal<sc_lv<ChBW*4 > > rtid [SubChN][4]; /* input data from router */
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sc_signal<sc_lv<ChBW*4 > > rtid [SubChN][4]; /* input data from router */
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sc_in<sc_lv<SubChN*ChBW*4 > > do0; /* output d0, undivided */
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sc_in<sc_lv<SubChN*ChBW*4 > > do0; /* output d0, undivided */
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sc_in<sc_lv<SubChN*ChBW*4 > > do1;
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sc_in<sc_lv<SubChN*ChBW*4 > > do1;
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sc_in<sc_lv<SubChN*ChBW*4 > > do2;
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sc_in<sc_lv<SubChN*ChBW*4 > > do2;
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sc_in<sc_lv<SubChN*ChBW*4 > > do3;
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sc_in<sc_lv<SubChN*ChBW*4 > > do3;
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sc_out<sc_lv<SubChN*ChBW*4 > > di0; /* input data, undivided */
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sc_out<sc_lv<SubChN*ChBW*4 > > di0; /* input data, undivided */
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sc_out<sc_lv<SubChN*ChBW*4 > > di1;
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sc_out<sc_lv<SubChN*ChBW*4 > > di1;
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sc_out<sc_lv<SubChN*ChBW*4 > > di2;
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sc_out<sc_lv<SubChN*ChBW*4 > > di2;
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sc_out<sc_lv<SubChN*ChBW*4 > > di3;
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sc_out<sc_lv<SubChN*ChBW*4 > > di3;
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sc_in<sc_logic > rst_n; /* global reste, from the verilog top level */
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sc_in<sc_logic > rst_n; /* global reste, from the verilog top level */
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// signals between IOD and NI
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// signals between IOD and NI
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sc_fifo<pdu_flit<ChBW> > * NI2P [SubChN]; /* flit fifo, from NI to IO driver */
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sc_fifo<pdu_flit<ChBW> > * NI2P [SubChN]; /* flit fifo, from NI to IO driver */
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sc_fifo<pdu_flit<ChBW> > * P2NI [SubChN]; /* flit fifo, from IO driver to NI */
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sc_fifo<pdu_flit<ChBW> > * P2NI [SubChN]; /* flit fifo, from IO driver to NI */
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// signals between NI and FG/FS
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// signals between NI and FG/FS
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sc_fifo<pdu_frame<ChBW> > * FIQ; /* the frame fifo, from PE to NI */
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sc_fifo<pdu_frame<ChBW> > * FIQ; /* the frame fifo, from PE to NI */
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sc_fifo<pdu_frame<ChBW> > * FOQ; /* the frame fifo, from NI to PE */
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sc_fifo<pdu_frame<ChBW> > * FOQ; /* the frame fifo, from NI to PE */
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sc_signal<bool> brst_n; /* the reset in the SystemC modules */
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sc_signal<bool> brst_n; /* the reset in the SystemC modules */
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int x, y; /* private local address */
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int x, y; /* private local address */
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SC_CTOR(NetNode)
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SC_CTOR(NetNode)
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: dia("dia"), do4("do4"), doa("doa"), di4("di4"),
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: dia("dia"), do4("do4"), doa("doa"), di4("di4"),
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do0("do0"), do1("do1"), do2("do2"), do3("do3"),
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do0("do0"), do1("do1"), do2("do2"), do3("do3"),
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di0("di0"), di1("di1"), di2("di2"), di3("di3"),
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di0("di0"), di1("di1"), di2("di2"), di3("di3"),
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rst_n("rst_n")
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rst_n("rst_n")
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{
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{
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// dynamically get the parameters from Verilog test bench
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// dynamically get the parameters from Verilog test bench
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ncsc_get_param("x", x);
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ncsc_get_param("x", x);
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ncsc_get_param("y", y);
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ncsc_get_param("y", y);
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// initialization
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// initialization
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NI = new Network_Adapter("NI", x, y);
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NI = new Network_Adapter("NI", x, y);
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PE = new ProcElem("PE", x, y);
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PE = new ProcElem("PE", x, y);
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FIQ = new sc_fifo<pdu_frame<ChBW> >(500); /* currently the fifo from PE is 500 frame deep */
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FIQ = new sc_fifo<pdu_frame<ChBW> >(500); /* currently the fifo from PE is 500 frame deep */
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FOQ = new sc_fifo<pdu_frame<ChBW> >(1);
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FOQ = new sc_fifo<pdu_frame<ChBW> >(1);
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for(unsigned int j=0; j<SubChN; j++) {
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for(unsigned int j=0; j<SubChN; j++) {
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LIOD[j] = new RTDriver("LIOD");
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LIOD[j] = new RTDriver("LIOD");
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NI2P[j] = new sc_fifo<pdu_flit<ChBW> >(1);
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NI2P[j] = new sc_fifo<pdu_flit<ChBW> >(1);
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P2NI[j] = new sc_fifo<pdu_flit<ChBW> >(1);
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P2NI[j] = new sc_fifo<pdu_flit<ChBW> >(1);
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}
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}
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// connections
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// connections
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for(unsigned int j=0; j<SubChN; j++) {
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for(unsigned int j=0; j<SubChN; j++) {
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LIOD[j]->NI2P(*NI2P[j]);
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LIOD[j]->NI2P(*NI2P[j]);
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LIOD[j]->P2NI(*P2NI[j]);
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LIOD[j]->P2NI(*P2NI[j]);
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for(unsigned int k=0; k<4; k++) {
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for(unsigned int k=0; k<4; k++) {
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LIOD[j]->rtid[k](rtid[j][k]);
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LIOD[j]->rtid[k](rtid[j][k]);
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LIOD[j]->rtod[k](rtod[j][k]);
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LIOD[j]->rtod[k](rtod[j][k]);
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}
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}
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LIOD[j]->rtia(rtia[j]);
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LIOD[j]->rtia(rtia[j]);
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LIOD[j]->rtid4(rtid4[j]);
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LIOD[j]->rtid4(rtid4[j]);
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LIOD[j]->rtoa(rtoa[j]);
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LIOD[j]->rtoa(rtoa[j]);
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LIOD[j]->rtod4(rtod4[j]);
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LIOD[j]->rtod4(rtod4[j]);
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}
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}
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NI->frame_in(*FIQ);
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NI->frame_in(*FIQ);
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NI->frame_out(*FOQ);
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NI->frame_out(*FOQ);
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for(unsigned int j=0; j<SubChN; j++) {
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for(unsigned int j=0; j<SubChN; j++) {
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NI->IP[j](*P2NI[j]);
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NI->IP[j](*P2NI[j]);
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NI->OP[j](*NI2P[j]);
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NI->OP[j](*NI2P[j]);
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}
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}
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PE->rst_n(brst_n);
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PE->rst_n(brst_n);
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PE->Fout(*FIQ);
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PE->Fout(*FIQ);
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PE->Fin(*FOQ);
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PE->Fin(*FOQ);
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brst_n.write(false);
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brst_n.write(false);
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SC_METHOD(rst_proc);
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SC_METHOD(rst_proc);
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sensitive << rst_n;
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sensitive << rst_n;
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sc_spawn_options opt_inp;
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sc_spawn_options opt_inp;
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opt_inp.spawn_method();
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opt_inp.spawn_method();
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for(unsigned int j=0; j<SubChN; j++) {
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for(unsigned int j=0; j<SubChN; j++) {
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opt_inp.set_sensitivity(&rtid[j][0]);
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opt_inp.set_sensitivity(&rtid[j][0]);
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opt_inp.set_sensitivity(&rtid[j][1]);
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opt_inp.set_sensitivity(&rtid[j][1]);
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opt_inp.set_sensitivity(&rtid[j][2]);
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opt_inp.set_sensitivity(&rtid[j][2]);
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opt_inp.set_sensitivity(&rtid[j][3]);
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opt_inp.set_sensitivity(&rtid[j][3]);
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opt_inp.set_sensitivity(&rtid4[j]);
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opt_inp.set_sensitivity(&rtid4[j]);
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}
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}
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opt_inp.set_sensitivity(&dia);
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opt_inp.set_sensitivity(&dia);
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sc_spawn(sc_bind(&NetNode::VC_inp, this), NULL, &opt_inp);
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sc_spawn(sc_bind(&NetNode::VC_inp, this), NULL, &opt_inp);
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sc_spawn_options opt_outp;
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sc_spawn_options opt_outp;
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opt_outp.spawn_method();
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opt_outp.spawn_method();
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for(unsigned int j=0; j<SubChN; j++) {
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for(unsigned int j=0; j<SubChN; j++) {
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opt_outp.set_sensitivity(&rtoa[j]);
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opt_outp.set_sensitivity(&rtoa[j]);
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}
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}
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opt_outp.set_sensitivity(&do0);
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opt_outp.set_sensitivity(&do0);
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opt_outp.set_sensitivity(&do1);
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opt_outp.set_sensitivity(&do1);
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opt_outp.set_sensitivity(&do2);
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opt_outp.set_sensitivity(&do2);
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opt_outp.set_sensitivity(&do3);
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opt_outp.set_sensitivity(&do3);
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opt_outp.set_sensitivity(&do4);
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opt_outp.set_sensitivity(&do4);
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sc_spawn(sc_bind(&NetNode::VC_outp, this), NULL, &opt_outp);
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sc_spawn(sc_bind(&NetNode::VC_outp, this), NULL, &opt_outp);
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}
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}
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// thread to divide the input buses according to virtual circuits
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// thread to divide the input buses according to virtual circuits
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void VC_inp() {
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void VC_inp() {
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sc_lv<SubChN*ChBW*4> md[4];
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sc_lv<SubChN*ChBW*4> md[4];
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#ifdef ENABLE_CHANNEL_CLISING
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#ifdef ENABLE_CHANNEL_CLISING
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sc_lv<SubChN*ChBW*4> md4;
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sc_lv<SubChN*ChBW*4> md4;
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sc_lv<SubChN*ChBW*4> mda;
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sc_lv<SubChN*ChBW*4> mda;
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#else
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#else
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sc_lv<SubChN> md4;
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sc_lv<SubChN> md4;
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sc_lv<SubChN> mda;
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sc_lv<SubChN> mda;
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#endif
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#endif
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mda = dia.read();
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mda = dia.read();
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for(unsigned int i=0; i<SubChN; i++) {
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for(unsigned int i=0; i<SubChN; i++) {
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#ifdef ENABLE_CHANNEL_CLISING
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#ifdef ENABLE_CHANNEL_CLISING
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rtia[i].write(mda(ChBW*4*(i+1)-1, ChBW*4*i));
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rtia[i].write(mda(ChBW*4*(i+1)-1, ChBW*4*i));
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md4(ChBW*4*(i+1)-1, ChBW*4*i) = rtid4[i].read();
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md4(ChBW*4*(i+1)-1, ChBW*4*i) = rtid4[i].read();
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#else
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#else
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rtia[i].write(mda[i]);
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rtia[i].write(mda[i]);
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md4[i] = rtid4[i].read();
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md4[i] = rtid4[i].read();
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#endif
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#endif
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md[0](ChBW*4*(i+1)-1, ChBW*4*i) = rtid[i][0].read();
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md[0](ChBW*4*(i+1)-1, ChBW*4*i) = rtid[i][0].read();
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md[1](ChBW*4*(i+1)-1, ChBW*4*i) = rtid[i][1].read();
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md[1](ChBW*4*(i+1)-1, ChBW*4*i) = rtid[i][1].read();
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md[2](ChBW*4*(i+1)-1, ChBW*4*i) = rtid[i][2].read();
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md[2](ChBW*4*(i+1)-1, ChBW*4*i) = rtid[i][2].read();
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md[3](ChBW*4*(i+1)-1, ChBW*4*i) = rtid[i][3].read();
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md[3](ChBW*4*(i+1)-1, ChBW*4*i) = rtid[i][3].read();
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}
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}
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di0.write(md[0]);
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di0.write(md[0]);
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di1.write(md[1]);
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di1.write(md[1]);
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di2.write(md[2]);
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di2.write(md[2]);
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di3.write(md[3]);
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di3.write(md[3]);
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di4.write(md4);
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di4.write(md4);
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}
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}
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// thread to combine the buses according to virtual circuits
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// thread to combine the buses according to virtual circuits
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void VC_outp() {
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void VC_outp() {
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sc_lv<SubChN*ChBW*4> md[4];
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sc_lv<SubChN*ChBW*4> md[4];
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#ifdef ENABLE_CHANNEL_CLISING
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#ifdef ENABLE_CHANNEL_CLISING
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sc_lv<SubChN*ChBW*4> md4;
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sc_lv<SubChN*ChBW*4> md4;
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sc_lv<SubChN*ChBW*4> mda;
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sc_lv<SubChN*ChBW*4> mda;
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#else
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#else
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sc_lv<SubChN> md4;
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sc_lv<SubChN> md4;
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sc_lv<SubChN> mda;
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sc_lv<SubChN> mda;
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#endif
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#endif
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md[0] = do0.read();
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md[0] = do0.read();
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md[1] = do1.read();
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md[1] = do1.read();
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md[2] = do2.read();
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md[2] = do2.read();
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md[3] = do3.read();
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md[3] = do3.read();
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md4 = do4.read();
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md4 = do4.read();
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for(unsigned int i=0; i<SubChN; i++) {
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for(unsigned int i=0; i<SubChN; i++) {
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#ifdef ENABLE_CHANNEL_CLISING
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#ifdef ENABLE_CHANNEL_CLISING
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mda(ChBW*4*(i+1)-1, ChBW*4*i) = rtoa[i].read();
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mda(ChBW*4*(i+1)-1, ChBW*4*i) = rtoa[i].read();
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rtod4[i].write(md4(ChBW*4*(i+1)-1, ChBW*4*i));
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rtod4[i].write(md4(ChBW*4*(i+1)-1, ChBW*4*i));
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#else
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#else
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mda[i] = rtoa[i].read();
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mda[i] = rtoa[i].read();
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rtod4[i].write(md4[i]);
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rtod4[i].write(md4[i]);
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#endif
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#endif
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rtod[i][0].write(md[0](ChBW*4*(i+1)-1, ChBW*4*i));
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rtod[i][0].write(md[0](ChBW*4*(i+1)-1, ChBW*4*i));
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rtod[i][1].write(md[1](ChBW*4*(i+1)-1, ChBW*4*i));
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rtod[i][1].write(md[1](ChBW*4*(i+1)-1, ChBW*4*i));
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rtod[i][2].write(md[2](ChBW*4*(i+1)-1, ChBW*4*i));
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rtod[i][2].write(md[2](ChBW*4*(i+1)-1, ChBW*4*i));
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rtod[i][3].write(md[3](ChBW*4*(i+1)-1, ChBW*4*i));
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rtod[i][3].write(md[3](ChBW*4*(i+1)-1, ChBW*4*i));
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}
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}
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doa.write(mda);
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doa.write(mda);
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}
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}
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// generate the reset for SystemC modules
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// generate the reset for SystemC modules
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void rst_proc() {
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void rst_proc() {
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bool mrst_n;
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bool mrst_n;
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mrst_n = rst_n.read().is_01() ? rst_n.read().to_bool() : false;
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mrst_n = rst_n.read().is_01() ? rst_n.read().to_bool() : false;
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brst_n.write(mrst_n);
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brst_n.write(mrst_n);
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}
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}
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};
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};
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#endif
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#endif
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