/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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The mesh network for simulation.
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The mesh network for simulation.
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History:
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History:
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03/03/2011 Initial version. <wsong83@gmail.com>
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03/03/2011 Initial version. <wsong83@gmail.com>
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30/05/2011 Clean up for opensource. <wsong83@gmail.com>
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30/05/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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module noc_top(/*AUTOARG*/
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module noc_top(/*AUTOARG*/
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// Inputs
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// Inputs
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rst_n
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rst_n
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);
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);
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input rst_n;
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input rst_n;
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parameter DW = 32;
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parameter DW = 32;
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parameter VCN = 1;
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parameter VCN = 1;
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parameter DIMX = 8;
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parameter DIMX = 8;
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parameter DIMY = 8;
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parameter DIMY = 8;
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parameter SCN = DW/2;
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parameter SCN = DW/2;
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wire [DIMX-1:0][DIMY-1:0][3:0][VCN*SCN-1:0] di0, di1, di2, di3;
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wire [DIMX-1:0][DIMY-1:0][3:0][VCN*SCN-1:0] di0, di1, di2, di3;
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wire [DIMX-1:0][DIMY-1:0][3:0][VCN*SCN-1:0] do0, do1, do2, do3;
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wire [DIMX-1:0][DIMY-1:0][3:0][VCN*SCN-1:0] do0, do1, do2, do3;
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [DIMX-1:0][DIMY-1:0][3:0][VCN*SCN-1:0] di4, dia;
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wire [DIMX-1:0][DIMY-1:0][3:0][VCN*SCN-1:0] di4, dia;
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wire [DIMX-1:0][DIMY-1:0][3:0][VCN*SCN-1:0] do4, doa;
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wire [DIMX-1:0][DIMY-1:0][3:0][VCN*SCN-1:0] do4, doa;
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`else
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`else
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wire [DIMX-1:0][DIMY-1:0][3:0][VCN-1:0] di4, dia;
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wire [DIMX-1:0][DIMY-1:0][3:0][VCN-1:0] di4, dia;
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wire [DIMX-1:0][DIMY-1:0][3:0][VCN-1:0] do4, doa;
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wire [DIMX-1:0][DIMY-1:0][3:0][VCN-1:0] do4, doa;
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`endif
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`endif
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genvar x, y;
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genvar x, y;
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generate for(x=0; x<DIMX; x++) begin: DX
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generate for(x=0; x<DIMX; x++) begin: DX
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for(y=0; y<DIMY; y++) begin: DY
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for(y=0; y<DIMY; y++) begin: DY
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node_top #(.DW(DW), .VCN(VCN), .x(x), .y(y))
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node_top #(.DW(DW), .VCN(VCN), .x(x), .y(y))
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NN (
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NN (
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.si0 (di0[x][y][0]), .si1 (di1[x][y][0]), .si2 (di2[x][y][0]), .si3 (di3[x][y][0]), .si4 (di4[x][y][0]), .sia (dia[x][y][0]),
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.si0 (di0[x][y][0]), .si1 (di1[x][y][0]), .si2 (di2[x][y][0]), .si3 (di3[x][y][0]), .si4 (di4[x][y][0]), .sia (dia[x][y][0]),
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.wi0 (di0[x][y][1]), .wi1 (di1[x][y][1]), .wi2 (di2[x][y][1]), .wi3 (di3[x][y][1]), .wi4 (di4[x][y][1]), .wia (dia[x][y][1]),
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.wi0 (di0[x][y][1]), .wi1 (di1[x][y][1]), .wi2 (di2[x][y][1]), .wi3 (di3[x][y][1]), .wi4 (di4[x][y][1]), .wia (dia[x][y][1]),
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.ni0 (di0[x][y][2]), .ni1 (di1[x][y][2]), .ni2 (di2[x][y][2]), .ni3 (di3[x][y][2]), .ni4 (di4[x][y][2]), .nia (dia[x][y][2]),
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.ni0 (di0[x][y][2]), .ni1 (di1[x][y][2]), .ni2 (di2[x][y][2]), .ni3 (di3[x][y][2]), .ni4 (di4[x][y][2]), .nia (dia[x][y][2]),
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.ei0 (di0[x][y][3]), .ei1 (di1[x][y][3]), .ei2 (di2[x][y][3]), .ei3 (di3[x][y][3]), .ei4 (di4[x][y][3]), .eia (dia[x][y][3]),
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.ei0 (di0[x][y][3]), .ei1 (di1[x][y][3]), .ei2 (di2[x][y][3]), .ei3 (di3[x][y][3]), .ei4 (di4[x][y][3]), .eia (dia[x][y][3]),
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.so0 (do0[x][y][0]), .so1 (do1[x][y][0]), .so2 (do2[x][y][0]), .so3 (do3[x][y][0]), .so4 (do4[x][y][0]), .soa (doa[x][y][0]),
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.so0 (do0[x][y][0]), .so1 (do1[x][y][0]), .so2 (do2[x][y][0]), .so3 (do3[x][y][0]), .so4 (do4[x][y][0]), .soa (doa[x][y][0]),
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.wo0 (do0[x][y][1]), .wo1 (do1[x][y][1]), .wo2 (do2[x][y][1]), .wo3 (do3[x][y][1]), .wo4 (do4[x][y][1]), .woa (doa[x][y][1]),
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.wo0 (do0[x][y][1]), .wo1 (do1[x][y][1]), .wo2 (do2[x][y][1]), .wo3 (do3[x][y][1]), .wo4 (do4[x][y][1]), .woa (doa[x][y][1]),
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.no0 (do0[x][y][2]), .no1 (do1[x][y][2]), .no2 (do2[x][y][2]), .no3 (do3[x][y][2]), .no4 (do4[x][y][2]), .noa (doa[x][y][2]),
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.no0 (do0[x][y][2]), .no1 (do1[x][y][2]), .no2 (do2[x][y][2]), .no3 (do3[x][y][2]), .no4 (do4[x][y][2]), .noa (doa[x][y][2]),
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.eo0 (do0[x][y][3]), .eo1 (do1[x][y][3]), .eo2 (do2[x][y][3]), .eo3 (do3[x][y][3]), .eo4 (do4[x][y][3]), .eoa (doa[x][y][3]),
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.eo0 (do0[x][y][3]), .eo1 (do1[x][y][3]), .eo2 (do2[x][y][3]), .eo3 (do3[x][y][3]), .eo4 (do4[x][y][3]), .eoa (doa[x][y][3]),
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.rst_n(rst_n)
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.rst_n(rst_n)
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);
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);
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// north link
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// north link
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if(x==0) begin
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if(x==0) begin
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assign di0[x][y][2] = do0[x][y][2];
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assign di0[x][y][2] = do0[x][y][2];
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assign di1[x][y][2] = do1[x][y][2];
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assign di1[x][y][2] = do1[x][y][2];
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assign di2[x][y][2] = do2[x][y][2];
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assign di2[x][y][2] = do2[x][y][2];
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assign di3[x][y][2] = do3[x][y][2];
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assign di3[x][y][2] = do3[x][y][2];
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assign di4[x][y][2] = do4[x][y][2];
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assign di4[x][y][2] = do4[x][y][2];
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assign doa[x][y][2] = dia[x][y][2];
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assign doa[x][y][2] = dia[x][y][2];
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end else begin
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end else begin
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assign di0[x][y][2] = do0[x-1][y][0];
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assign di0[x][y][2] = do0[x-1][y][0];
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assign di1[x][y][2] = do1[x-1][y][0];
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assign di1[x][y][2] = do1[x-1][y][0];
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assign di2[x][y][2] = do2[x-1][y][0];
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assign di2[x][y][2] = do2[x-1][y][0];
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assign di3[x][y][2] = do3[x-1][y][0];
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assign di3[x][y][2] = do3[x-1][y][0];
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assign di4[x][y][2] = do4[x-1][y][0];
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assign di4[x][y][2] = do4[x-1][y][0];
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assign doa[x-1][y][0] = dia[x][y][2];
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assign doa[x-1][y][0] = dia[x][y][2];
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end
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end
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// south link
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// south link
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if(x==DIMX-1) begin
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if(x==DIMX-1) begin
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assign di0[x][y][0] = do0[x][y][0];
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assign di0[x][y][0] = do0[x][y][0];
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assign di1[x][y][0] = do1[x][y][0];
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assign di1[x][y][0] = do1[x][y][0];
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assign di2[x][y][0] = do2[x][y][0];
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assign di2[x][y][0] = do2[x][y][0];
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assign di3[x][y][0] = do3[x][y][0];
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assign di3[x][y][0] = do3[x][y][0];
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assign di4[x][y][0] = do4[x][y][0];
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assign di4[x][y][0] = do4[x][y][0];
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assign doa[x][y][0] = dia[x][y][0];
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assign doa[x][y][0] = dia[x][y][0];
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end else begin
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end else begin
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assign di0[x][y][0] = do0[x+1][y][2];
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assign di0[x][y][0] = do0[x+1][y][2];
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assign di1[x][y][0] = do1[x+1][y][2];
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assign di1[x][y][0] = do1[x+1][y][2];
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assign di2[x][y][0] = do2[x+1][y][2];
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assign di2[x][y][0] = do2[x+1][y][2];
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assign di3[x][y][0] = do3[x+1][y][2];
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assign di3[x][y][0] = do3[x+1][y][2];
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assign di4[x][y][0] = do4[x+1][y][2];
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assign di4[x][y][0] = do4[x+1][y][2];
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assign doa[x+1][y][2] = dia[x][y][0];
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assign doa[x+1][y][2] = dia[x][y][0];
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end
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end
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// west link
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// west link
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if(y==0) begin
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if(y==0) begin
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assign di0[x][y][1] = do0[x][y][1];
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assign di0[x][y][1] = do0[x][y][1];
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assign di1[x][y][1] = do1[x][y][1];
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assign di1[x][y][1] = do1[x][y][1];
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assign di2[x][y][1] = do2[x][y][1];
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assign di2[x][y][1] = do2[x][y][1];
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assign di3[x][y][1] = do3[x][y][1];
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assign di3[x][y][1] = do3[x][y][1];
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assign di4[x][y][1] = do4[x][y][1];
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assign di4[x][y][1] = do4[x][y][1];
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assign doa[x][y][1] = dia[x][y][1];
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assign doa[x][y][1] = dia[x][y][1];
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end else begin
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end else begin
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assign di0[x][y][1] = do0[x][y-1][3];
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assign di0[x][y][1] = do0[x][y-1][3];
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assign di1[x][y][1] = do1[x][y-1][3];
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assign di1[x][y][1] = do1[x][y-1][3];
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assign di2[x][y][1] = do2[x][y-1][3];
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assign di2[x][y][1] = do2[x][y-1][3];
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assign di3[x][y][1] = do3[x][y-1][3];
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assign di3[x][y][1] = do3[x][y-1][3];
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assign di4[x][y][1] = do4[x][y-1][3];
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assign di4[x][y][1] = do4[x][y-1][3];
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assign doa[x][y-1][3] = dia[x][y][1];
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assign doa[x][y-1][3] = dia[x][y][1];
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end // else: !if(y==0)
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end // else: !if(y==0)
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// east link
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// east link
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if(y==DIMY-1) begin
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if(y==DIMY-1) begin
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assign di0[x][y][3] = do0[x][y][3];
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assign di0[x][y][3] = do0[x][y][3];
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assign di1[x][y][3] = do1[x][y][3];
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assign di1[x][y][3] = do1[x][y][3];
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assign di2[x][y][3] = do2[x][y][3];
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assign di2[x][y][3] = do2[x][y][3];
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assign di3[x][y][3] = do3[x][y][3];
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assign di3[x][y][3] = do3[x][y][3];
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assign di4[x][y][3] = do4[x][y][3];
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assign di4[x][y][3] = do4[x][y][3];
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assign doa[x][y][3] = dia[x][y][3];
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assign doa[x][y][3] = dia[x][y][3];
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end else begin
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end else begin
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assign di0[x][y][3] = do0[x][y+1][1];
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assign di0[x][y][3] = do0[x][y+1][1];
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assign di1[x][y][3] = do1[x][y+1][1];
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assign di1[x][y][3] = do1[x][y+1][1];
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assign di2[x][y][3] = do2[x][y+1][1];
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assign di2[x][y][3] = do2[x][y+1][1];
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assign di3[x][y][3] = do3[x][y+1][1];
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assign di3[x][y][3] = do3[x][y+1][1];
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assign di4[x][y][3] = do4[x][y+1][1];
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assign di4[x][y][3] = do4[x][y+1][1];
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assign doa[x][y+1][1] = dia[x][y][3];
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assign doa[x][y+1][1] = dia[x][y][3];
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end // else: !if(y==DIMY-1)
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end // else: !if(y==DIMY-1)
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end // block: DY
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end // block: DY
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end // block: DX
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end // block: DX
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endgenerate
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endgenerate
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endmodule // noc_top
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endmodule // noc_top
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