/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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The port driver between NI and router.
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The port driver between NI and router.
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History:
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History:
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27/04/2010 Initial version. <wsong83@gmail.com>
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27/04/2010 Initial version. <wsong83@gmail.com>
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16/10/2010 Support SDM. <wsong83@gmail.com>
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16/10/2010 Support SDM. <wsong83@gmail.com>
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31/05/2011 Remove the sc_unit datatype to support data width larger than 64. <wsong83@gmail.com>
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31/05/2011 Remove the sc_unit datatype to support data width larger than 64. <wsong83@gmail.com>
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*/
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*/
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#include "rtdriver.h"
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#include "rtdriver.h"
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RTDriver::RTDriver(sc_module_name mname)
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RTDriver::RTDriver(sc_module_name mname)
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: sc_module(mname),
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: sc_module(mname),
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NI2P("NI2P"),
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NI2P("NI2P"),
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P2NI("P2NI")
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P2NI("P2NI")
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{
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{
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SC_METHOD(IPdetect);
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SC_METHOD(IPdetect);
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sensitive << rtia;
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sensitive << rtia;
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SC_METHOD(OPdetect);
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SC_METHOD(OPdetect);
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sensitive << rtod[0] << rtod[1] << rtod[2] << rtod[3] << rtod4;
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sensitive << rtod[0] << rtod[1] << rtod[2] << rtod[3] << rtod4;
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SC_THREAD(send);
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SC_THREAD(send);
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SC_THREAD(recv);
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SC_THREAD(recv);
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rtinp_sig = false;
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rtinp_sig = false;
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rtoutp_sig = false;
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rtoutp_sig = false;
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}
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}
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void RTDriver::IPdetect() {
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void RTDriver::IPdetect() {
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sc_logic ack_lv_high, ack_lv_low; // the sc_logic ack
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sc_logic ack_lv_high, ack_lv_low; // the sc_logic ack
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// read the ack
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// read the ack
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#ifdef ENABLE_CHANNEL_CLISING
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#ifdef ENABLE_CHANNEL_CLISING
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ack_lv_high = rtia.read().and_reduce();
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ack_lv_high = rtia.read().and_reduce();
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ack_lv_low = rtia.read().or_reduce();
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ack_lv_low = rtia.read().or_reduce();
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#else
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#else
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ack_lv_high = rtia.read();
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ack_lv_high = rtia.read();
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ack_lv_low = rtia.read();
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ack_lv_low = rtia.read();
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#endif
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#endif
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if(ack_lv_high.is_01() && ack_lv_high.to_bool())
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if(ack_lv_high.is_01() && ack_lv_high.to_bool())
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rtinp_sig = true;
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rtinp_sig = true;
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if(ack_lv_low.is_01() && (!ack_lv_low.to_bool()))
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if(ack_lv_low.is_01() && (!ack_lv_low.to_bool()))
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rtinp_sig = false;
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rtinp_sig = false;
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}
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}
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void RTDriver::OPdetect() {
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void RTDriver::OPdetect() {
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sc_lv<ChBW*4> data_lv; // the ORed data
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sc_lv<ChBW*4> data_lv; // the ORed data
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sc_logic data_lv_high, data_lv_low;
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sc_logic data_lv_high, data_lv_low;
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#ifdef ENABLE_CHANNEL_CLISING
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#ifdef ENABLE_CHANNEL_CLISING
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data_lv = rtod[0].read() | rtod[1].read() | rtod[2].read() | rtod[3].read() | rtod4.read();
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data_lv = rtod[0].read() | rtod[1].read() | rtod[2].read() | rtod[3].read() | rtod4.read();
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data_lv_high = data_lv.and_reduce();
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data_lv_high = data_lv.and_reduce();
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data_lv_low = data_lv.or_reduce();
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data_lv_low = data_lv.or_reduce();
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#else
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#else
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data_lv = rtod[0].read() | rtod[1].read() | rtod[2].read() | rtod[3].read();
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data_lv = rtod[0].read() | rtod[1].read() | rtod[2].read() | rtod[3].read();
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data_lv_high = data_lv.and_reduce() | rtod4.read();
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data_lv_high = data_lv.and_reduce() | rtod4.read();
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data_lv_low = data_lv.or_reduce() | rtod4.read();
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data_lv_low = data_lv.or_reduce() | rtod4.read();
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#endif
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#endif
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if(data_lv_high.is_01() && data_lv_high.to_bool())
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if(data_lv_high.is_01() && data_lv_high.to_bool())
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rtoutp_sig = true;
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rtoutp_sig = true;
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if(data_lv_high.is_01() && (!data_lv_low.to_bool()))
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if(data_lv_high.is_01() && (!data_lv_low.to_bool()))
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rtoutp_sig = false;
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rtoutp_sig = false;
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}
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}
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void RTDriver::send() {
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void RTDriver::send() {
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FLIT mflit; // the local flit buffer
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FLIT mflit; // the local flit buffer
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unsigned int i, j; // local loop index
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unsigned int i, j; // local loop index
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sc_lv<ChBW*4> mdata[4]; // local data copy
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sc_lv<ChBW*4> mdata[4]; // local data copy
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#ifdef ENABLE_CHANNEL_CLISING
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#ifdef ENABLE_CHANNEL_CLISING
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sc_lv<ChBW*4> mdata4; // local copy of eof
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sc_lv<ChBW*4> mdata4; // local copy of eof
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#else
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#else
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sc_logic mdata4; // local copy of eof
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sc_logic mdata4; // local copy of eof
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#endif
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#endif
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// initialize the output ports
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// initialize the output ports
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mdata[0] = 0;
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mdata[0] = 0;
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mdata[1] = 0;
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mdata[1] = 0;
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mdata[2] = 0;
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mdata[2] = 0;
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mdata[3] = 0;
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mdata[3] = 0;
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#ifdef ENABLE_CHANNEL_CLISING
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#ifdef ENABLE_CHANNEL_CLISING
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mdata4 = 0;
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mdata4 = 0;
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#else
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#else
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mdata4 = false;
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mdata4 = false;
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#endif
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#endif
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rtid[0].write(mdata[0]);
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rtid[0].write(mdata[0]);
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rtid[1].write(mdata[1]);
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rtid[1].write(mdata[1]);
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rtid[2].write(mdata[2]);
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rtid[2].write(mdata[2]);
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rtid[3].write(mdata[3]);
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rtid[3].write(mdata[3]);
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rtid4.write(mdata4);
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rtid4.write(mdata4);
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while(true) {
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while(true) {
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mflit = NI2P->read(); // read in the flit
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mflit = NI2P->read(); // read in the flit
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// write the flit
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// write the flit
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if(mflit.ftype == F_HD) {
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if(mflit.ftype == F_HD) {
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// the target address
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// the target address
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mdata[mflit.addrx&0x3][0] = SC_LOGIC_1;
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mdata[mflit.addrx&0x3][0] = SC_LOGIC_1;
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mdata[(mflit.addrx&0xc)>>2][1] = SC_LOGIC_1;
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mdata[(mflit.addrx&0xc)>>2][1] = SC_LOGIC_1;
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mdata[mflit.addry&0x3][2] = SC_LOGIC_1;
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mdata[mflit.addry&0x3][2] = SC_LOGIC_1;
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mdata[(mflit.addry&0xc)>>2][3] = SC_LOGIC_1;
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mdata[(mflit.addry&0xc)>>2][3] = SC_LOGIC_1;
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for(i=0,j=4; i<(ChBW-1)*4; i++, j++) {
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for(i=0,j=4; i<(ChBW-1)*4; i++, j++) {
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switch((mflit[i/4] >> ((i%4)*2)) & 0x3) {
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switch((mflit[i/4] >> ((i%4)*2)) & 0x3) {
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case 0: mdata[0][j] = SC_LOGIC_1; break;
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case 0: mdata[0][j] = SC_LOGIC_1; break;
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case 1: mdata[1][j] = SC_LOGIC_1; break;
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case 1: mdata[1][j] = SC_LOGIC_1; break;
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case 2: mdata[2][j] = SC_LOGIC_1; break;
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case 2: mdata[2][j] = SC_LOGIC_1; break;
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case 3: mdata[3][j] = SC_LOGIC_1; break;
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case 3: mdata[3][j] = SC_LOGIC_1; break;
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}
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}
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}
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}
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} else {
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} else {
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for(i=0; i<ChBW*4; i++) {
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for(i=0; i<ChBW*4; i++) {
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switch((mflit[i/4] >> ((i%4)*2)) & 0x3) {
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switch((mflit[i/4] >> ((i%4)*2)) & 0x3) {
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case 0: mdata[0][i] = SC_LOGIC_1; break;
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case 0: mdata[0][i] = SC_LOGIC_1; break;
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case 1: mdata[1][i] = SC_LOGIC_1; break;
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case 1: mdata[1][i] = SC_LOGIC_1; break;
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case 2: mdata[2][i] = SC_LOGIC_1; break;
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case 2: mdata[2][i] = SC_LOGIC_1; break;
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case 3: mdata[3][i] = SC_LOGIC_1; break;
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case 3: mdata[3][i] = SC_LOGIC_1; break;
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}
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}
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}
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}
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}
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}
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// write to the port
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// write to the port
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rtid[0].write(mdata[0]);
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rtid[0].write(mdata[0]);
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rtid[1].write(mdata[1]);
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rtid[1].write(mdata[1]);
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rtid[2].write(mdata[2]);
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rtid[2].write(mdata[2]);
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rtid[3].write(mdata[3]);
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rtid[3].write(mdata[3]);
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// wait for the router to capture the data
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// wait for the router to capture the data
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wait(rtinp_sig.posedge_event());
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wait(rtinp_sig.posedge_event());
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wait(0.2, SC_NS); // a delay to avoid data override
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wait(0.2, SC_NS); // a delay to avoid data override
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// clear the data
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// clear the data
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mdata[0] = 0;
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mdata[0] = 0;
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mdata[1] = 0;
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mdata[1] = 0;
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mdata[2] = 0;
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mdata[2] = 0;
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mdata[3] = 0;
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mdata[3] = 0;
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rtid[0].write(mdata[0]);
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rtid[0].write(mdata[0]);
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rtid[1].write(mdata[1]);
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rtid[1].write(mdata[1]);
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rtid[2].write(mdata[2]);
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rtid[2].write(mdata[2]);
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rtid[3].write(mdata[3]);
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rtid[3].write(mdata[3]);
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// wait for the input port be ready again
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// wait for the input port be ready again
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wait(rtinp_sig.negedge_event());
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wait(rtinp_sig.negedge_event());
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wait(0.2, SC_NS); // a delay to avoid data override
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wait(0.2, SC_NS); // a delay to avoid data override
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// check whether a tailf flit is needed
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// check whether a tailf flit is needed
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if(mflit.ftype == F_TL) {
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if(mflit.ftype == F_TL) {
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// write the eof
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// write the eof
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rtid4.write(~mdata4);
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rtid4.write(~mdata4);
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// wait for the router to capture the data
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// wait for the router to capture the data
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wait(rtinp_sig.posedge_event());
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wait(rtinp_sig.posedge_event());
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wait(0.2, SC_NS); // a delay to avoid data override
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wait(0.2, SC_NS); // a delay to avoid data override
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// clear the eof
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// clear the eof
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rtid4.write(mdata4);
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rtid4.write(mdata4);
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// wait for the input port be ready again
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// wait for the input port be ready again
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wait(rtinp_sig.negedge_event());
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wait(rtinp_sig.negedge_event());
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wait(0.2, SC_NS); // a delay to avoid data override
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wait(0.2, SC_NS); // a delay to avoid data override
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}
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}
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}
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}
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}
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}
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void RTDriver::recv() {
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void RTDriver::recv() {
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FLIT mflit; // the local flit buffer
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FLIT mflit; // the local flit buffer
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sc_lv<ChBW*4> mdata[4]; // local data copy
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sc_lv<ChBW*4> mdata[4]; // local data copy
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#ifdef ENABLE_CHANNEL_CLISING
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#ifdef ENABLE_CHANNEL_CLISING
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sc_lv<ChBW*4> mdata4; // local copy of eof
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sc_lv<ChBW*4> mdata4; // local copy of eof
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sc_lv<ChBW*4> mack = 0; // local copy of ack
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sc_lv<ChBW*4> mack = 0; // local copy of ack
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#else
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#else
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sc_logic mdata4; // local copy of eof
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sc_logic mdata4; // local copy of eof
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sc_logic mack = SC_LOGIC_0; // local copy of ack
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sc_logic mack = SC_LOGIC_0; // local copy of ack
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#endif
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#endif
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sc_lv<4> dd; // the current 1-of-4 data under process
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sc_lv<4> dd; // the current 1-of-4 data under process
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unsigned int i, j; // local loop index
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unsigned int i, j; // local loop index
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bool is_hd = true; // the current flit is a header flit
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bool is_hd = true; // the current flit is a header flit
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// initialize the ack signal
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// initialize the ack signal
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rtoa.write(mack);
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rtoa.write(mack);
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while(true) {
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while(true) {
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// clear the flit
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// clear the flit
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mflit.clear();
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mflit.clear();
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// wait for an incoming flit
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// wait for an incoming flit
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wait(rtoutp_sig.posedge_event());
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wait(rtoutp_sig.posedge_event());
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// analyse the flit
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// analyse the flit
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mdata[0] = rtod[0].read();
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mdata[0] = rtod[0].read();
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mdata[1] = rtod[1].read();
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mdata[1] = rtod[1].read();
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mdata[2] = rtod[2].read();
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mdata[2] = rtod[2].read();
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mdata[3] = rtod[3].read();
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mdata[3] = rtod[3].read();
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mdata4 = rtod4.read();
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mdata4 = rtod4.read();
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if(is_hd) {
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if(is_hd) {
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mflit.ftype = F_HD;
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mflit.ftype = F_HD;
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is_hd = false;
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is_hd = false;
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}
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}
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#ifdef ENABLE_CHANNEL_CLISING
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#ifdef ENABLE_CHANNEL_CLISING
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else if(mdata4[0].to_bool()) {
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else if(mdata4[0].to_bool()) {
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mflit.ftype = F_TL;
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mflit.ftype = F_TL;
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is_hd = true;
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is_hd = true;
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}
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}
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#else
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#else
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else if(mdata4.to_bool()) {
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else if(mdata4.to_bool()) {
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mflit.ftype = F_TL;
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mflit.ftype = F_TL;
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is_hd = true;
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is_hd = true;
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}
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}
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#endif
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#endif
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else {
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else {
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mflit.ftype = F_DAT;
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mflit.ftype = F_DAT;
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}
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}
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if(mflit.ftype == F_HD) {
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if(mflit.ftype == F_HD) {
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// fetch the address
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// fetch the address
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dd[0] = mdata[0][0]; dd[1] = mdata[1][0]; dd[2] = mdata[2][0]; dd[3] = mdata[3][0];
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dd[0] = mdata[0][0]; dd[1] = mdata[1][0]; dd[2] = mdata[2][0]; dd[3] = mdata[3][0];
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mflit.addrx |= (c1o42b(dd.to_uint()) << 0);
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mflit.addrx |= (c1o42b(dd.to_uint()) << 0);
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dd[0] = mdata[0][1]; dd[1] = mdata[1][1]; dd[2] = mdata[2][1]; dd[3] = mdata[3][1];
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dd[0] = mdata[0][1]; dd[1] = mdata[1][1]; dd[2] = mdata[2][1]; dd[3] = mdata[3][1];
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mflit.addrx |= (c1o42b(dd.to_uint()) << 2);
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mflit.addrx |= (c1o42b(dd.to_uint()) << 2);
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dd[0] = mdata[0][2]; dd[1] = mdata[1][2]; dd[2] = mdata[2][2]; dd[3] = mdata[3][2];
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dd[0] = mdata[0][2]; dd[1] = mdata[1][2]; dd[2] = mdata[2][2]; dd[3] = mdata[3][2];
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mflit.addry |= (c1o42b(dd.to_uint()) << 0);
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mflit.addry |= (c1o42b(dd.to_uint()) << 0);
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dd[0] = mdata[0][3]; dd[1] = mdata[1][3]; dd[2] = mdata[2][3]; dd[3] = mdata[3][3];
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dd[0] = mdata[0][3]; dd[1] = mdata[1][3]; dd[2] = mdata[2][3]; dd[3] = mdata[3][3];
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mflit.addry |= (c1o42b(dd.to_uint()) << 2);
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mflit.addry |= (c1o42b(dd.to_uint()) << 2);
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// fill in data
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// fill in data
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for(i=1; i<ChBW; i++) {
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for(i=1; i<ChBW; i++) {
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for(j=0; j<4; j++) {
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for(j=0; j<4; j++) {
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dd[0] = mdata[0][i*4+j];
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dd[0] = mdata[0][i*4+j];
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dd[1] = mdata[1][i*4+j];
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dd[1] = mdata[1][i*4+j];
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dd[2] = mdata[2][i*4+j];
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dd[2] = mdata[2][i*4+j];
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dd[3] = mdata[3][i*4+j];
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dd[3] = mdata[3][i*4+j];
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mflit[i-1] |= c1o42b(dd.to_uint()) << j*2;
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mflit[i-1] |= c1o42b(dd.to_uint()) << j*2;
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}
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}
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}
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}
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} else if (mflit.ftype != F_TL) {
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} else if (mflit.ftype != F_TL) {
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// fill in data
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// fill in data
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for(i=0; i<ChBW; i++) {
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for(i=0; i<ChBW; i++) {
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for(j=0; j<4; j++) {
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for(j=0; j<4; j++) {
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dd[0] = mdata[0][i*4+j];
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dd[0] = mdata[0][i*4+j];
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dd[1] = mdata[1][i*4+j];
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dd[1] = mdata[1][i*4+j];
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dd[2] = mdata[2][i*4+j];
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dd[2] = mdata[2][i*4+j];
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dd[3] = mdata[3][i*4+j];
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dd[3] = mdata[3][i*4+j];
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mflit[i] |= c1o42b(dd.to_uint()) << j*2;
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mflit[i] |= c1o42b(dd.to_uint()) << j*2;
|
}
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}
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}
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}
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}
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}
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// send the flit to the NI
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// send the flit to the NI
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P2NI->write(mflit);
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P2NI->write(mflit);
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|
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wait(0.2, SC_NS); // a delay to avoid data override
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wait(0.2, SC_NS); // a delay to avoid data override
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rtoa.write(~mack); // notify that data is captured
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rtoa.write(~mack); // notify that data is captured
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|
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// wait for the data withdrawal
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// wait for the data withdrawal
|
wait(rtoutp_sig.negedge_event());
|
wait(rtoutp_sig.negedge_event());
|
wait(0.2, SC_NS); // a delay to avoid data override
|
wait(0.2, SC_NS); // a delay to avoid data override
|
rtoa.write(mack); // notify that data is captured
|
rtoa.write(mack); // notify that data is captured
|
|
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}
|
}
|
}
|
}
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|
|
unsigned int RTDriver::c1o42b(unsigned int dd) {
|
unsigned int RTDriver::c1o42b(unsigned int dd) {
|
switch(dd) {
|
switch(dd) {
|
case 1: return 0;
|
case 1: return 0;
|
case 2: return 1;
|
case 2: return 1;
|
case 4: return 2;
|
case 4: return 2;
|
case 8: return 3;
|
case 8: return 3;
|
default: return 0xff;
|
default: return 0xff;
|
}
|
}
|
}
|
}
|
|
|
