/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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The wrapper for the synthesized router.
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The wrapper for the synthesized router.
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History:
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History:
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28/05/2009 Initial version. <wsong83@gmail.com>
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28/05/2009 Initial version. <wsong83@gmail.com>
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30/05/2011 Clean up for opensource. <wsong83@gmail.com>
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30/05/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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module router_hdl(/*AUTOARG*/
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module router_hdl(/*AUTOARG*/
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// Outputs
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// Outputs
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so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
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so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
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eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
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eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
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wia, nia, eia, lia,
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wia, nia, eia, lia,
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// Inputs
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// Inputs
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si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
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si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
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ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
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ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
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woa, noa, eoa, loa, addrx, addry, rst_n
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woa, noa, eoa, loa, addrx, addry, rst_n
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);
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);
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parameter VCN = 1; // number of virtual circuits in each direction. When VCN == 1, it is a wormhole router
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parameter VCN = 1; // number of virtual circuits in each direction. When VCN == 1, it is a wormhole router
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parameter DW = 32; // the datawidth of a single virtual circuit, the total data width of the router is DW*VCN
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parameter DW = 32; // the datawidth of a single virtual circuit, the total data width of the router is DW*VCN
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parameter SCN = DW/2; // the number of 1-of-4 sub-channel in each virtual circuit
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parameter SCN = DW/2; // the number of 1-of-4 sub-channel in each virtual circuit
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input [VCN*SCN-1:0] si0, si1, si2, si3;
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input [VCN*SCN-1:0] si0, si1, si2, si3;
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input [VCN*SCN-1:0] wi0, wi1, wi2, wi3;
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input [VCN*SCN-1:0] wi0, wi1, wi2, wi3;
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input [VCN*SCN-1:0] ni0, ni1, ni2, ni3;
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input [VCN*SCN-1:0] ni0, ni1, ni2, ni3;
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input [VCN*SCN-1:0] ei0, ei1, ei2, ei3;
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input [VCN*SCN-1:0] ei0, ei1, ei2, ei3;
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input [VCN*SCN-1:0] li0, li1, li2, li3;
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input [VCN*SCN-1:0] li0, li1, li2, li3;
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output [VCN*SCN-1:0] so0, so1, so2, so3;
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output [VCN*SCN-1:0] so0, so1, so2, so3;
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output [VCN*SCN-1:0] wo0, wo1, wo2, wo3;
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output [VCN*SCN-1:0] wo0, wo1, wo2, wo3;
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output [VCN*SCN-1:0] no0, no1, no2, no3;
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output [VCN*SCN-1:0] no0, no1, no2, no3;
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output [VCN*SCN-1:0] eo0, eo1, eo2, eo3;
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output [VCN*SCN-1:0] eo0, eo1, eo2, eo3;
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output [VCN*SCN-1:0] lo0, lo1, lo2, lo3;
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output [VCN*SCN-1:0] lo0, lo1, lo2, lo3;
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// eof bits and ack lines
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// eof bits and ack lines
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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input [VCN*SCN-1:0] si4, wi4, ni4, ei4, li4;
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input [VCN*SCN-1:0] si4, wi4, ni4, ei4, li4;
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output [VCN*SCN-1:0] so4, wo4, no4, eo4, lo4;
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output [VCN*SCN-1:0] so4, wo4, no4, eo4, lo4;
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output [VCN*SCN-1:0] sia, wia, nia, eia, lia;
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output [VCN*SCN-1:0] sia, wia, nia, eia, lia;
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input [VCN*SCN-1:0] soa, woa, noa, eoa, loa;
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input [VCN*SCN-1:0] soa, woa, noa, eoa, loa;
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`else
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`else
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input [VCN-1:0] si4, wi4, ni4, ei4, li4;
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input [VCN-1:0] si4, wi4, ni4, ei4, li4;
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output [VCN-1:0] so4, wo4, no4, eo4, lo4;
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output [VCN-1:0] so4, wo4, no4, eo4, lo4;
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output [VCN-1:0] sia, wia, nia, eia, lia;
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output [VCN-1:0] sia, wia, nia, eia, lia;
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input [VCN-1:0] soa, woa, noa, eoa, loa;
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input [VCN-1:0] soa, woa, noa, eoa, loa;
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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input [7:0] addrx, addry;
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input [7:0] addrx, addry;
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input rst_n;
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input rst_n;
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wire [VCN*SCN-1:0] psi0, psi1, psi2, psi3;
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wire [VCN*SCN-1:0] psi0, psi1, psi2, psi3;
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wire [VCN*SCN-1:0] pwi0, pwi1, pwi2, pwi3;
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wire [VCN*SCN-1:0] pwi0, pwi1, pwi2, pwi3;
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wire [VCN*SCN-1:0] pni0, pni1, pni2, pni3;
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wire [VCN*SCN-1:0] pni0, pni1, pni2, pni3;
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wire [VCN*SCN-1:0] pei0, pei1, pei2, pei3;
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wire [VCN*SCN-1:0] pei0, pei1, pei2, pei3;
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wire [VCN*SCN-1:0] pli0, pli1, pli2, pli3;
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wire [VCN*SCN-1:0] pli0, pli1, pli2, pli3;
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wire [VCN*SCN-1:0] pso0, pso1, pso2, pso3;
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wire [VCN*SCN-1:0] pso0, pso1, pso2, pso3;
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wire [VCN*SCN-1:0] pwo0, pwo1, pwo2, pwo3;
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wire [VCN*SCN-1:0] pwo0, pwo1, pwo2, pwo3;
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wire [VCN*SCN-1:0] pno0, pno1, pno2, pno3;
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wire [VCN*SCN-1:0] pno0, pno1, pno2, pno3;
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wire [VCN*SCN-1:0] peo0, peo1, peo2, peo3;
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wire [VCN*SCN-1:0] peo0, peo1, peo2, peo3;
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wire [VCN*SCN-1:0] plo0, plo1, plo2, plo3;
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wire [VCN*SCN-1:0] plo0, plo1, plo2, plo3;
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// eof bits and ack lines
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// eof bits and ack lines
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [VCN*SCN-1:0] psi4, pwi4, pni4, pei4, pli4;
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wire [VCN*SCN-1:0] psi4, pwi4, pni4, pei4, pli4;
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wire [VCN*SCN-1:0] pso4, pwo4, pno4, peo4, plo4;
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wire [VCN*SCN-1:0] pso4, pwo4, pno4, peo4, plo4;
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wire [VCN*SCN-1:0] psia, pwia, pnia, peia, plia;
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wire [VCN*SCN-1:0] psia, pwia, pnia, peia, plia;
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wire [VCN*SCN-1:0] psoa, pwoa, pnoa, peoa, ploa;
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wire [VCN*SCN-1:0] psoa, pwoa, pnoa, peoa, ploa;
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`else
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`else
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wire [VCN-1:0] psi4, pwi4, pni4, pei4, pli4;
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wire [VCN-1:0] psi4, pwi4, pni4, pei4, pli4;
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wire [VCN-1:0] pso4, pwo4, pno4, peo4, plo4;
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wire [VCN-1:0] pso4, pwo4, pno4, peo4, plo4;
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wire [VCN-1:0] psia, pwia, pnia, peia, plia;
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wire [VCN-1:0] psia, pwia, pnia, peia, plia;
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wire [VCN-1:0] psoa, pwoa, pnoa, peoa, ploa;
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wire [VCN-1:0] psoa, pwoa, pnoa, peoa, ploa;
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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wire [7:0] paddrx, paddry;
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wire [7:0] paddrx, paddry;
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wire prst_n;
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wire prst_n;
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router RT (
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router RT (
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.sia ( psia ),
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.sia ( psia ),
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.wia ( pwia ),
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.wia ( pwia ),
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.nia ( pnia ),
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.nia ( pnia ),
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.eia ( peia ),
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.eia ( peia ),
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.lia ( plia ),
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.lia ( plia ),
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.so0 ( pso0 ),
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.so0 ( pso0 ),
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.so1 ( pso1 ),
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.so1 ( pso1 ),
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.so2 ( pso2 ),
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.so2 ( pso2 ),
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.so3 ( pso3 ),
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.so3 ( pso3 ),
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.wo0 ( pwo0 ),
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.wo0 ( pwo0 ),
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.wo1 ( pwo1 ),
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.wo1 ( pwo1 ),
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.wo2 ( pwo2 ),
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.wo2 ( pwo2 ),
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.wo3 ( pwo3 ),
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.wo3 ( pwo3 ),
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.no0 ( pno0 ),
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.no0 ( pno0 ),
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.no1 ( pno1 ),
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.no1 ( pno1 ),
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.no2 ( pno2 ),
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.no2 ( pno2 ),
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.no3 ( pno3 ),
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.no3 ( pno3 ),
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.eo0 ( peo0 ),
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.eo0 ( peo0 ),
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.eo1 ( peo1 ),
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.eo1 ( peo1 ),
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.eo2 ( peo2 ),
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.eo2 ( peo2 ),
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.eo3 ( peo3 ),
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.eo3 ( peo3 ),
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.lo0 ( plo0 ),
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.lo0 ( plo0 ),
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.lo1 ( plo1 ),
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.lo1 ( plo1 ),
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.lo2 ( plo2 ),
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.lo2 ( plo2 ),
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.lo3 ( plo3 ),
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.lo3 ( plo3 ),
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.so4 ( pso4 ),
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.so4 ( pso4 ),
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.wo4 ( pwo4 ),
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.wo4 ( pwo4 ),
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.no4 ( pno4 ),
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.no4 ( pno4 ),
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.eo4 ( peo4 ),
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.eo4 ( peo4 ),
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.lo4 ( plo4 ),
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.lo4 ( plo4 ),
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.si0 ( psi0 ),
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.si0 ( psi0 ),
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.si1 ( psi1 ),
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.si1 ( psi1 ),
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.si2 ( psi2 ),
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.si2 ( psi2 ),
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.si3 ( psi3 ),
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.si3 ( psi3 ),
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.wi0 ( pwi0 ),
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.wi0 ( pwi0 ),
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.wi1 ( pwi1 ),
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.wi1 ( pwi1 ),
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.wi2 ( pwi2 ),
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.wi2 ( pwi2 ),
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.wi3 ( pwi3 ),
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.wi3 ( pwi3 ),
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.ni0 ( pni0 ),
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.ni0 ( pni0 ),
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.ni1 ( pni1 ),
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.ni1 ( pni1 ),
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.ni2 ( pni2 ),
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.ni2 ( pni2 ),
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.ni3 ( pni3 ),
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.ni3 ( pni3 ),
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.ei0 ( pei0 ),
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.ei0 ( pei0 ),
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.ei1 ( pei1 ),
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.ei1 ( pei1 ),
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.ei2 ( pei2 ),
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.ei2 ( pei2 ),
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.ei3 ( pei3 ),
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.ei3 ( pei3 ),
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.li0 ( pli0 ),
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.li0 ( pli0 ),
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.li1 ( pli1 ),
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.li1 ( pli1 ),
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.li2 ( pli2 ),
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.li2 ( pli2 ),
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.li3 ( pli3 ),
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.li3 ( pli3 ),
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.si4 ( psi4 ),
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.si4 ( psi4 ),
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.wi4 ( pwi4 ),
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.wi4 ( pwi4 ),
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.ni4 ( pni4 ),
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.ni4 ( pni4 ),
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.ei4 ( pei4 ),
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.ei4 ( pei4 ),
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.li4 ( pli4 ),
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.li4 ( pli4 ),
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.soa ( psoa ),
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.soa ( psoa ),
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.woa ( pwoa ),
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.woa ( pwoa ),
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.noa ( pnoa ),
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.noa ( pnoa ),
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.eoa ( peoa ),
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.eoa ( peoa ),
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.loa ( ploa ),
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.loa ( ploa ),
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.addrx ( paddrx ),
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.addrx ( paddrx ),
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.addry ( paddry ),
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.addry ( paddry ),
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.rst_n ( prst_n )
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.rst_n ( prst_n )
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);
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);
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assign sia = psia ;
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assign sia = psia ;
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assign wia = pwia ;
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assign wia = pwia ;
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assign nia = pnia ;
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assign nia = pnia ;
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assign eia = peia ;
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assign eia = peia ;
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assign lia = plia ;
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assign lia = plia ;
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assign so0 = pso0 ;
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assign so0 = pso0 ;
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assign so1 = pso1 ;
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assign so1 = pso1 ;
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assign so2 = pso2 ;
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assign so2 = pso2 ;
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assign so3 = pso3 ;
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assign so3 = pso3 ;
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assign wo0 = pwo0 ;
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assign wo0 = pwo0 ;
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assign wo1 = pwo1 ;
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assign wo1 = pwo1 ;
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assign wo2 = pwo2 ;
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assign wo2 = pwo2 ;
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assign wo3 = pwo3 ;
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assign wo3 = pwo3 ;
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assign no0 = pno0 ;
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assign no0 = pno0 ;
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assign no1 = pno1 ;
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assign no1 = pno1 ;
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assign no2 = pno2 ;
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assign no2 = pno2 ;
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assign no3 = pno3 ;
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assign no3 = pno3 ;
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assign eo0 = peo0 ;
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assign eo0 = peo0 ;
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assign eo1 = peo1 ;
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assign eo1 = peo1 ;
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assign eo2 = peo2 ;
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assign eo2 = peo2 ;
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assign eo3 = peo3 ;
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assign eo3 = peo3 ;
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assign lo0 = plo0 ;
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assign lo0 = plo0 ;
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assign lo1 = plo1 ;
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assign lo1 = plo1 ;
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assign lo2 = plo2 ;
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assign lo2 = plo2 ;
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assign lo3 = plo3 ;
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assign lo3 = plo3 ;
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assign so4 = pso4 ;
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assign so4 = pso4 ;
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assign wo4 = pwo4 ;
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assign wo4 = pwo4 ;
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assign no4 = pno4 ;
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assign no4 = pno4 ;
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assign eo4 = peo4 ;
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assign eo4 = peo4 ;
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assign lo4 = plo4 ;
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assign lo4 = plo4 ;
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assign psi0 = si0 ;
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assign psi0 = si0 ;
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assign psi1 = si1 ;
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assign psi1 = si1 ;
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assign psi2 = si2 ;
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assign psi2 = si2 ;
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assign psi3 = si3 ;
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assign psi3 = si3 ;
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assign pwi0 = wi0 ;
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assign pwi0 = wi0 ;
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assign pwi1 = wi1 ;
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assign pwi1 = wi1 ;
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assign pwi2 = wi2 ;
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assign pwi2 = wi2 ;
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assign pwi3 = wi3 ;
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assign pwi3 = wi3 ;
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assign pni0 = ni0 ;
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assign pni0 = ni0 ;
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assign pni1 = ni1 ;
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assign pni1 = ni1 ;
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assign pni2 = ni2 ;
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assign pni2 = ni2 ;
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assign pni3 = ni3 ;
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assign pni3 = ni3 ;
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assign pei0 = ei0 ;
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assign pei0 = ei0 ;
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assign pei1 = ei1 ;
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assign pei1 = ei1 ;
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assign pei2 = ei2 ;
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assign pei2 = ei2 ;
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assign pei3 = ei3 ;
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assign pei3 = ei3 ;
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assign pli0 = li0 ;
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assign pli0 = li0 ;
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assign pli1 = li1 ;
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assign pli1 = li1 ;
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assign pli2 = li2 ;
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assign pli2 = li2 ;
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assign pli3 = li3 ;
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assign pli3 = li3 ;
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assign psi4 = si4 ;
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assign psi4 = si4 ;
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assign pwi4 = wi4 ;
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assign pwi4 = wi4 ;
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assign pni4 = ni4 ;
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assign pni4 = ni4 ;
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assign pei4 = ei4 ;
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assign pei4 = ei4 ;
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assign pli4 = li4 ;
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assign pli4 = li4 ;
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assign psoa = soa ;
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assign psoa = soa ;
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assign pwoa = woa ;
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assign pwoa = woa ;
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assign pnoa = noa ;
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assign pnoa = noa ;
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assign peoa = eoa ;
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assign peoa = eoa ;
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assign ploa = loa ;
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assign ploa = loa ;
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assign paddrx = addrx ;
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assign paddrx = addrx ;
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assign paddry = addry ;
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assign paddry = addry ;
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assign prst_n = rst_n ;
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assign prst_n = rst_n ;
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initial $sdf_annotate("../syn/file/router.sdf", RT);
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initial $sdf_annotate("../syn/file/router.sdf", RT);
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endmodule
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endmodule
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