/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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The input buffer for VC routers.
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The input buffer for VC routers.
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History:
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History:
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01/04/2010 Initial version. <wsong83@gmail.com>
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01/04/2010 Initial version. <wsong83@gmail.com>
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12/05/2010 Use MPxP crossbars. <wsong83@gmail.com>
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12/05/2010 Use MPxP crossbars. <wsong83@gmail.com>
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17/04/2010 Remove unnecessary pipeline stages. <wsong83@gmail.com>
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17/04/2010 Remove unnecessary pipeline stages. <wsong83@gmail.com>
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02/06/2011 Clean up for opensource. <wsong83@gmail.com>
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02/06/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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module inpbuf (/*AUTOARG*/
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module inpbuf (/*AUTOARG*/
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// Outputs
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// Outputs
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dia, cor, do0, do1, do2, do3, dot, dortg, vcr, swr,
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dia, cor, do0, do1, do2, do3, dot, dortg, vcr, swr,
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// Inputs
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// Inputs
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di0, di1, di2, di3, dit, divc, coa, doa, vcra, swrt, addrx, addry,
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di0, di1, di2, di3, dit, divc, coa, doa, vcra, swrt, addrx, addry,
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rst_n
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rst_n
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);
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);
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parameter DW = 32; // data width
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parameter DW = 32; // data width
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parameter VCN = 2; // VC number
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parameter VCN = 2; // VC number
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parameter DIR = 0; // 0-4 south, west, north, east, local
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parameter DIR = 0; // 0-4 south, west, north, east, local
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parameter SN = 2; // maximal output port number
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parameter SN = 2; // maximal output port number
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parameter PD = 3; // the depth of the input buffer pipeline
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parameter PD = 3; // the depth of the input buffer pipeline
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parameter SCN = DW/2; // number of 1-of-4 sub-channels
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parameter SCN = DW/2; // number of 1-of-4 sub-channels
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parameter FT = 3; // flit type, now 3, HOF, BOF, EOF
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parameter FT = 3; // flit type, now 3, HOF, BOF, EOF
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// data IP
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// data IP
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input [SCN-1:0] di0, di1, di2, di3;
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input [SCN-1:0] di0, di1, di2, di3;
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input [FT-1:0] dit;
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input [FT-1:0] dit;
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input [VCN-1:0] divc;
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input [VCN-1:0] divc;
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output dia;
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output dia;
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// credit flow-control
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// credit flow-control
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output [VCN-1:0] cor;
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output [VCN-1:0] cor;
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input [VCN-1:0] coa;
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input [VCN-1:0] coa;
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// data to crossbar
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// data to crossbar
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output [VCN-1:0][SCN-1:0] do0,do1,do2,do3;
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output [VCN-1:0][SCN-1:0] do0,do1,do2,do3;
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output [VCN-1:0][FT-1:0] dot;
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output [VCN-1:0][FT-1:0] dot;
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output [VCN-1:0][SN-1:0] dortg;
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output [VCN-1:0][SN-1:0] dortg;
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input [VCN-1:0] doa;
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input [VCN-1:0] doa;
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// request to VC allocator
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// request to VC allocator
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output [VCN-1:0][SN-1:0] vcr;
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output [VCN-1:0][SN-1:0] vcr;
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input [VCN-1:0] vcra;
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input [VCN-1:0] vcra;
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// output to SW allocator
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// output to SW allocator
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output [VCN-1:0][1:0] swr;
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output [VCN-1:0][1:0] swr;
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// routing guide for SW DEMUX
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// routing guide for SW DEMUX
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input [VCN-1:0][SN-1:0] swrt;
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input [VCN-1:0][SN-1:0] swrt;
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// local addresses
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// local addresses
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input [7:0] addrx, addry;
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input [7:0] addrx, addry;
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input rst_n;
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input rst_n;
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//-----------------------------
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//-----------------------------
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// VC_MUX
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// VC_MUX
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wire ivma, rua;
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wire ivma, rua;
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wire [SCN-1:0] di0m, di1m, di2m, di3m;
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wire [SCN-1:0] di0m, di1m, di2m, di3m;
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wire [FT-1:0] ditm;
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wire [FT-1:0] ditm;
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wire [VCN-1:0] divcm;
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wire [VCN-1:0] divcm;
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wire [VCN-1:0] muxa;
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wire [VCN-1:0] muxa;
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// VC_BUF
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// VC_BUF
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wire [2*PD:0][VCN-1:0][SCN-1:0] vcd0, vcd1, vcd2, vcd3; // VC data
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wire [2*PD:0][VCN-1:0][SCN-1:0] vcd0, vcd1, vcd2, vcd3; // VC data
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wire [2*PD:0][VCN-1:0][FT-1:0] vcdt; // VC flit type
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wire [2*PD:0][VCN-1:0][FT-1:0] vcdt; // VC flit type
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wire [2*PD:0][VCN-1:0][SCN-1:0] vcdad, vcdadn; // VC ack
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wire [2*PD:0][VCN-1:0][SCN-1:0] vcdad, vcdadn; // VC ack
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wire [2*PD:0][VCN-1:0] vcdat, vcdatn; // VC data ack and type ack
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wire [2*PD:0][VCN-1:0] vcdat, vcdatn; // VC data ack and type ack
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wire [1:0][VCN-1:0] vcda; // the comman ack
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wire [1:0][VCN-1:0] vcda; // the comman ack
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// control path
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// control path
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wire [2*PD:2*PD-2][VCN-1:0][1:0] vcft; // flit type on control path
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wire [2*PD:2*PD-2][VCN-1:0][1:0] vcft; // flit type on control path
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wire [2*PD:2*PD-2][VCN-1:0] vcfta, vcftan; // flit type ack, on control path
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wire [2*PD:2*PD-2][VCN-1:0] vcfta, vcftan; // flit type ack, on control path
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wire [VCN-1:0] vcdam; // need an extra ack internal signal
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wire [VCN-1:0] vcdam; // need an extra ack internal signal
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wire [VCN-1:0][SN-1:0] rtg; // routing direction guide
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wire [VCN-1:0][SN-1:0] rtg; // routing direction guide
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wire [VCN-1:0] doan;
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wire [VCN-1:0] doan;
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// last stage of input buffer
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// last stage of input buffer
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wire [VCN-1:0] vcor;
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wire [VCN-1:0] vcor;
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wire [VCN-1:0] vcog;
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wire [VCN-1:0] vcog;
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wire [VCN-1:0] swa;
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wire [VCN-1:0] swa;
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genvar gbd, gvc, gsub, i;
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genvar gbd, gvc, gsub, i;
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//---------------------------------------------
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//---------------------------------------------
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// the input VCDMUX
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// the input VCDMUX
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vcdmux #(.VCN(VCN), .DW(DW))
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vcdmux #(.VCN(VCN), .DW(DW))
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IVM (
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IVM (
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.dia ( ivma ),
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.dia ( ivma ),
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.do0 ( vcd0[0] ),
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.do0 ( vcd0[0] ),
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.do1 ( vcd1[0] ),
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.do1 ( vcd1[0] ),
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.do2 ( vcd2[0] ),
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.do2 ( vcd2[0] ),
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.do3 ( vcd3[0] ),
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.do3 ( vcd3[0] ),
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.dot ( vcdt[0] ),
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.dot ( vcdt[0] ),
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.di0 ( di0m ),
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.di0 ( di0m ),
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.di1 ( di1m ),
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.di1 ( di1m ),
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.di2 ( di2m ),
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.di2 ( di2m ),
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.di3 ( di3m ),
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.di3 ( di3m ),
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.dit ( ditm ),
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.dit ( ditm ),
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.divc ( divcm ),
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.divc ( divcm ),
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.doa ( muxa )
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.doa ( muxa )
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);
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);
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//c2 IVMA (.a0(ivma), .a1(rua), .q(dia)); divc is not checked
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//c2 IVMA (.a0(ivma), .a1(rua), .q(dia)); divc is not checked
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ctree #(.DW(3)) ACKT(.ci({ivma, rua, (|divcm)}), .co(dia));
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ctree #(.DW(3)) ACKT(.ci({ivma, rua, (|divcm)}), .co(dia));
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assign di0m = rst_n ? di0 : 0;
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assign di0m = rst_n ? di0 : 0;
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assign di1m = rst_n ? di1 : 0;
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assign di1m = rst_n ? di1 : 0;
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assign di2m = rst_n ? di2 : 0;
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assign di2m = rst_n ? di2 : 0;
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assign di3m = rst_n ? di3 : 0;
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assign di3m = rst_n ? di3 : 0;
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assign ditm = rst_n ? dit : 0;
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assign ditm = rst_n ? dit : 0;
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assign divcm = rst_n ? divc : 0;
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assign divcm = rst_n ? divc : 0;
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//---------------------------------------------
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//---------------------------------------------
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// the VC buffers
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// the VC buffers
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generate
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generate
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for(gbd=0; gbd<PD*2-2; gbd++) begin:BFN
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for(gbd=0; gbd<PD*2-2; gbd++) begin:BFN
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for(gvc=0; gvc<VCN; gvc++) begin:V
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for(gvc=0; gvc<VCN; gvc++) begin:V
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for(gsub=0; gsub<SCN; gsub++) begin:SC
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for(gsub=0; gsub<SCN; gsub++) begin:SC
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pipe4 #(.DW(2))
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pipe4 #(.DW(2))
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DP (
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DP (
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.ia ( vcdad[gbd][gvc][gsub] ),
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.ia ( vcdad[gbd][gvc][gsub] ),
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.o0 ( vcd0[gbd+1][gvc][gsub] ),
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.o0 ( vcd0[gbd+1][gvc][gsub] ),
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.o1 ( vcd1[gbd+1][gvc][gsub] ),
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.o1 ( vcd1[gbd+1][gvc][gsub] ),
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.o2 ( vcd2[gbd+1][gvc][gsub] ),
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.o2 ( vcd2[gbd+1][gvc][gsub] ),
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.o3 ( vcd3[gbd+1][gvc][gsub] ),
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.o3 ( vcd3[gbd+1][gvc][gsub] ),
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.i0 ( vcd0[gbd][gvc][gsub] ),
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.i0 ( vcd0[gbd][gvc][gsub] ),
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.i1 ( vcd1[gbd][gvc][gsub] ),
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.i1 ( vcd1[gbd][gvc][gsub] ),
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.i2 ( vcd2[gbd][gvc][gsub] ),
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.i2 ( vcd2[gbd][gvc][gsub] ),
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.i3 ( vcd3[gbd][gvc][gsub] ),
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.i3 ( vcd3[gbd][gvc][gsub] ),
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.oa ( vcdadn[gbd+1][gvc][gsub] )
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.oa ( vcdadn[gbd+1][gvc][gsub] )
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);
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);
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assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rst_n;
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assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rst_n;
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end // block: SC
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end // block: SC
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pipen #(.DW(FT))
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pipen #(.DW(FT))
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TP (
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TP (
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.d_in ( vcdt[gbd][gvc] ),
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.d_in ( vcdt[gbd][gvc] ),
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.d_in_a ( vcdat[gbd][gvc] ),
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.d_in_a ( vcdat[gbd][gvc] ),
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.d_out ( vcdt[gbd+1][gvc] ),
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.d_out ( vcdt[gbd+1][gvc] ),
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.d_out_a ( vcdatn[gbd+1][gvc] )
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.d_out_a ( vcdatn[gbd+1][gvc] )
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);
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);
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assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rst_n;
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assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rst_n;
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end // block: V
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end // block: V
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end // block: BFN
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end // block: BFN
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for(gvc=0; gvc<VCN; gvc++) begin:BFNV
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for(gvc=0; gvc<VCN; gvc++) begin:BFNV
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if(PD>1) begin:ACKG
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if(PD>1) begin:ACKG
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ctree #(.DW(SCN+1)) ACKT(.ci({vcdat[0],vcdad[0]}), .co(muxa[gvc]));
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ctree #(.DW(SCN+1)) ACKT(.ci({vcdat[0],vcdad[0]}), .co(muxa[gvc]));
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assign vcdad[PD*2-2][gvc] = {SCN{vcda[0][gvc]}};
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assign vcdad[PD*2-2][gvc] = {SCN{vcda[0][gvc]}};
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assign vcdat[PD*2-2] = vcda[0][gvc];
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assign vcdat[PD*2-2] = vcda[0][gvc];
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end else begin
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end else begin
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assign muxa[gvc] = vcda[0][gvc];
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assign muxa[gvc] = vcda[0][gvc];
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end
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end
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end // block: V
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end // block: V
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endgenerate
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endgenerate
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// the last two stages of VC buffers, separate flit type and data
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// the last two stages of VC buffers, separate flit type and data
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generate
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generate
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for(gbd=PD*2-2; gbd<PD*2; gbd++) begin:BFL2
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for(gbd=PD*2-2; gbd<PD*2; gbd++) begin:BFL2
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for(gvc=0; gvc<VCN; gvc++) begin:V
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for(gvc=0; gvc<VCN; gvc++) begin:V
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for(gsub=0; gsub<SCN; gsub++) begin:SC
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for(gsub=0; gsub<SCN; gsub++) begin:SC
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pipe4 #(.DW(2))
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pipe4 #(.DW(2))
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DP (
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DP (
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.ia ( vcdad[gbd][gvc][gsub] ),
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.ia ( vcdad[gbd][gvc][gsub] ),
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.o0 ( vcd0[gbd+1][gvc][gsub] ),
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.o0 ( vcd0[gbd+1][gvc][gsub] ),
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.o1 ( vcd1[gbd+1][gvc][gsub] ),
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.o1 ( vcd1[gbd+1][gvc][gsub] ),
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.o2 ( vcd2[gbd+1][gvc][gsub] ),
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.o2 ( vcd2[gbd+1][gvc][gsub] ),
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.o3 ( vcd3[gbd+1][gvc][gsub] ),
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.o3 ( vcd3[gbd+1][gvc][gsub] ),
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.i0 ( vcd0[gbd][gvc][gsub] ),
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.i0 ( vcd0[gbd][gvc][gsub] ),
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.i1 ( vcd1[gbd][gvc][gsub] ),
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.i1 ( vcd1[gbd][gvc][gsub] ),
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.i2 ( vcd2[gbd][gvc][gsub] ),
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.i2 ( vcd2[gbd][gvc][gsub] ),
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.i3 ( vcd3[gbd][gvc][gsub] ),
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.i3 ( vcd3[gbd][gvc][gsub] ),
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.oa ( vcdadn[gbd+1][gvc][gsub] )
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.oa ( vcdadn[gbd+1][gvc][gsub] )
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);
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);
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assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rst_n;
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assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rst_n;
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end // block: SC
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end // block: SC
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pipen #(.DW(FT))
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pipen #(.DW(FT))
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TP (
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TP (
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.d_in ( vcdt[gbd][gvc] ),
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.d_in ( vcdt[gbd][gvc] ),
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.d_in_a ( vcdat[gbd][gvc] ),
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.d_in_a ( vcdat[gbd][gvc] ),
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.d_out ( vcdt[gbd+1][gvc] ),
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.d_out ( vcdt[gbd+1][gvc] ),
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.d_out_a ( vcdatn[gbd+1][gvc] )
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.d_out_a ( vcdatn[gbd+1][gvc] )
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);
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);
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|
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assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rst_n;
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assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rst_n;
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|
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pipen #(.DW(2))
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pipen #(.DW(2))
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CTP (
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CTP (
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.d_in ( vcft[gbd][gvc] ),
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.d_in ( vcft[gbd][gvc] ),
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.d_in_a ( vcfta[gbd][gvc] ),
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.d_in_a ( vcfta[gbd][gvc] ),
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.d_out ( vcft[gbd+1][gvc] ),
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.d_out ( vcft[gbd+1][gvc] ),
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.d_out_a ( vcftan[gbd+1][gvc] )
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.d_out_a ( vcftan[gbd+1][gvc] )
|
);
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);
|
|
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assign vcftan[gbd+1][gvc] = (~vcfta[gbd+1][gvc])&rst_n;
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assign vcftan[gbd+1][gvc] = (~vcfta[gbd+1][gvc])&rst_n;
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end // block: V
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end // block: V
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end // block: BFL2
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end // block: BFL2
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|
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for(gvc=0; gvc<VCN; gvc++) begin:BFL2V
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for(gvc=0; gvc<VCN; gvc++) begin:BFL2V
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ctree #(.DW(SCN+2)) ACKT(.ci({vcfta[PD*2-2][gvc], vcdat[PD*2-2][gvc], vcdad[PD*2-2][gvc]}), .co(vcda[0][gvc]));
|
ctree #(.DW(SCN+2)) ACKT(.ci({vcfta[PD*2-2][gvc], vcdat[PD*2-2][gvc], vcdad[PD*2-2][gvc]}), .co(vcda[0][gvc]));
|
assign vcdat[PD*2][gvc] = vcda[1][gvc];
|
assign vcdat[PD*2][gvc] = vcda[1][gvc];
|
assign vcdad[PD*2][gvc] = {SCN{vcda[1][gvc]}};
|
assign vcdad[PD*2][gvc] = {SCN{vcda[1][gvc]}};
|
assign vcfta[PD*2][gvc] = swa[gvc];
|
assign vcfta[PD*2][gvc] = swa[gvc];
|
assign vcft[PD*2-2][gvc] = {vcdt[PD*2-2][gvc][FT-1], |vcdt[PD*2-2][gvc][FT-2:0]};
|
assign vcft[PD*2-2][gvc] = {vcdt[PD*2-2][gvc][FT-1], |vcdt[PD*2-2][gvc][FT-2:0]};
|
assign swr[gvc] = vcft[PD*2][gvc];
|
assign swr[gvc] = vcft[PD*2][gvc];
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
// the routing guide pipeline stage
|
// the routing guide pipeline stage
|
generate
|
generate
|
for(gvc=0; gvc<VCN; gvc++) begin:R
|
for(gvc=0; gvc<VCN; gvc++) begin:R
|
pipen #(.DW(SN))
|
pipen #(.DW(SN))
|
RP (
|
RP (
|
.d_in ( swrt[gvc] ),
|
.d_in ( swrt[gvc] ),
|
.d_in_a ( swa[gvc] ),
|
.d_in_a ( swa[gvc] ),
|
.d_out ( rtg[gvc] ),
|
.d_out ( rtg[gvc] ),
|
.d_out_a ( (~vcda[1][gvc])&rst_n )
|
.d_out_a ( (~vcda[1][gvc])&rst_n )
|
);
|
);
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
generate
|
generate
|
for(gvc=0; gvc<VCN; gvc++) begin:LPS
|
for(gvc=0; gvc<VCN; gvc++) begin:LPS
|
|
|
// credit control
|
// credit control
|
dc2 FCP (.q(cor[gvc]), .d(|rtg[gvc]), .a((~coa[gvc])&rst_n));
|
dc2 FCP (.q(cor[gvc]), .d(|rtg[gvc]), .a((~coa[gvc])&rst_n));
|
|
|
// output name conversation
|
// output name conversation
|
assign do0[gvc] = vcd0[PD*2][gvc];
|
assign do0[gvc] = vcd0[PD*2][gvc];
|
assign do1[gvc] = vcd1[PD*2][gvc];
|
assign do1[gvc] = vcd1[PD*2][gvc];
|
assign do2[gvc] = vcd2[PD*2][gvc];
|
assign do2[gvc] = vcd2[PD*2][gvc];
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assign do3[gvc] = vcd3[PD*2][gvc];
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assign do3[gvc] = vcd3[PD*2][gvc];
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assign dot[gvc] = vcdt[PD*2][gvc];
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assign dot[gvc] = vcdt[PD*2][gvc];
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assign dortg[gvc] = rtg[gvc];
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assign dortg[gvc] = rtg[gvc];
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c2 AC (.q(vcda[1][gvc]), .a0(cor[gvc]), .a1(doa[gvc]));
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c2 AC (.q(vcda[1][gvc]), .a0(cor[gvc]), .a1(doa[gvc]));
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end // block: LPS
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end // block: LPS
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endgenerate
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endgenerate
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// routing unit
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// routing unit
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rtu #(.VCN(VCN), .DIR(DIR), .SN(SN), .PD(PD))
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rtu #(.VCN(VCN), .DIR(DIR), .SN(SN), .PD(PD))
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RTC (
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RTC (
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.dia ( rua ),
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.dia ( rua ),
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.dort ( vcr ),
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.dort ( vcr ),
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.rst_n ( rst_n ),
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.rst_n ( rst_n ),
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.di0 ( di0m[3:0] ),
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.di0 ( di0m[3:0] ),
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.di1 ( di1m[3:0] ),
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.di1 ( di1m[3:0] ),
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.di2 ( di2m[3:0] ),
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.di2 ( di2m[3:0] ),
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.di3 ( di3m[3:0] ),
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.di3 ( di3m[3:0] ),
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.dit ( ditm ),
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.dit ( ditm ),
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.divc ( divcm ),
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.divc ( divcm ),
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.addrx ( addrx ),
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.addrx ( addrx ),
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.addry ( addry ),
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.addry ( addry ),
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.doa ( vcra )
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.doa ( vcra )
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);
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);
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endmodule // inpbuf
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endmodule // inpbuf
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